From patchwork Tue Nov 15 03:11:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13043176 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7E69C43219 for ; Tue, 15 Nov 2022 03:12:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232262AbiKODMX (ORCPT ); Mon, 14 Nov 2022 22:12:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232218AbiKODLx (ORCPT ); Mon, 14 Nov 2022 22:11:53 -0500 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D539F014 for ; Mon, 14 Nov 2022 19:11:50 -0800 (PST) X-ASG-Debug-ID: 1668481908-1eb14e7e6289900001-0c9NHn Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx2.zhaoxin.com with ESMTP id QaNre0bD6YF8PyiC (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 15 Nov 2022 11:11:48 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:11:48 +0800 Received: from localhost.localdomain (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:11:44 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , , , CC: , , , leoliu-oc Subject: [PATCH v2 1/5] ACPI/APEI: Add apei_hest_parse_aer() Date: Tue, 15 Nov 2022 11:11:43 +0800 X-ASG-Orig-Subj: [PATCH v2 1/5] ACPI/APEI: Add apei_hest_parse_aer() Message-ID: <20221115031143.1666653-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Originating-IP: [10.32.64.1] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1668481908 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 7893 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0025 1.0000 -2.0046 X-Barracuda-Spam-Score: -2.00 X-Barracuda-Spam-Status: No, SCORE=-2.00 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.102147 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: leoliu-oc apei_hest_parse_aer() is used to parse and extract register values from HEST PCIe AER structures. Signed-off-by: leoliu-oc --- drivers/acpi/apei/hest.c | 115 ++++++++++++++++++++++++++++++++++++++- include/acpi/actbl1.h | 69 +++++++++++++++++++++++ include/acpi/apei.h | 7 +++ 3 files changed, 189 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c index 6aef1ee5e1bd..ab1ffe6923ce 100644 --- a/drivers/acpi/apei/hest.c +++ b/drivers/acpi/apei/hest.c @@ -25,7 +25,7 @@ #include #include #include - +#include #include "apei-internal.h" #define HEST_PFX "HEST: " @@ -86,7 +86,50 @@ static int hest_esrc_len(struct acpi_hest_header *hest_hdr) return len; }; -typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); +static bool hest_source_is_pcie_aer(struct acpi_hest_header *hest_hdr) +{ + switch (hest_hdr->type) { + case ACPI_HEST_TYPE_AER_ROOT_PORT: + case ACPI_HEST_TYPE_AER_ENDPOINT: + case ACPI_HEST_TYPE_AER_BRIDGE: + return true; + default: + return false; + } +} + +static bool hest_match_type(struct acpi_hest_header *hest_hdr, + struct pci_dev *dev) +{ + u16 hest_type = hest_hdr->type; + u8 pcie_type = pci_pcie_type(dev); + + if ((hest_type == ACPI_HEST_TYPE_AER_ROOT_PORT && + pcie_type == PCI_EXP_TYPE_ROOT_PORT) || + (hest_type == ACPI_HEST_TYPE_AER_ENDPOINT && + pcie_type == PCI_EXP_TYPE_ENDPOINT) || + (hest_type == ACPI_HEST_TYPE_AER_BRIDGE && + (pcie_type == PCI_EXP_TYPE_PCI_BRIDGE || pcie_type == PCI_EXP_TYPE_PCIE_BRIDGE))) + return true; + return false; +} + +static bool hest_match_pci_devfn(struct acpi_hest_aer_common *p, + struct pci_dev *pci) +{ + return ACPI_HEST_SEGMENT(p->bus) == pci_domain_nr(pci->bus) && + ACPI_HEST_BUS(p->bus) == pci->bus->number && + p->device == PCI_SLOT(pci->devfn) && + p->function == PCI_FUNC(pci->devfn); +} + +static bool hest_match_pci(struct acpi_hest_header *hest_hdr, + struct acpi_hest_aer_common *p, struct pci_dev *pci) +{ + if (hest_match_type(hest_hdr, pci)) + return hest_match_pci_devfn(p, pci); + return false; +} static int apei_hest_parse(apei_hest_func_t func, void *data) { @@ -124,6 +167,74 @@ static int apei_hest_parse(apei_hest_func_t func, void *data) return 0; } +/* + * apei_hest_parse_aer - Find the AER structure in the HEST and + * match it with the PCIe device. + * + * @hest_hdr: To save the ACPI AER error source in HEST + * + * Return 1 if the PCIe dev matched with the ACPI AER error source in + * HEST, else return 0. + */ +int apei_hest_parse_aer(struct acpi_hest_header *hest_hdr, void *data) +{ + struct acpi_hest_parse_aer_info *info = data; + struct acpi_hest_aer_endpoint *acpi_hest_aer_endpoint = NULL; + struct acpi_hest_aer_root_port *acpi_hest_aer_root_port = NULL; + struct acpi_hest_aer_for_bridge *acpi_hest_aer_for_bridge = NULL; + + if (!hest_source_is_pcie_aer(hest_hdr)) + return 0; + + switch (hest_hdr->type) { + case ACPI_HEST_TYPE_AER_ROOT_PORT: + acpi_hest_aer_root_port = (struct acpi_hest_aer_root_port *)(hest_hdr + 1); + if (acpi_hest_aer_root_port->flags & ACPI_HEST_GLOBAL) { + if (hest_match_type(hest_hdr, info->pci_dev)) { + info->acpi_hest_aer_root_port = acpi_hest_aer_root_port; + info->hest_matched_with_dev = 1; + } + } else if (hest_match_pci(hest_hdr, + (struct acpi_hest_aer_common *)acpi_hest_aer_root_port, + info->pci_dev)) { + info->acpi_hest_aer_root_port = acpi_hest_aer_root_port; + info->hest_matched_with_dev = 1; + } + break; + case ACPI_HEST_TYPE_AER_ENDPOINT: + acpi_hest_aer_endpoint = (struct acpi_hest_aer_endpoint *)(hest_hdr + 1); + if (acpi_hest_aer_endpoint->flags & ACPI_HEST_GLOBAL) { + if (hest_match_type(hest_hdr, info->pci_dev)) { + info->acpi_hest_aer_endpoint = acpi_hest_aer_endpoint; + info->hest_matched_with_dev = 1; + } + } else if (hest_match_pci(hest_hdr, + (struct acpi_hest_aer_common *)acpi_hest_aer_endpoint, + info->pci_dev)) { + info->acpi_hest_aer_endpoint = acpi_hest_aer_endpoint; + info->hest_matched_with_dev = 1; + } + break; + case ACPI_HEST_TYPE_AER_BRIDGE: + acpi_hest_aer_for_bridge = (struct acpi_hest_aer_for_bridge *)(hest_hdr + 1); + if (acpi_hest_aer_for_bridge->flags & ACPI_HEST_GLOBAL) { + if (hest_match_type(hest_hdr, info->pci_dev)) { + info->acpi_hest_aer_for_bridge = acpi_hest_aer_for_bridge; + info->hest_matched_with_dev = 1; + } + } else if (hest_match_pci(hest_hdr, + (struct acpi_hest_aer_common *)acpi_hest_aer_for_bridge, + info->pci_dev)) { + info->acpi_hest_aer_for_bridge = acpi_hest_aer_for_bridge; + info->hest_matched_with_dev = 1; + } + break; + default: + break; + } + return info->hest_matched_with_dev; +} + /* * Check if firmware advertises firmware first mode. We need FF bit to be set * along with a set of MC banks which work in FF mode. diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 15c78678c5d3..a3540133ddce 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1385,6 +1385,75 @@ struct acpi_hest_aer_bridge { u32 advanced_capabilities2; }; +struct acpi_hest_parse_aer_info { + struct pci_dev *pci_dev; + int hest_matched_with_dev; + struct acpi_hest_aer_endpoint *acpi_hest_aer_endpoint; + struct acpi_hest_aer_root_port *acpi_hest_aer_root_port; + struct acpi_hest_aer_for_bridge *acpi_hest_aer_for_bridge; +}; + +/* HEST Sub-structure for PCIe Root Port Structure (6) */ + +struct acpi_hest_aer_root_port { + u16 reserved1; + u8 flags; + u8 enabled; + u32 records_to_preallocate; + u32 max_sections_per_record; + u32 bus; + u16 device; + u16 function; + u16 device_control; + u16 reserved2; + u32 uncorrectable_mask; + u32 uncorrectable_severity; + u32 correctable_mask; + u32 advanced_capabilities; + u32 root_error_command; +}; + +/* HEST Sub-structure for PCIe Endpoint Structure (7) */ + +struct acpi_hest_aer_endpoint { + u16 reserved1; + u8 flags; + u8 enabled; + u32 records_to_preallocate; + u32 max_sections_per_record; + u32 bus; + u16 device; + u16 function; + u16 device_control; + u16 reserved2; + u32 uncorrectable_mask; + u32 uncorrectable_severity; + u32 correctable_mask; + u32 advanced_capabilities; +}; + +/* HEST Sub-structure for PCIe/PCI-X Bridge Structure (8) */ + +struct acpi_hest_aer_for_bridge { + u16 reserved1; + u8 flags; + u8 enabled; + u32 records_to_preallocate; + u32 max_sections_per_record; + u32 bus; + u16 device; + u16 function; + u16 device_control; + u16 reserved2; + u32 uncorrectable_mask; + u32 uncorrectable_severity; + u32 correctable_mask; + u32 advanced_capabilities; + u32 uncorrectable_mask2; + u32 uncorrectable_severity2; + u32 advanced_capabilities2; +}; + /* 9: Generic Hardware Error Source */ struct acpi_hest_generic { diff --git a/include/acpi/apei.h b/include/acpi/apei.h index dc60f7db5524..8a0b2b9edbaf 100644 --- a/include/acpi/apei.h +++ b/include/acpi/apei.h @@ -33,10 +33,17 @@ void __init acpi_ghes_init(void); static inline void acpi_ghes_init(void) { } #endif +typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); + #ifdef CONFIG_ACPI_APEI void __init acpi_hest_init(void); +int apei_hest_parse_aer(struct acpi_hest_header *hest_hdr, void *data); #else static inline void acpi_hest_init(void) { } +static inline int apei_hest_parse_aer(struct acpi_hest_header *hest_hdr, void *data) +{ + return -EINVAL; +} #endif int erst_write(const struct cper_record_header *record); From patchwork Tue Nov 15 03:11:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13043175 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E85F2C43217 for ; Tue, 15 Nov 2022 03:12:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231908AbiKODMW (ORCPT ); Mon, 14 Nov 2022 22:12:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237444AbiKODMH (ORCPT ); Mon, 14 Nov 2022 22:12:07 -0500 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE24A2BF8 for ; Mon, 14 Nov 2022 19:12:05 -0800 (PST) X-ASG-Debug-ID: 1668481921-086e2353248d070001-0c9NHn Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx1.zhaoxin.com with ESMTP id AfkY9x5666383doF (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 15 Nov 2022 11:12:01 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:12:01 +0800 Received: from localhost.localdomain (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:11:58 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , , , CC: , , , leoliu-oc Subject: [PATCH v2 2/5] ACPI/APEI: Remove static from apei_hest_parse() Date: Tue, 15 Nov 2022 11:11:57 +0800 X-ASG-Orig-Subj: [PATCH v2 2/5] ACPI/APEI: Remove static from apei_hest_parse() Message-ID: <20221115031157.1666789-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Originating-IP: [10.32.64.1] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1668481921 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1632 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0890 1.0000 -1.4588 X-Barracuda-Spam-Score: -1.46 X-Barracuda-Spam-Status: No, SCORE=-1.46 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.102147 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: leoliu-oc Each dev with AER capability needs to call the apei_hest_parse function to match and extract register values from HEST PCIe AER structures. Therefore, remove static from apei_hest_parse() so that it can be called in another file. Signed-off-by: leoliu-oc --- drivers/acpi/apei/hest.c | 2 +- include/acpi/apei.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c index ab1ffe6923ce..1ac9afbff448 100644 --- a/drivers/acpi/apei/hest.c +++ b/drivers/acpi/apei/hest.c @@ -131,7 +131,7 @@ static bool hest_match_pci(struct acpi_hest_header *hest_hdr, return false; } -static int apei_hest_parse(apei_hest_func_t func, void *data) +int apei_hest_parse(apei_hest_func_t func, void *data) { struct acpi_hest_header *hest_hdr; int i, rc, len; diff --git a/include/acpi/apei.h b/include/acpi/apei.h index 8a0b2b9edbaf..e7896491ae52 100644 --- a/include/acpi/apei.h +++ b/include/acpi/apei.h @@ -37,9 +37,11 @@ typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); #ifdef CONFIG_ACPI_APEI void __init acpi_hest_init(void); +int apei_hest_parse(apei_hest_func_t func, void *data); int apei_hest_parse_aer(struct acpi_hest_header *hest_hdr, void *data); #else static inline void acpi_hest_init(void) { } +static inline int apei_hest_parse(apei_hest_func_t func, void *data) { return -EINVAL; } static inline int apei_hest_parse_aer(struct acpi_hest_header *hest_hdr, void *data) { return -EINVAL; From patchwork Tue Nov 15 03:12:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13043177 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92EE1C4332F for ; Tue, 15 Nov 2022 03:13:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232449AbiKODNF (ORCPT ); Mon, 14 Nov 2022 22:13:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232467AbiKODMy (ORCPT ); Mon, 14 Nov 2022 22:12:54 -0500 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D071912A92 for ; Mon, 14 Nov 2022 19:12:51 -0800 (PST) X-ASG-Debug-ID: 1668481969-1eb14e7e6489960001-0c9NHn Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx2.zhaoxin.com with ESMTP id kWOIIZDAWmtr9SHg (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 15 Nov 2022 11:12:49 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:12:48 +0800 Received: from localhost.localdomain (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:12:45 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , , , CC: , , , leoliu-oc Subject: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Date: Tue, 15 Nov 2022 11:12:44 +0800 X-ASG-Orig-Subj: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Message-ID: <20221115031244.1667093-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Originating-IP: [10.32.64.1] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1668481969 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1313 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0273 1.0000 -1.8440 X-Barracuda-Spam-Score: -1.84 X-Barracuda-Spam-Status: No, SCORE=-1.84 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.102147 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: leoliu-oc Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Signed-off-by: leoliu-oc Acked-by: Bjorn Helgaas --- include/uapi/linux/pci_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..37f3baa336d7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -799,6 +799,11 @@ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ +/* PCIe advanced error reporting extended capabilities for PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ From patchwork Tue Nov 15 03:12:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13043178 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7886DC4332F for ; Tue, 15 Nov 2022 03:13:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232564AbiKODNQ (ORCPT ); Mon, 14 Nov 2022 22:13:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232334AbiKODNI (ORCPT ); Mon, 14 Nov 2022 22:13:08 -0500 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A244B853 for ; Mon, 14 Nov 2022 19:13:06 -0800 (PST) X-ASG-Debug-ID: 1668481982-086e2353278d0b0001-0c9NHn Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx1.zhaoxin.com with ESMTP id sVtGCQrlOKcgKXS8 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 15 Nov 2022 11:13:02 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:13:02 +0800 Received: from localhost.localdomain (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:12:59 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , , , CC: , , , leoliu-oc Subject: [PATCH v2 4/5] ACPI/PCI: Add pci_acpi_program_hest_aer_params() Date: Tue, 15 Nov 2022 11:12:58 +0800 X-ASG-Orig-Subj: [PATCH v2 4/5] ACPI/PCI: Add pci_acpi_program_hest_aer_params() Message-ID: <20221115031258.1667231-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Originating-IP: [10.32.64.1] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1668481982 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5681 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0125 1.0000 -1.9397 X-Barracuda-Spam-Score: -1.94 X-Barracuda-Spam-Status: No, SCORE=-1.94 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.102147 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: leoliu-oc The extracted register values from HEST PCI Express AER structures are written to AER Capabilities. Signed-off-by: leoliu-oc --- drivers/pci/pci-acpi.c | 92 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 5 +++ 2 files changed, 97 insertions(+) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index a46fec776ad7..8b737b403855 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "pci.h" /* @@ -783,6 +784,97 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) return -ENODEV; } +/* + * program_aer_structure_to_aer_registers - Write the AER structure to + * the corresponding dev's AER registers. + * + * @info - the AER structure information + * + */ +static void program_aer_structure_to_aer_registers(struct acpi_hest_parse_aer_info info) +{ + u32 uncorrectable_mask; + u32 uncorrectable_severity; + u32 correctable_mask; + u32 advanced_capabilities; + u32 root_error_command; + u32 uncorrectable_mask2; + u32 uncorrectable_severity2; + u32 advanced_capabilities2; + int port_type; + int pos; + struct pci_dev *dev; + + dev = info.pci_dev; + port_type = pci_pcie_type(dev); + + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return; + + if (port_type == PCI_EXP_TYPE_ROOT_PORT) { + uncorrectable_mask = info.acpi_hest_aer_root_port->uncorrectable_mask; + uncorrectable_severity = info.acpi_hest_aer_root_port->uncorrectable_severity; + correctable_mask = info.acpi_hest_aer_root_port->correctable_mask; + advanced_capabilities = info.acpi_hest_aer_root_port->advanced_capabilities; + root_error_command = info.acpi_hest_aer_root_port->root_error_command; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncorrectable_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncorrectable_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, correctable_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, advanced_capabilities); + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_error_command); + } else if (port_type == PCI_EXP_TYPE_ENDPOINT) { + uncorrectable_mask = info.acpi_hest_aer_endpoint->uncorrectable_mask; + uncorrectable_severity = info.acpi_hest_aer_endpoint->uncorrectable_severity; + correctable_mask = info.acpi_hest_aer_endpoint->correctable_mask; + advanced_capabilities = info.acpi_hest_aer_endpoint->advanced_capabilities; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncorrectable_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncorrectable_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, correctable_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, advanced_capabilities); + } else if ((pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) || + (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE)) { + uncorrectable_mask = info.acpi_hest_aer_for_bridge->uncorrectable_mask; + uncorrectable_severity = info.acpi_hest_aer_for_bridge->uncorrectable_severity; + correctable_mask = info.acpi_hest_aer_for_bridge->correctable_mask; + advanced_capabilities = info.acpi_hest_aer_for_bridge->advanced_capabilities; + uncorrectable_mask2 = info.acpi_hest_aer_for_bridge->uncorrectable_mask2; + uncorrectable_severity2 = info.acpi_hest_aer_for_bridge->uncorrectable_severity2; + advanced_capabilities2 = info.acpi_hest_aer_for_bridge->advanced_capabilities2; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncorrectable_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncorrectable_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, correctable_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, advanced_capabilities); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncorrectable_mask2); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncorrectable_severity2); + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, advanced_capabilities2); + } +} + +int pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + struct acpi_hest_parse_aer_info info = { + .pci_dev = dev, + .hest_matched_with_dev = 0, + .acpi_hest_aer_endpoint = NULL, + .acpi_hest_aer_root_port = NULL, + .acpi_hest_aer_for_bridge = NULL, + }; + + if (!pci_is_pcie(dev)) + return -ENODEV; + + apei_hest_parse(apei_hest_parse_aer, &info); + if (info.hest_matched_with_dev == 1) + program_aer_structure_to_aer_registers(info); + else + return -ENODEV; + return 0; +} + /** * pciehp_is_native - Check whether a hotplug port is handled by the OS * @bridge: Hotplug port to check diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b1ebb7ab8805..cb854fb87bb9 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -710,6 +710,7 @@ void acpi_pci_refresh_power_state(struct pci_dev *dev); int acpi_pci_wakeup(struct pci_dev *dev, bool enable); bool acpi_pci_need_resume(struct pci_dev *dev); pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); +int pci_acpi_program_hest_aer_params(struct pci_dev *dev); #else static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { @@ -749,6 +750,10 @@ static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) { return PCI_POWER_ERROR; } +static inline int pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + return -ENODEV; +} #endif #ifdef CONFIG_PCIEASPM From patchwork Tue Nov 15 03:13:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13043179 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24B39C4332F for ; Tue, 15 Nov 2022 03:13:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232467AbiKODN1 (ORCPT ); Mon, 14 Nov 2022 22:13:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236320AbiKODNX (ORCPT ); Mon, 14 Nov 2022 22:13:23 -0500 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10CD9BCB4 for ; Mon, 14 Nov 2022 19:13:21 -0800 (PST) X-ASG-Debug-ID: 1668481999-1eb14e7e63898a0001-0c9NHn Received: from ZXSHMBX3.zhaoxin.com (ZXSHMBX3.zhaoxin.com [10.28.252.165]) by mx2.zhaoxin.com with ESMTP id AEK4qm34JgfWn1ro (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 15 Nov 2022 11:13:19 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:13:19 +0800 Received: from localhost.localdomain (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:13:16 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , , , CC: , , , leoliu-oc Subject: [PATCH v2 5/5] ACPI/PCI: Config PCIe devices's AER register Date: Tue, 15 Nov 2022 11:13:15 +0800 X-ASG-Orig-Subj: [PATCH v2 5/5] ACPI/PCI: Config PCIe devices's AER register Message-ID: <20221115031315.1667355-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Originating-IP: [10.32.64.1] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1668481999 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 791 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.3900 1.0000 -0.0264 X-Barracuda-Spam-Score: -0.03 X-Barracuda-Spam-Status: No, SCORE=-0.03 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.102147 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: leoliu-oc Call the func pci_acpi_program_hest_aer_params() for every PCIe device. Extracting register values from HEST PCIe AER structures and programming them into AER Capabilities are implemented in this function. Signed-off-by: leoliu-oc --- drivers/pci/probe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b66fa42c4b1f..02bf9180e96d 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2263,6 +2263,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_serr(dev); pci_acpi_program_hp_params(dev); + pci_acpi_program_hest_aer_params(dev); } static void pci_release_capabilities(struct pci_dev *dev)