From patchwork Wed Nov 16 14:30:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyan Thota X-Patchwork-Id: 13045307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B74E8C433FE for ; Wed, 16 Nov 2022 14:31:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 540F010E4B7; Wed, 16 Nov 2022 14:31:05 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA00E10E4AD; Wed, 16 Nov 2022 14:30:53 +0000 (UTC) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AGBxHTu026233; Wed, 16 Nov 2022 14:30:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=FcBLrYDz5MLJ+JQbxLtt5oyeeAzeEZbn+lgGXcvd7CA=; b=Vl/SUlrY5cX/WB+K3cvDKUvGwJD/HmIl8X0vMXBBmAi2OOmxk9HQflN/kuG6J0dWSmzT 2EnA4NfTEYqMU/hE+HwJpPUEIvfrVy+9ZnIUZWo0LJDPrC9DesHSLjd+ADuBgr/LE81S exPDnPklUTSMyNy/dMM6kPBkV8mIXpyNb47jg5rsBbJliOHtlE09gY3UmU4j4Bm9R87l 13C5ikH6x+FEVicdfGkc4YAEPyNqGIoKIYeqY2+V5hrUn9KkILx1fXOp/f1jvuN2lnhy GF3kmxbjd2X2oV3w5wAIC8BiiY9Ur1KB3gbuCnmohnbb6nT6+TVg5I9cNTNQXwMpTOgZ RQ== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kvyfm8aq3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 16 Nov 2022 14:30:49 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 2AGEUjvo008039; Wed, 16 Nov 2022 14:30:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3kt4jkxbcb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 16 Nov 2022 14:30:45 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2AGEUjID008030; Wed, 16 Nov 2022 14:30:45 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 2AGEUjFU008026; Wed, 16 Nov 2022 14:30:45 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id 9953448A0; Wed, 16 Nov 2022 06:30:44 -0800 (PST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder Date: Wed, 16 Nov 2022 06:30:38 -0800 Message-Id: <1668609040-2549-2-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1668609040-2549-1-git-send-email-quic_kalyant@quicinc.com> References: <1668609040-2549-1-git-send-email-quic_kalyant@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bX5IMCjNQ7Do9QsEjm83_8lsHFm115xW X-Proofpoint-ORIG-GUID: bX5IMCjNQ7Do9QsEjm83_8lsHFm115xW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-16_03,2022-11-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211160100 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kalyan Thota , robdclark@chromium.org, dianders@chromium.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, quic_vpolimer@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Pin each crtc with one encoder. This arrangement will disallow crtc switching between encoders and also will facilitate to advertise certain features on crtc based on encoder type. Changes in v1: - use drm_for_each_encoder macro while iterating through encoder list (Dmitry) Changes in v2: - make sure no encoder miss to have a crtc (Dmitry) - revisit various factors in deciding the crtc count such as num_mixers, num_sspp (Dmitry) Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 7a5fabc..4784db8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -763,7 +763,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) drm_for_each_encoder(encoder, dev) num_encoders++; - max_crtc_count = min(catalog->mixer_count, num_encoders); + max_crtc_count = num_encoders; /* Create the planes, keeping track of one primary/cursor per crtc */ for (i = 0; i < catalog->sspp_count; i++) { @@ -795,22 +795,25 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) primary_planes[primary_planes_idx++] = plane; } - max_crtc_count = min(max_crtc_count, primary_planes_idx); + /* + * All the platforms should have at least 1 primary plane for an + * encoder. The below warn should help in setting up the catalog + */ + WARN_ON(num_encoders > primary_planes_idx); /* Create one CRTC per encoder */ - for (i = 0; i < max_crtc_count; i++) { + i = 0; + drm_for_each_encoder(encoder, dev) { crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); if (IS_ERR(crtc)) { ret = PTR_ERR(crtc); return ret; } priv->crtcs[priv->num_crtcs++] = crtc; + encoder->possible_crtcs = 1 << drm_crtc_index(crtc); + i++; } - /* All CRTCs are compatible with all encoders */ - drm_for_each_encoder(encoder, dev) - encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; - return 0; } From patchwork Wed Nov 16 14:30:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyan Thota X-Patchwork-Id: 13045305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BCF7C43217 for ; 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Wed, 16 Nov 2022 14:30:50 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 2AGETMLw005215; Wed, 16 Nov 2022 14:30:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3kt4jkxbcm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 16 Nov 2022 14:30:46 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2AGEUklM008049; Wed, 16 Nov 2022 14:30:46 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 2AGEUksx008046; Wed, 16 Nov 2022 14:30:46 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id 921D148C2; Wed, 16 Nov 2022 06:30:45 -0800 (PST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/3] drm/msm/disp/dpu1: add helper to know if display is pluggable Date: Wed, 16 Nov 2022 06:30:39 -0800 Message-Id: <1668609040-2549-3-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1668609040-2549-1-git-send-email-quic_kalyant@quicinc.com> References: <1668609040-2549-1-git-send-email-quic_kalyant@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mkKminuOSsAhzOcCXC25zH4He9Kt9hWW X-Proofpoint-ORIG-GUID: mkKminuOSsAhzOcCXC25zH4He9Kt9hWW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-16_03,2022-11-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 mlxlogscore=997 phishscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211160100 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kalyan Thota , robdclark@chromium.org, dianders@chromium.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, quic_vpolimer@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since DRM encoder type for few encoders can be similar (like eDP and DP) find out if the interface supports HPD from encoder bridge to differentiate between builtin and pluggable displays. Changes in v1: - add connector type in the disp_info (Dmitry) - add helper functions to know encoder type - update commit text reflecting the change Changes in v2: - avoid hardcode of connector type for DSI as it may not be true (Dmitry) - get the HPD information from encoder bridge Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 6 ++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 9c6817b..be93269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "msm_drv.h" #include "dpu_kms.h" @@ -217,6 +218,21 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = { 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 }; +bool dpu_encoder_is_pluggable(struct drm_encoder *encoder) +{ + struct drm_bridge *bridge; + int ops = 0; + + if (!encoder) + return false; + + /* Get last bridge in the chain to determine pluggable state */ + drm_for_each_bridge_in_chain(encoder, bridge) + if (!drm_bridge_get_next_bridge(bridge)) + ops = bridge->ops; + + return ops & DRM_BRIDGE_OP_HPD; +} bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 9e7236e..691ab57 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -224,4 +224,10 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, */ bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc); +/** + * dpu_encoder_is_pluggable - find if the encoder is of type pluggable + * @drm_enc: Pointer to previously created drm encoder structure + */ +bool dpu_encoder_is_pluggable(struct drm_encoder *drm_enc); + #endif /* __DPU_ENCODER_H__ */ From patchwork Wed Nov 16 14:30:40 2022 Content-Type: text/plain; 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Wed, 16 Nov 2022 14:30:48 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3kt4jkxbcq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 16 Nov 2022 14:30:48 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2AGEUl70008082; Wed, 16 Nov 2022 14:30:47 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 2AGEUlK3008081; Wed, 16 Nov 2022 14:30:47 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id 9976A48A0; Wed, 16 Nov 2022 06:30:46 -0800 (PST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] drm/msm/disp/dpu1: add color management support for the crtc Date: Wed, 16 Nov 2022 06:30:40 -0800 Message-Id: <1668609040-2549-4-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1668609040-2549-1-git-send-email-quic_kalyant@quicinc.com> References: <1668609040-2549-1-git-send-email-quic_kalyant@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BKSbHIPyWNFRQ9hPBQbJtVHLLG1_1Q0- X-Proofpoint-ORIG-GUID: BKSbHIPyWNFRQ9hPBQbJtVHLLG1_1Q0- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-16_03,2022-11-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211160100 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kalyan Thota , robdclark@chromium.org, dianders@chromium.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, quic_vpolimer@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add color management support for the crtc provided there are enough dspps that can be allocated from the catalog. Changes in v1: - cache color enabled state in the dpu crtc obj (Dmitry) - simplify dspp allocation while creating crtc (Dmitry) - register for color when crtc is created (Dmitry) Changes in v2: - avoid primary encoders in the documentation (Dmitry) Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 58 ++++++++++++++++++++++++++++- 4 files changed, 69 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 4170fbe..ca4c3b3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { /* initialize crtc */ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, - struct drm_plane *cursor) + struct drm_plane *cursor, unsigned long features) { struct drm_crtc *crtc = NULL; struct dpu_crtc *dpu_crtc = NULL; @@ -1583,6 +1583,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, crtc = &dpu_crtc->base; crtc->dev = dev; + dpu_crtc->color_enabled = features & BIT(DPU_DSPP_PCC); spin_lock_init(&dpu_crtc->spin_lock); atomic_set(&dpu_crtc->frame_pending, 0); @@ -1604,7 +1605,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); - drm_crtc_enable_color_mgmt(crtc, 0, true, 0); + drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled, 0); /* save user friendly CRTC name for later */ snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 539b68b..342f9ae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -136,6 +136,7 @@ struct dpu_crtc_frame_event { * @enabled : whether the DPU CRTC is currently enabled. updated in the * commit-thread, not state-swap time which is earlier, so * safe to make decisions on during VBLANK on/off work + * @color_enabled : whether crtc supports color management * @feature_list : list of color processing features supported on a crtc * @active_list : list of color processing features are active * @dirty_list : list of color processing features are dirty @@ -164,7 +165,7 @@ struct dpu_crtc { u64 play_count; ktime_t vblank_cb_time; bool enabled; - + bool color_enabled; struct list_head feature_list; struct list_head active_list; struct list_head dirty_list; @@ -269,10 +270,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc); * @dev: dpu device * @plane: base plane * @cursor: cursor plane + * @features: color features * @Return: new crtc object or error */ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, - struct drm_plane *cursor); + struct drm_plane *cursor, unsigned long features); /** * dpu_crtc_register_custom_event - api for enabling/disabling crtc event diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index be93269..7f1cfc5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -561,6 +561,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) static struct msm_display_topology dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, + struct dpu_crtc *dpu_crtc, struct drm_display_mode *mode) { struct msm_display_topology topology = {0}; @@ -589,7 +590,7 @@ static struct msm_display_topology dpu_encoder_get_topology( else topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { + if (dpu_crtc->color_enabled) { if (dpu_kms->catalog->dspp && (dpu_kms->catalog->dspp_count >= topology.num_lm)) topology.num_dspp = topology.num_lm; @@ -624,6 +625,7 @@ static int dpu_encoder_virt_atomic_check( struct drm_display_mode *adj_mode; struct msm_display_topology topology; struct dpu_global_state *global_state; + struct dpu_crtc *dpu_crtc; int i = 0; int ret = 0; @@ -634,6 +636,7 @@ static int dpu_encoder_virt_atomic_check( } dpu_enc = to_dpu_encoder_virt(drm_enc); + dpu_crtc = to_dpu_crtc(crtc_state->crtc); DPU_DEBUG_ENC(dpu_enc, "\n"); priv = drm_enc->dev->dev_private; @@ -659,7 +662,7 @@ static int dpu_encoder_virt_atomic_check( } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, dpu_crtc, adj_mode); /* Reserve dynamic resources now. */ if (!ret) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 4784db8..84e948d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -732,7 +732,58 @@ static int _dpu_kms_setup_displays(struct drm_device *dev, return rc; } +/** + * _dpu_kms_populate_dspp_features - Evaluate how many dspps pairs can be facilitated + * to enable color features for encoder and assign + * color features preferring primary + * @dpu_kms: Pointer to dpu kms structure + * @features: Pointer to feature array + * + * Baring single entry, if at least 2 dspps are available in the catalogue, + * then color can be enabled for that crtc + */ +static void _dpu_kms_populate_dspp_features(struct dpu_kms *dpu_kms, + unsigned long *features) +{ + struct drm_encoder *encoder; + u32 enc_mask = 0; + u32 num_dspps = dpu_kms->catalog->dspp_count; + + if (!num_dspps) + return; + else if (num_dspps > 1) + num_dspps /= 2; + + /* Ensure all builtin displays get first allocation of color */ + drm_for_each_encoder(encoder, dpu_kms->dev) { + if (!dpu_encoder_is_pluggable(encoder) && + encoder->encoder_type != DRM_MODE_ENCODER_VIRTUAL) { + if (num_dspps) { + features[encoder->index] = + dpu_kms->catalog->dspp->features; + num_dspps--; + } + } else if (dpu_encoder_is_pluggable(encoder)) { + enc_mask |= drm_encoder_mask(encoder); + } + } + + /* if color resources are exhausted return */ + if (!num_dspps) + return; + + /* Add color for pluggable displays after builtin on availability */ + drm_for_each_encoder_mask(encoder, dpu_kms->dev, enc_mask) { + if (num_dspps) { + features[encoder->index] = + dpu_kms->catalog->dspp->features; + num_dspps--; + } + } +} + #define MAX_PLANES 20 +#define MAX_ENCODERS 10 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) { struct drm_device *dev; @@ -747,6 +798,8 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; int max_crtc_count; + unsigned long features[MAX_ENCODERS] = {0}; + dev = dpu_kms->dev; priv = dev->dev_private; catalog = dpu_kms->catalog; @@ -801,10 +854,13 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) */ WARN_ON(num_encoders > primary_planes_idx); + _dpu_kms_populate_dspp_features(dpu_kms, features); + /* Create one CRTC per encoder */ i = 0; drm_for_each_encoder(encoder, dev) { - crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); + crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i], + features[encoder->index]); if (IS_ERR(crtc)) { ret = PTR_ERR(crtc); return ret;