From patchwork Thu Nov 17 00:30:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13045960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 903A5C4332F for ; Thu, 17 Nov 2022 00:28:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA3DD10E4F9; Thu, 17 Nov 2022 00:28:12 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8420F10E4F9 for ; Thu, 17 Nov 2022 00:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668644889; x=1700180889; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=HJRsAR7ALfFAIfBVGeVVOWZRiVo2HC1pL4yIiJc8RIU=; b=ZWsx1KTf5+LE/LEJz6/Q0/TbYcBDfp8Fgl+vmpiyfIZKvufZvg150BR3 G4JE9vGh4OLxbCPY+o2zA9npDR04ffGErOeO7EYMbcmvWJuQwNi2CO05r wu/ubICjjNyPNR1MyENcay1AP/tZCjNeAxKo5rKVruS52c29UHfN3wjII Qd7SomJBYXpJl8mBMOgYLS4IukDYsiglxnVAMBdO8TGWkhF211JXI2o9o ycKRxq/Zg1jRYp1bjVSI1ZlqyoZ7cuyA0V49Zy77cowZdDQm/omhncsYB Rs9At5nWDBJAtcYz+NCycFRmdspTf7u3sSmU26PBpthFQ8ek2ia3le2Mb g==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="312722092" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="312722092" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 16:27:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="781985081" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="781985081" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2022 16:27:48 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Nov 2022 16:30:13 -0800 Message-Id: <20221117003018.1433115-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> References: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 1/6] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In preparation for future MTL-PXP feature support, PXP control context should only valid on the correct gt tile. Depending on the device-info this depends on which tile owns the VEBOX and KCR. PXP is still a global feature though (despite its control-context located in the owning GT structure). Additionally, we find that the HAS_PXP macro is only used within the pxp module, That said, lets drop that HAS_PXP macro altogether and replace it with a more fitting named intel_gtpxp_is_supported and helpers so that PXP init/fini can use to verify if the referenced gt supports PXP or teelink. Add TODO for Meteorlake that will come in future series. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/i915_drv.h | 4 ---- drivers/gpu/drm/i915/pxp/intel_pxp.c | 22 ++++++++++++++------ drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++ drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- 4 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7e3820d2c404..0616e5f0bd31 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -933,10 +933,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) -#define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \ - INTEL_INFO(dev_priv)->has_pxp) && \ - VDBOX_MASK(to_gt(dev_priv))) - #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 5efe61f67546..d993e752bd36 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -44,6 +44,20 @@ struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) return container_of(pxp, struct intel_gt, pxp); } +static bool _gt_needs_teelink(struct intel_gt *gt) +{ + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && intel_huc_is_loaded_by_gsc(>->uc.huc) && + intel_uc_uses_huc(>->uc)); +} + +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp) +{ + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_DRM_I915_PXP) && + INTEL_INFO((pxp_to_gt(pxp))->i915)->has_pxp && VDBOX_MASK(pxp_to_gt(pxp))); +} + bool intel_pxp_is_enabled(const struct intel_pxp *pxp) { return pxp->ce; @@ -142,17 +156,13 @@ void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = pxp_to_gt(pxp); - /* we rely on the mei PXP module */ - if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP)) - return; - /* * If HuC is loaded by GSC but PXP is disabled, we can skip the init of * the full PXP session/object management and just init the tee channel. */ - if (HAS_PXP(gt->i915)) + if (intel_pxp_supported_on_gt(pxp)) pxp_init_full(pxp); - else if (intel_huc_is_loaded_by_gsc(>->uc.huc) && intel_uc_uses_huc(>->uc)) + else if (_gt_needs_teelink(gt)) intel_pxp_tee_component_init(pxp); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 2da309088c6d..efa83f9d5e24 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -13,6 +13,9 @@ struct intel_pxp; struct drm_i915_gem_object; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); + +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp); + bool intel_pxp_is_enabled(const struct intel_pxp *pxp); bool intel_pxp_is_active(const struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4359e8be4101..f0ad6f34624a 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -70,7 +70,7 @@ void intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *gt_root) if (!gt_root) return; - if (!HAS_PXP((pxp_to_gt(pxp)->i915))) + if (!intel_pxp_supported_on_gt(pxp)) return; root = debugfs_create_dir("pxp", gt_root); From patchwork Thu Nov 17 00:30:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13045962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3ACAC433FE for ; Thu, 17 Nov 2022 00:28:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5195310E509; Thu, 17 Nov 2022 00:28:14 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2889F10E4FB for ; Thu, 17 Nov 2022 00:28:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668644890; x=1700180890; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hv2kPxo0rkMBJygTSwugqL373JPoegf35ZwqsuO3V7o=; b=JwuKfY65eqL7sf28vPRtHYnsDBeaQ1sbHDkFBOU3HBn9OLNgDTymgD9F EgCu22y7agzvl9YJEehIUCL379ZUTl6/7ZhrSDhEkvBbN7fKyyEUNc4U/ d5QSVH3aCV0CClWerOg2JX0fYCj4ebKAf7qitA0/U9jiZEPdrjBhDazBJ yU4iQ0wx6ANn3eVDrU4qajBps4ja7DnRHVh53aIQ4VDaEdMTD8/MNk+pn nwwgNJWlEwA5+ZBoxG5w+X6VOv2jA4eoeKuLLS3sHFVfCKAVFfxm2VP1P KYOPLbVtJPVvXcJ6v9X1tIQmKlb/RiYrex48QgbQS+OlsAa3FXykXmtB/ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="312722093" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="312722093" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 16:27:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="781985082" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="781985082" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2022 16:27:48 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Nov 2022 16:30:14 -0800 Message-Id: <20221117003018.1433115-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> References: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 2/6] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_enabled a global check and implicitly find the PXP-owning-GT. PXP feature support is a device-config flag. In preparation for MTL PXP control-context shall reside on of the two GT's. That said, update intel_pxp_is_enabled to take in i915 as its input and internally find the right gt to check if PXP is enabled so its transparent to callers of this functions. However we also need to expose the per-gt variation of this internal pxp files to use (like what intel_pxp_enabled was prior) so also expose a new intel_gtpxp_is_enabled function for replacement. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 28 ++++++++++++++++++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 ++- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 8 +++--- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 +-- 9 files changed, 40 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 7f2831efc798..c123f4847b19 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -257,7 +257,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, if (!protected) { pc->uses_protected_content = false; - } else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) { + } else if (!intel_pxp_is_enabled(i915)) { ret = -ENODEV; } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) || !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 33673fe7ee0a..e44803f9bec4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data if (ext.flags) return -EINVAL; - if (!intel_pxp_is_enabled(&to_gt(ext_data->i915)->pxp)) + if (!intel_pxp_is_enabled(ext_data->i915)) return -ENODEV; ext_data->flags |= I915_BO_PROTECTED; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index d993e752bd36..88105101af79 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -9,6 +9,7 @@ #include "intel_pxp_tee.h" #include "gem/i915_gem_context.h" #include "gt/intel_context.h" +#include "gt/intel_gt.h" #include "i915_drv.h" /** @@ -58,11 +59,34 @@ bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp) INTEL_INFO((pxp_to_gt(pxp))->i915)->has_pxp && VDBOX_MASK(pxp_to_gt(pxp))); } -bool intel_pxp_is_enabled(const struct intel_pxp *pxp) +bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp) { return pxp->ce; } +static struct intel_gt *i915_to_pxp_gt(struct drm_i915_private *i915) +{ + struct intel_gt *gt = NULL; + int i = 0; + + for_each_gt(gt, i915, i) { + /* There can be only one GT that supports PXP */ + if (intel_pxp_supported_on_gt(>->pxp)) + return gt; + } + return NULL; +} + +bool intel_pxp_is_enabled(struct drm_i915_private *i915) +{ + struct intel_gt *gt = i915_to_pxp_gt(i915); + + if (!gt) + return false; + + return intel_pxp_is_enabled_on_gt(>->pxp); +} + bool intel_pxp_is_active(const struct intel_pxp *pxp) { return pxp->arb_is_valid; @@ -216,7 +240,7 @@ int intel_pxp_start(struct intel_pxp *pxp) { int ret = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return -ENODEV; if (wait_for(pxp_component_bound(pxp), 250)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index efa83f9d5e24..3f71b1653f74 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -11,12 +11,14 @@ struct intel_pxp; struct drm_i915_gem_object; +struct drm_i915_private; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp); -bool intel_pxp_is_enabled(const struct intel_pxp *pxp); +bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp); +bool intel_pxp_is_enabled(struct drm_i915_private *i915); bool intel_pxp_is_active(const struct intel_pxp *pxp); void intel_pxp_init(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c index f41e45763d0d..f322a49ebadc 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -99,7 +99,7 @@ int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id) u32 *cs; int err = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return 0; rq = i915_request_create(ce); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index f0ad6f34624a..4d257055434b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -18,7 +18,7 @@ static int pxp_info_show(struct seq_file *m, void *data) { struct intel_pxp *pxp = m->private; struct drm_printer p = drm_seq_file_printer(m); - bool enabled = intel_pxp_is_enabled(pxp); + bool enabled = intel_pxp_is_enabled_on_gt(pxp); if (!enabled) { drm_printf(&p, "pxp disabled\n"); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index c28be430718a..d3c697bf9aab 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -22,7 +22,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { struct intel_gt *gt = pxp_to_gt(pxp); - if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) + if (GEM_WARN_ON(!intel_pxp_is_enabled_on_gt(pxp))) return; lockdep_assert_held(gt->irq_lock); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 6a7d4e2ee138..19ac8828cbde 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -11,7 +11,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; pxp->arb_is_valid = false; @@ -23,7 +23,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) { intel_wakeref_t wakeref; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; with_intel_runtime_pm(&pxp_to_gt(pxp)->i915->runtime_pm, wakeref) { @@ -34,7 +34,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) void intel_pxp_resume(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; /* @@ -50,7 +50,7 @@ void intel_pxp_resume(struct intel_pxp *pxp) void intel_pxp_runtime_suspend(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; pxp->arb_is_valid = false; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index b0c9170b1395..a5c9c692c20d 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -152,7 +152,7 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, return 0; /* the component is required to fully start the PXP HW */ - if (intel_pxp_is_enabled(pxp)) + if (intel_pxp_is_enabled_on_gt(pxp)) intel_pxp_init_hw(pxp); intel_runtime_pm_put(&i915->runtime_pm, wakeref); @@ -167,7 +167,7 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); intel_wakeref_t wakeref; - if (intel_pxp_is_enabled(pxp)) + if (intel_pxp_is_enabled_on_gt(pxp)) with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) intel_pxp_fini_hw(pxp); From patchwork Thu Nov 17 00:30:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13045963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C716AC433FE for ; Thu, 17 Nov 2022 00:28:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7CC1D10E50C; Thu, 17 Nov 2022 00:28:16 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5BFEA10E4F9 for ; Thu, 17 Nov 2022 00:28:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668644890; x=1700180890; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=IGxxnbzXiVkz2wbvhQhw69WtTK/OvzTQBpcbQxVP9qc=; b=HHnz0YKd2hHFdtFN3zaPpGL93OBkb1ZHgfmpz0o8e3Jw4PxE+nWG9Sjk fuIw/IBYLZhuLmRV2Nz3rdQc0LXyAPoEz3asu+8S6T8TqOWYvzRsp/a4A O7jDbTPgSMlvNWmWzfrSgsaPK7TIexcuJuyBEDaelGpwoO7pRru6lcQrV FobTeOecQ/PTUoe9D9+gd+6pub/HM9LG9n+0PWqrTaVdccT+KsPsE90Zu TuchLp67UBJgFAC9ZqlFXCR1RfsUI9n570dCSTAZ5PaNHvuBeRs+NUU8e /YryzHy1WNhsdJkY1bjmxOh8oSrp3mo4eqZfyUKiNgDg2E6wdkLB400fR g==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="312722094" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="312722094" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 16:27:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="781985084" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="781985084" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2022 16:27:48 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Nov 2022 16:30:15 -0800 Message-Id: <20221117003018.1433115-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> References: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 3/6] drm/i915/pxp: Make intel_pxp_is_active implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_active a global check and implicitly find the PXP-owning-GT. As per prior two patches, callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_is_active implicitly find the right gt so it's transparent for global view callers (like display or gem-exec). However we also need to expose the per-gt variation of this for internal pxp files to use (like what intel_pxp_is_active was prior) so also expose a new intel_gtpxp_is_active function for replacement. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 4 ++-- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +- 5 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index c123f4847b19..165be45a3c13 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -271,7 +271,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, */ pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); - if (!intel_pxp_is_active(&to_gt(i915)->pxp)) + if (!intel_pxp_is_active(i915)) ret = intel_pxp_start(&to_gt(i915)->pxp); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 88105101af79..76a924587543 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -87,11 +87,21 @@ bool intel_pxp_is_enabled(struct drm_i915_private *i915) return intel_pxp_is_enabled_on_gt(>->pxp); } -bool intel_pxp_is_active(const struct intel_pxp *pxp) +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp) { return pxp->arb_is_valid; } +bool intel_pxp_is_active(struct drm_i915_private *i915) +{ + struct intel_gt *gt = i915_to_pxp_gt(i915); + + if (!gt) + return false; + + return intel_pxp_is_active_on_gt(>->pxp); +} + /* KCR register definitions */ #define KCR_INIT _MMIO(0x320f0) /* Setting KCR Init bit is required after system boot */ @@ -287,7 +297,7 @@ int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object *obj, bool assign) { - if (!intel_pxp_is_active(pxp)) + if (!intel_pxp_is_active_on_gt(pxp)) return -ENODEV; if (!i915_gem_object_is_protected(obj)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 3f71b1653f74..fe981eebf0ec 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -19,7 +19,8 @@ bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp); bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp); bool intel_pxp_is_enabled(struct drm_i915_private *i915); -bool intel_pxp_is_active(const struct intel_pxp *pxp); +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp); +bool intel_pxp_is_active(struct drm_i915_private *i915); void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4d257055434b..52a808fd4704 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -25,7 +25,7 @@ static int pxp_info_show(struct seq_file *m, void *data) return 0; } - drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp))); + drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active_on_gt(pxp))); drm_printf(&p, "instance counter: %u\n", pxp->key_instance); return 0; @@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val) struct intel_pxp *pxp = data; struct intel_gt *gt = pxp_to_gt(pxp); - if (!intel_pxp_is_active(pxp)) + if (!intel_pxp_is_active_on_gt(pxp)) return -ENODEV; /* simulate a termination interrupt */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index d3c697bf9aab..c25c1979cccc 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -86,7 +86,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp) * called in a path were the driver consider the session as valid and * doesn't call a termination on restart. */ - GEM_WARN_ON(intel_pxp_is_active(pxp)); + GEM_WARN_ON(intel_pxp_is_active_on_gt(pxp)); spin_lock_irq(gt->irq_lock); From patchwork Thu Nov 17 00:30:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13045966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E333BC4332F for ; Thu, 17 Nov 2022 00:28:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BEFF510E4F9; Thu, 17 Nov 2022 00:28:57 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 965A110E50B for ; Thu, 17 Nov 2022 00:28:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668644890; x=1700180890; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=sOFvRKH/ULgfTSsQYThhX9caxvOm2uDcWLMER5PQ74U=; b=gx2ZOzgfnuF/p4QBSzcJp/5l635XXscS6mC5/n1Y0xzsNFekal2YnZdT GKYVwAI1unt9HQy0mc4+VoKDlsXGOQXUWYZN8dAkcSO24nTFm2XFFhtty r4PJqLubDEWK5gnS+o/Rzm2zw6OEoxIbCrIR3A6g33WsiJXajGJu0QbOr 3XuEtr8MKnQZbZpWzwVHYTRW+hF6tBi4GrI0qVs5iq0d5l2vzHGlmoBsp abqpt18TNu+yarqrVoSLLPiP2OGPy620lkhnMJ/hp6moyrQUS7mqBicHz ydNhotg12MmVr8VLw82rubj6Z1EsLqoF7esYUxGc0Najzs1eTE2D8j8WB w==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="312722095" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="312722095" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 16:27:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="781985085" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="781985085" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2022 16:27:48 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Nov 2022 16:30:16 -0800 Message-Id: <20221117003018.1433115-5-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> References: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 4/6] drm/i915/pxp: Make PXP tee component bind/unbind aware of PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out getting the correct per-GT PXP control-context from the PXP-owning-GT when establishing or ending connection. Thus, replace _i915_to_pxp_gt with intel_pxp_get_owning_gt (also takes in i915). Signed-off-by: Alan Previn Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 6 +++--- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 ++++++++++++-- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 76a924587543..6a78b6ef0235 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -64,7 +64,7 @@ bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp) return pxp->ce; } -static struct intel_gt *i915_to_pxp_gt(struct drm_i915_private *i915) +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915) { struct intel_gt *gt = NULL; int i = 0; @@ -79,7 +79,7 @@ static struct intel_gt *i915_to_pxp_gt(struct drm_i915_private *i915) bool intel_pxp_is_enabled(struct drm_i915_private *i915) { - struct intel_gt *gt = i915_to_pxp_gt(i915); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); if (!gt) return false; @@ -94,7 +94,7 @@ bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp) bool intel_pxp_is_active(struct drm_i915_private *i915) { - struct intel_gt *gt = i915_to_pxp_gt(i915); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); if (!gt) return false; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index fe981eebf0ec..c798c3bde957 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -13,6 +13,8 @@ struct intel_pxp; struct drm_i915_gem_object; struct drm_i915_private; +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915); + struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index a5c9c692c20d..b9198e961cb6 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -20,8 +20,12 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); - return &to_gt(i915)->pxp; + if (!gt) + return NULL; + + return >->pxp; } static int intel_pxp_tee_io_message(struct intel_pxp *pxp, @@ -128,10 +132,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); - struct intel_uc *uc = &pxp_to_gt(pxp)->uc; + struct intel_uc *uc; intel_wakeref_t wakeref; int ret = 0; + if (!pxp) { + drm_warn(&i915->drm, "tee comp binding without a PXP-owner GT\n"); + return -ENODEV; + } + uc = &pxp_to_gt(pxp)->uc; + mutex_lock(&pxp->tee_mutex); pxp->pxp_component = data; pxp->pxp_component->tee_dev = tee_kdev; From patchwork Thu Nov 17 00:30:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13045965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 408CFC433FE for ; Thu, 17 Nov 2022 00:28:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 430D210E50D; Thu, 17 Nov 2022 00:28:48 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8046F10E509 for ; Thu, 17 Nov 2022 00:28:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668644890; x=1700180890; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=66746lkdTlKIVsnhTdEaXzkBVgYPhaxVi01xEEKBH44=; b=UPGoXf7CGik8V+7tvMeQZGSp0eqXgCtt/3KXyiffPLQGJQXvGjO/cOBE KAzI+cwTPEa9i1LNRTzJLRbrWGP7DDKKGNlVKeN4M0U2oWBnQdn8J7+H4 VUVcDX90Vza6QqAzzW1GAdvBhiq+reEVVnloT2Iva9z7i98ZtlBoxuNs8 fCsE00k3SW6+cVgUDNFmiOzgee8kcMgsoOrRWNCBJnUTw2RGEzZp5YYA6 ExRU+jN/uLsoHQnLD0+NS2T96W7ac6Mua570sa8HQyRzN3L9OUPxYVg7c Z2MVcPWQqoJ4dqLocitBl8XO++v0PfBCXtkJlauC7mAxtvRoMuLV0TiV2 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="312722096" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="312722096" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 16:27:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="781985086" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="781985086" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2022 16:27:48 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Nov 2022 16:30:17 -0800 Message-Id: <20221117003018.1433115-6-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> References: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 5/6] drm/i915/pxp: Make intel_pxp_start implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_start implicitly find the PXP-owning-GT. Callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_start implicitly find the right gt to start PXP arb session so it's transparent to the callers. Signed-off-by: Alan Previn Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 ++++++++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 165be45a3c13..15c3d435093a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -272,7 +272,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); if (!intel_pxp_is_active(i915)) - ret = intel_pxp_start(&to_gt(i915)->pxp); + ret = intel_pxp_start(i915); } return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 6a78b6ef0235..43f3790e1520 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -246,10 +246,17 @@ static bool pxp_component_bound(struct intel_pxp *pxp) * the arb session is restarted from the irq work when we receive the * termination completion interrupt */ -int intel_pxp_start(struct intel_pxp *pxp) +int intel_pxp_start(struct drm_i915_private *i915) { + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; int ret = 0; + if (!gt) + return -ENODEV; + + pxp = >->pxp; + if (!intel_pxp_is_enabled_on_gt(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index c798c3bde957..7b2b93a2ba94 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -32,7 +32,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); -int intel_pxp_start(struct intel_pxp *pxp); +int intel_pxp_start(struct drm_i915_private *i915); int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object *obj, From patchwork Thu Nov 17 00:30:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13045964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 472D1C4332F for ; Thu, 17 Nov 2022 00:28:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3511210E511; Thu, 17 Nov 2022 00:28:41 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 16B5F10E4FB for ; Thu, 17 Nov 2022 00:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668644891; x=1700180891; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=sAcmVXfnnGaRNrvmGb5c3zsx0Z8I26wIqzEklGI/2mo=; b=OOgTXsEDLbwSkaph3BiyLT//HzS9MZLp+pgJukMKfyYpI3AWwrL8+Udf aQcS37BK/9kuEkU2Ciiqd5fKYDdGpR8lO0AVpHxzrJuccxIvCH1zkkqm2 m4BRT+pFmGCMVXQyd0pKhnoPG8RMzs303ubLSTwL29GXf0rqZfzRIFQA5 m0S91ZAPBu33Iz1b8UdL2CaMurPPxdmG0wcyFpHf4KvWmIlt+DbFABFdj wbXj1EJ8SLPfUcH3aOayeHze+1m5TQuwud13LoopZC4yhraHuq4gea2Dx 6bwi5IEJN+l1JKgkdQsmhYMnpVxtt3tYd0thp+zntlu3I7buUCYCHuIjO A==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="312722097" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="312722097" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 16:27:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="781985087" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="781985087" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2022 16:27:48 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Nov 2022 16:30:18 -0800 Message-Id: <20221117003018.1433115-7-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> References: <20221117003018.1433115-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 6/6] drm/i915/pxp: Make intel_pxp_key_check implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_key_check implicitly find the PXP-owning-GT. Callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_key_check implicitly find the right gt to verify pxp session key establishment count so it's transparent to the callers. Signed-off-by: Alan Previn Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++++++++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 76490cc59d8f..3436bf433c10 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1848,7 +1848,7 @@ static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - return intel_pxp_key_check(&to_gt(i915)->pxp, obj, false) == 0; + return intel_pxp_key_check(i915, obj, false) == 0; } static bool pxp_is_borked(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 29e9e8d5b6fe..9943d5827300 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -869,7 +869,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) */ if (i915_gem_context_uses_protected_content(eb->gem_context) && i915_gem_object_is_protected(obj)) { - err = intel_pxp_key_check(&vm->gt->pxp, obj, true); + err = intel_pxp_key_check(vm->gt->i915, obj, true); if (err) { i915_gem_object_put(obj); return ERR_PTR(err); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 43f3790e1520..58219beecfa4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -300,10 +300,18 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp) intel_pxp_irq_disable(pxp); } -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign) { + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; + + if (!gt) + return -ENODEV; + + pxp = >->pxp; + if (!intel_pxp_is_active_on_gt(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 7b2b93a2ba94..6fe1595a84d6 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -34,7 +34,7 @@ void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); int intel_pxp_start(struct drm_i915_private *i915); -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign);