From patchwork Fri Nov 18 02:56:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13047682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7637BC4332F for ; Fri, 18 Nov 2022 03:20:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=feoQGeVwFVYy/EcBu5zL9pOC5pmPD1LbJrRn75KtEw8=; b=kONpmEBDa2eyhg 7O8wGeMBtlifO35ffyP5klW8z5wNQyNFY1s3ATBZ0i0Q+GGkA1kG50LLMkcQc75/iVybt2Uge2VAw 9MdseJgYIx+F1tOu1Qj/XytXL6s61ujUQEU4ie1ljCAGYk7S4M+sQH0okL46BaJkkgzYS6wAEGiGh 0PNc59yBlrWVhm9eTbMZbuAD3X5/RmnC8Ntnfm9oztWUe0J+Zks8O1e7/wWTawUa0mQZVh+LrtpcU ti79FkTHcqWmwIav4iXmnz60jhcdyQzQZtsGhLXVJrTrTUCWcq5RFWOGLFHgLv3sVwue+vy27ZtT+ 07nzZD8EFdhkTJ0mzRUg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovrta-001cbf-PH; Fri, 18 Nov 2022 03:18:26 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovrtW-001cVV-7o for linux-arm-kernel@lists.infradead.org; Fri, 18 Nov 2022 03:18:24 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A24B71A1251; Fri, 18 Nov 2022 04:18:16 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 699611A1244; Fri, 18 Nov 2022 04:18:16 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 941C418002F4; Fri, 18 Nov 2022 11:18:14 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com, marex@denx.de, tharvey@gateworks.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, shawnguo@kernel.org, alexander.stein@ew.tq-group.com, richard.leitner@linux.dev Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v2] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations Date: Fri, 18 Nov 2022 10:56:39 +0800 Message-Id: <1668740199-31956-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221117_191822_457322_FFE08A70 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as i.MX8MP PCIe reference clock. The following properties of PHY dts node should be changed accordingly. - Set 'fsl,refclk-pad-mode' as ''. - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_AXI>'. Signed-off-by: Richard Zhu Tested-by: Marcel Ziswiler --- v1->v2: Refer to Lucas' comments, don't expose IMX8MP_CLK_HSIO_ROOT to dts node. https://patchwork.ozlabs.org/project/linux-pci/patch/1666590189-1364-1-git-send-email-hongxing.zhu@nxp.com/ Use <&clk IMX8MP_CLK_HSIO_AXI> as referrence clock source when internal clock mode is used by i.MX8MP PCIe module. Verified on i.MX8MP EVK board with removing R131/R132/R137/R138, and populating R135/R136. --- drivers/soc/imx/imx8mp-blk-ctrl.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index 0e3b6ba22f94..5ad20a8ea25e 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -21,6 +21,16 @@ #define USB_CLOCK_MODULE_EN BIT(1) #define PCIE_PHY_APB_RST BIT(4) #define PCIE_PHY_INIT_RST BIT(5) +#define GPR_REG2 0x8 +#define P_PLL_MASK GENMASK(5, 0) +#define M_PLL_MASK GENMASK(15, 6) +#define S_PLL_MASK GENMASK(18, 16) +#define P_PLL (0xc << 0) +#define M_PLL (0x320 << 6) +#define S_PLL (0x4 << 16) +#define GPR_REG3 0xc +#define PLL_CKE BIT(17) +#define PLL_RST BIT(31) struct imx8mp_blk_ctrl_domain; @@ -86,6 +96,18 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, case IMX8MP_HSIOBLK_PD_PCIE_PHY: regmap_set_bits(bc->regmap, GPR_REG0, PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST); + + /* Set the PLL configurations, P = 12, M = 800, S = 4. */ + regmap_update_bits(bc->regmap, GPR_REG2, + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK, + P_PLL | M_PLL | S_PLL); + udelay(1); + + regmap_update_bits(bc->regmap, GPR_REG3, PLL_RST, PLL_RST); + udelay(10); + + /* Set 1b'1 to pll_cke of GPR_REG3 */ + regmap_update_bits(bc->regmap, GPR_REG3, PLL_CKE, PLL_CKE); break; default: break;