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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/3] xen/arm: Drop early_uart_init macro from debug-meson.inc Date: Fri, 18 Nov 2022 12:46:16 +0100 Message-ID: <20221118114618.20754-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118114618.20754-1-michal.orzel@amd.com> References: <20221118114618.20754-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT005:EE_|PH8PR12MB6723:EE_ X-MS-Office365-Filtering-Correlation-Id: 88f6f17a-6641-4e71-4d5c-08dac95a91c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HSsOzed7LukJXNSRm1HmxGogaM08uhyORH4nUeb7I+okBxTtuGbnJfNJhJOOJGvUG3tGFR1xxYRkOBpV2QPBZOwu461Yo6e2mS+lhNGuoawskSH4/j0lekoSgFJ9/k4pEaYEV77ZHp6kr4CjqlJ2hI+lRWBclyZXMkg1ddcbjFqeBsZ5cHdKPIlnWOyCZ/IA9WTG9+jlyy5X74i6ucsKW8oZ+ZpVzJLLK3symBflX8n6au4KhfRKllrlJ2wI1psDeNHI+syq6ScHNggRfkw7F1yczoggy++tOX/XaXp45hUtQ9En2G/rr6JBdnk6L+mmO2cUaILY4MNiZrosCXYahccSOrI0shw3eoGS9NnTQNiaiRfATo58i9wqvXeS5DXCqcXcTEa0A5mGpOw2d0U+GI7tWyI9uRITrckF6px8CnVJTFYRQHCe+WaK3l1lLFa55sMH41MIBabQuc/kVv8wMcTlS4R4HeUiLD0aSo2+grA5Gyrct7SXUjq0hTv0vJApx1jE80ptMANxVk1d6y9j0/KjhKhZKglFGunHwhmhfLX/3sxxijQ3zY5eNrRxgWoDe/GcQolSbJHg7n8J3aKM+lkOYZROjVqN5HfoXGEbWGtjd68jkPZj1jWJBTw9lvlvf0lvqQj109mA5G/THWjsRMkEvHgUv2gvAUGwFhHmP+DqS6Z6R+DBSNUlCp1n0iJdK83P6tsJ3pXCRROretVOUwDEal0QyIDqDLtUQfxr/bE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(396003)(346002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36860700001)(40480700001)(86362001)(36756003)(40460700003)(81166007)(356005)(82740400003)(82310400005)(26005)(6666004)(6916009)(54906003)(44832011)(4744005)(8936002)(336012)(47076005)(186003)(1076003)(5660300002)(83380400001)(426003)(2906002)(8676002)(4326008)(70586007)(316002)(478600001)(2616005)(70206006)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 11:46:45.5875 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88f6f17a-6641-4e71-4d5c-08dac95a91c7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6723 early_uart_init macro is only used if CONFIG_EARLY_UART_INIT is set. This config option depends on EARLY_UART_PL011, so there is no point in defining it for MESON, especially if it is empty. Remove it and adapt the existing comment. Signed-off-by: Michal Orzel Acked-by: Julien Grall --- xen/arch/arm/arm64/debug-meson.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/arm64/debug-meson.inc b/xen/arch/arm/arm64/debug-meson.inc index e1a8fa8ab9c4..e65e1ccde482 100644 --- a/xen/arch/arm/arm64/debug-meson.inc +++ b/xen/arch/arm/arm64/debug-meson.inc @@ -23,9 +23,10 @@ #define AML_UART_TX_FIFO_FULL 21 -.macro early_uart_init xb, c -/* Uart has already been initialized by Firmware, for instance by TF-A */ -.endm +/* + * No need for early_uart_init, as UART has already been initialized + * by Firmware, for instance by TF-A. + */ /* * MESON UART wait UART to be ready to transmit From patchwork Fri Nov 18 11:46:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Orzel X-Patchwork-Id: 13048139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BF6FC43217 for ; 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bh=+M+4H7JP9TPokpt207QPaKodTXJurywMQrtxzR4L+NM=; b=f0bqYLDx0NIAzf18YVjniYL+Lc+2ExZqGjR1xBtICbm8JRg3xq5zLkAcUJZx0iXckT+GqD9iyDv9hMM7E0sXQ/5TKLiJUSxnClS2SxiqiYwvpfuhVvT5nOc4Llanl5NqiWXX9Z/lIPMqp8XWfdcHBLvtno9qN9bshq26ghCdJ5Q= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Luca Fancellu , Julien Grall Subject: [PATCH 2/3] xen/arm: debug-pl011.inc: Use macros instead of hardcoded values Date: Fri, 18 Nov 2022 12:46:17 +0100 Message-ID: <20221118114618.20754-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118114618.20754-1-michal.orzel@amd.com> References: <20221118114618.20754-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT108:EE_|PH8PR12MB6865:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f95dd7c-98b6-44ff-3b18-08dac95a8e96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 11:46:40.2171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f95dd7c-98b6-44ff-3b18-08dac95a8e96 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6865 Make use of the macros defined in asm/pl011-uart.h instead of hardcoding the values. Also, take the opportunity to fix the file extension in a top-level comment. No functional change intended. Signed-off-by: Michal Orzel Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- This patch has already been reviewed/acked when pushed as a standalone one. Added to the series for ease of merging. --- xen/arch/arm/arm64/debug-pl011.inc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-pl011.inc index 1928a2e3ffbb..d82f2f1de197 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -1,5 +1,5 @@ /* - * xen/arch/arm/arm64/debug-pl011.S + * xen/arch/arm/arm64/debug-pl011.inc * * PL011 specific debug code * @@ -16,6 +16,8 @@ * GNU General Public License for more details. */ + #include + /* * PL011 UART initialization * xb: register which containts the UART base address @@ -23,13 +25,13 @@ */ .macro early_uart_init xb, c mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE % 16) - strh w\c, [\xb, #0x28] /* -> UARTFBRD (Baud divisor fraction) */ + strh w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */ mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) - strh w\c, [\xb, #0x24] /* -> UARTIBRD (Baud divisor integer) */ + strh w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer) */ mov x\c, #0x60 /* 8n1 */ - str w\c, [\xb, #0x2C] /* -> UARTLCR_H (Line control) */ - ldr x\c, =0x00000301 /* RXE | TXE | UARTEN */ - str w\c, [\xb, #0x30] /* -> UARTCR (Control Register) */ + str w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ + ldr x\c, =(RXE | TXE | UARTEN) + str w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ .endm /* @@ -39,8 +41,8 @@ */ .macro early_uart_ready xb, c 1: - ldrh w\c, [\xb, #0x18] /* <- UARTFR (Flag register) */ - tst w\c, #0x8 /* Check BUSY bit */ + ldrh w\c, [\xb, #FR] /* <- UARTFR (Flag register) */ + tst w\c, #BUSY /* Check BUSY bit */ b.ne 1b /* Wait for the UART to be ready */ .endm @@ -50,7 +52,7 @@ * wt: register which contains the character to transmit */ .macro early_uart_transmit xb, wt - strb \wt, [\xb] /* -> UARTDR (Data Register) */ + strb \wt, [\xb, #DR] /* -> UARTDR (Data Register) */ .endm /* From patchwork Fri Nov 18 11:46:18 2022 Content-Type: text/plain; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/3] xen/arm: Define WLEN_8 macro and use it in debug-pl011 Date: Fri, 18 Nov 2022 12:46:18 +0100 Message-ID: <20221118114618.20754-4-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118114618.20754-1-michal.orzel@amd.com> References: <20221118114618.20754-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT095:EE_|BL1PR12MB5126:EE_ X-MS-Office365-Filtering-Correlation-Id: 85675678-a091-4d4a-4e0d-08dac95aa2a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pNksFMQiXPYjvVMFm33YJBM7/WKHf8VoBaEal+lXK6vZ1h9PHbeSs+xTVZ+U1+CfnwYBpkccvRw3nLx9yd9I/ieHA9NHtIcsF8tBuIOPjZpTt0Cz5qN/H84JnTWDt3OSR5GxShWZ/VLEsunKeSUNLtXL+ho/gdT0DtXDIs7sY2bE0FyQby2AxV27lgDjNyxCORd1pL06a741OBgONz/JZOhLH6jTe47S7BL85gnV0+6KPCs+u/vQHNjwVhSDThD2c7KKZ2QrIVhAMltwTjXXTBNIY9IMQOY8sVOkwIojGOtO6VdEv1zKS//uxYHwwDeRQX0I+UzGDovrpxozZMMNUbWn95lYWC2N/xPGApDvXTmNNpnC9PSWwHGAHn9mutjOOhu2c4L0K12+fv1G23TXtB7aYKog41USGwIHC268GVCfZVD6NBUNpRsJ4gfncfI7271mcg5gbBHgQuFNUDxWdwtWNoP0fcoJZBjnmZADcyZXVPQQqoxAONIqgAEQpEyALW5zjc9Tgbgcf/E1q1sdSxrAd3l53OyFs8fgOV8F4/RdibCvzbpfd2QzTL8lD93yC7VPfHOlCSE0TmtS6wmZh+9r1OfrvXntzHRl3UTDSjzyqhNkXPVrea92In0aurIy/p0pH+JcRlL9OoyEOSIiwX48zy0JVgoT1/SoDAkmn2p2cwdHOE2XBb/q8CRglyS6REK+MHY8R/dIA90gEQwC6rgQsQQxZ+P16laihcD+06E= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(41300700001)(36756003)(2616005)(36860700001)(1076003)(86362001)(2906002)(5660300002)(44832011)(336012)(426003)(83380400001)(186003)(8936002)(82740400003)(40460700003)(82310400005)(40480700001)(356005)(81166007)(47076005)(26005)(316002)(54906003)(6916009)(478600001)(6666004)(70586007)(70206006)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 11:47:13.8769 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85675678-a091-4d4a-4e0d-08dac95aa2a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT095.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5126 At the moment, early printk code for pl011 uses a hardcoded value for 8n1 LCR configuration. Define and use macro WLEN_8 for that purpose (no parity and 1 stop bit are defined as 0). Signed-off-by: Michal Orzel Acked-by: Julien Grall --- xen/arch/arm/arm32/debug-pl011.inc | 2 +- xen/arch/arm/arm64/debug-pl011.inc | 2 +- xen/arch/arm/include/asm/pl011-uart.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm32/debug-pl011.inc b/xen/arch/arm/arm32/debug-pl011.inc index 214f68dc95bd..c527f1d4424d 100644 --- a/xen/arch/arm/arm32/debug-pl011.inc +++ b/xen/arch/arm/arm32/debug-pl011.inc @@ -29,7 +29,7 @@ str \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */ mov \rc, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) str \rc, [\rb, #IBRD] /* -> UARTIBRD (Baud divisor integer) */ - mov \rc, #0x60 /* 8n1 */ + mov \rc, #WLEN_8 /* 8n1 */ str \rc, [\rb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr \rc, =(RXE | TXE | UARTEN) /* RXE | TXE | UARTEN */ str \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-pl011.inc index d82f2f1de197..6d60e78c8ba3 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -28,7 +28,7 @@ strh w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */ mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) strh w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer) */ - mov x\c, #0x60 /* 8n1 */ + mov x\c, #WLEN_8 /* 8n1 */ str w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr x\c, =(RXE | TXE | UARTEN) str w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ diff --git a/xen/arch/arm/include/asm/pl011-uart.h b/xen/arch/arm/include/asm/pl011-uart.h index 57e9ec73ac19..5bb563ec0814 100644 --- a/xen/arch/arm/include/asm/pl011-uart.h +++ b/xen/arch/arm/include/asm/pl011-uart.h @@ -55,6 +55,7 @@ /* LCR_H bits */ #define SPS (1<<7) /* Stick parity select */ +#define WLEN_8 (_AC(0x3, U) << 5) /* 8 bits word length */ #define FEN (1<<4) /* FIFO enable */ #define STP2 (1<<3) /* Two stop bits select */ #define EPS (1<<2) /* Even parity select */