From patchwork Fri Nov 18 15:53:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 13048441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5550FC433FE for ; Fri, 18 Nov 2022 15:54:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E74888F78; Fri, 18 Nov 2022 15:53:57 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 334D588F78; Fri, 18 Nov 2022 15:53:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668786834; x=1700322834; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=IgwbfkOzAdjg9aNcU8aS7ayZEFzAAc21vo4gWvNc0RE=; b=EgFInCEuERiuWYtuXiYQnYT7KMrQjOBigGePEXA3jbpLy7YI39qJd4j+ cKt9MX1DsEiuMrhGEGJsiDPMl9UXqzDxFa2DMCJxX73XL1v7sYmjo/j2O NhptQ5VwvIg9lfxmx3hrGax7h66J8Yx2RtOG1mZBu57cKgWwSCksgzSHT cXVXJlMTyOgU9Gx3U/+Bw2FXl2NzRwbwibPDsZVIDkSfuKG8cuTnKHcF9 Rx8voesDRdmoCNAwvgIRpyGYbNxIcQd094L6/LCzmmcoNcR7khRV1avjq U27mbS6TloeDiFJLT3R9TOa0EKGn3OY+YKTNXnlbOdIYczxobwmuLa/Ro Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10535"; a="296525536" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="296525536" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 07:53:44 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10535"; a="969315379" X-IronPort-AV: E=Sophos;i="5.96,174,1665471600"; d="scan'208";a="969315379" Received: from bbaker-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.1.50]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2022 07:53:42 -0800 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Fri, 18 Nov 2022 15:53:35 +0000 Message-Id: <20221118155335.635430-1-matthew.auld@intel.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t] tests/i915/gem_exec_balancer: exercise dmabuf import X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Andrzej Hajda , Nirmoy Das Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With parallel submission it should be easy to get a fence array as the output fence. Try importing this into dma-buf reservation object, to see if anything explodes. References: https://gitlab.freedesktop.org/drm/intel/-/issues/7532 Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Andrzej Hajda --- tests/i915/gem_exec_balancer.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c index 4300dbd1..fdae8de5 100644 --- a/tests/i915/gem_exec_balancer.c +++ b/tests/i915/gem_exec_balancer.c @@ -37,6 +37,7 @@ #include "igt_sysfs.h" #include "igt_types.h" #include "sw_sync.h" +#include IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing"); @@ -2856,6 +2857,24 @@ static void logical_sort_siblings(int i915, #define PARALLEL_SUBMIT_FENCE (0x1 << 3) #define PARALLEL_CONTEXTS (0x1 << 4) #define PARALLEL_VIRTUAL (0x1 << 5) +#define PARALLEL_OUT_FENCE_DMABUF (0x1 << 6) + +struct igt_dma_buf_sync_file { + __u32 flags; + __s32 fd; +}; + +#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct igt_dma_buf_sync_file) +#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct igt_dma_buf_sync_file) + +static void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd) +{ + struct igt_dma_buf_sync_file arg; + + arg.flags = flags; + arg.fd = sync_fd; + do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg); +} static void parallel_thread(int i915, unsigned int flags, struct i915_engine_class_instance *siblings, @@ -2871,6 +2890,8 @@ static void parallel_thread(int i915, unsigned int flags, uint32_t target_bo_idx = 0; uint32_t first_bb_idx = 1; intel_ctx_cfg_t cfg; + uint32_t dmabuf_handle; + int dmabuf; igt_assert(bb_per_execbuf < 32); @@ -2924,11 +2945,20 @@ static void parallel_thread(int i915, unsigned int flags, execbuf.buffers_ptr = to_user_pointer(obj); execbuf.rsvd1 = ctx->id; + if (flags & PARALLEL_OUT_FENCE_DMABUF) { + dmabuf_handle = gem_create(i915, 4096); + dmabuf = prime_handle_to_fd(i915, dmabuf_handle); + } + for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) { execbuf.flags &= ~0x3full; gem_execbuf_wr(i915, &execbuf); if (flags & PARALLEL_OUT_FENCE) { + if (flags & PARALLEL_OUT_FENCE_DMABUF) + dmabuf_import_sync_file(dmabuf, DMA_BUF_SYNC_WRITE, + execbuf.rsvd2 >> 32); + igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32, 1000), 0); igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 1); @@ -2959,6 +2989,11 @@ static void parallel_thread(int i915, unsigned int flags, if (fence) close(fence); + if (flags & PARALLEL_OUT_FENCE_DMABUF) { + gem_close(i915, dmabuf_handle); + close(dmabuf); + } + check_bo(i915, obj[target_bo_idx].handle, bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true); @@ -3420,6 +3455,10 @@ igt_main igt_subtest("parallel-out-fence") parallel(i915, PARALLEL_OUT_FENCE); + igt_subtest("parallel-out-fence-import-dmabuf") + parallel(i915, PARALLEL_OUT_FENCE | + PARALLEL_OUT_FENCE_DMABUF); + igt_subtest("parallel-keep-in-fence") parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);