From patchwork Fri Nov 18 23:32:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9141FC433FE for ; Sat, 19 Nov 2022 00:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229862AbiKSAJy (ORCPT ); Fri, 18 Nov 2022 19:09:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237483AbiKSAJd (ORCPT ); Fri, 18 Nov 2022 19:09:33 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98A289E972 for ; Fri, 18 Nov 2022 15:32:49 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id c1so10619429lfi.7 for ; Fri, 18 Nov 2022 15:32:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+A6rilHFZI6MYdzHjtL9YOIpSlyXP0el9z1gbix2N18=; b=oOU7yE9qXDOAgFpSHdkzaJB8QWRzZPXm8BJ75Cj1dDj1tclwRuVIuTQNe7K8dbzbxh PkboBWf2XsZxcZ3RhCKvkHcVA4zQ0TKKVkCa0xN7/dfBNkkPZQDNOHbQsrsxU2ht9Xzv 2wd2vPrOd8rQ5J+NO9nDRKe9CHdlWMcA+4GR0hb82+txUIExVPkRAouY83dWWWMn8Nyf FHN3ZfgfqWi57zlV21xUybvShXZ7FTP7Ruj5HeIB4BUuNSmff9+pvmmhZOYSLa0xeSqK UPL/HguKX/tgMfzdG2Ce5aRuVp4bpgSq9mIrXKUiziY8KSpTDTJkklG0uuQGOR3ZejvM 85tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+A6rilHFZI6MYdzHjtL9YOIpSlyXP0el9z1gbix2N18=; b=GzsjtyhxguLbc+EbRLxmIb0TvB00n1YtW1cllsp+V+b9SnxQrMtrcRYlpXIsN0FZAn s8xUIF9DxK237dTmNI8gobnPI5689XJ12zODYS4fn27y3Ldxz/YpnhP5VG9BBE3wk4Nf cOircreyWxd/dWoDD22biSxjIfTeUYiDbjyN6To8JFc6s5+UG/eHpBV9Dt4H2NNKwnQu S9roNiTDqhoHOBptI/hkVLlrfe6jLBTqkaBEfN7gxijasevup3zaE94CEmmlhfpFWe2I Wi3pvYc69kILzi5hAM7YTCnZ1Q0l3q+ZTCzkl7e8OZ7rfN4xAGEe1ARreEgr0sWqE5V0 UAZA== X-Gm-Message-State: ANoB5plh2w+asf8ErjvUONgINMVq/AJLrC+tT6THEPaJlxzcziBqumHZ 18NgFzuKu98vAkiP2ozSFmKpKQ== X-Google-Smtp-Source: AA0mqf42nQntitlvu0C5N/oHufK7bSWByH1O58uOQ5GalVNLYodSXuk1OmCznTzWJ97hZTgyjS3LnQ== X-Received: by 2002:ac2:5f9b:0:b0:4a2:5163:f61b with SMTP id r27-20020ac25f9b000000b004a25163f61bmr3006817lfe.177.1668814367948; Fri, 18 Nov 2022 15:32:47 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:47 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 1/8] dt-bindings: PCI: qcom: Add sm8350 to bindings Date: Sat, 19 Nov 2022 01:32:35 +0200 Message-Id: <20221118233242.2904088-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add bindings for two PCIe hosts on SM8350 platform. The only difference between them is in the aggre0 clock, which warrants the oneOf clause for the clocks properties. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 2f851c804bb0..ea295bc30504 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -32,6 +32,7 @@ properties: - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-ipq6018 @@ -193,6 +194,7 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 then: @@ -548,6 +550,35 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8350 + then: + properties: + clocks: + minItems: 8 + maxItems: 9 + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: @@ -690,6 +721,7 @@ allOf: - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 then: From patchwork Fri Nov 18 23:32:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EAB0C43217 for ; Sat, 19 Nov 2022 00:09:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237538AbiKSAJx (ORCPT ); Fri, 18 Nov 2022 19:09:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237497AbiKSAJe (ORCPT ); Fri, 18 Nov 2022 19:09:34 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945372DEF for ; Fri, 18 Nov 2022 15:32:51 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id j4so10687609lfk.0 for ; Fri, 18 Nov 2022 15:32:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DvnyFdgcWdO/y4g/GZdtkoa/ckJSM/CaYgX7M7Lgruw=; b=Mf6BPIQL3AC+s2O6KnSFxSJ33V9BDuaVz0eE1Iux1WjDj4JJZww5cF088ubioQ65a9 vGsrSNMWndMIT+0mXr0Sj6QosszPvs6czfpmW+8yZCOpzMeqhTVd/0jk6ZoXPv8X+iC+ xHFPM65rg9ruTjp6wNLmPKEptZJMUaxO5bW0qQX2A9Q4as9kq9ZDxIH5qJiw43o3HjSs 7dWktYJvThKbGR0LtxU0O5sAuUMSEwi6eEOL+RQVJl88w21SYJFQK6BCxxHdnRSJgN+C dPzBRSD5C/aZAfqAPzUq+L39wVWzUcjMn3GkttTDkg05SyvpCzp+CmHA9S5QOwXiOIXC oqJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DvnyFdgcWdO/y4g/GZdtkoa/ckJSM/CaYgX7M7Lgruw=; b=mazKoQ1rYt5EzPg5t8hDaXoxFW7NYBk46CYR+uKAp2NtjJ1e4nNs9tTFZqGX146fuR ZpO0P0L9spkk5vjvd6m2weo+FewKKTnXy+yxyneNzICYiZuHqVtZIfmaG75ZmbgNoyDx ttSYeKy3BAPTSCOIGK14t/ik7VZsWvclgU/LjJOTpIspJQnzOfIkkjGcGJQZiT0s69B+ DYzT13y5oGrje/45+eciTFYlzJNe4WtOybvhyE0j4mqNUm9hap/oouop/vqPXy3U63wS 9Qj3kADPqEdhvvxwnNEJUq0ElCcecxOSlNWc7VySeNKz2uMys4T+wxcg0RISfcnL2T8W PNrA== X-Gm-Message-State: ANoB5pkGI4pHwBoq4iNoFPsmPHkTLIU4DvVk22cL1oGMA+0kGun5zAju D9RFtbfirbL4/YxWRhAHAMSNRA== X-Google-Smtp-Source: AA0mqf6Znugn88JXILPSHLaNOhRx0k3bTOgt1DQZ1HyWx4qmV0JGOalJkHboO03+sRVZ8iuaxcS2Uw== X-Received: by 2002:ac2:4a62:0:b0:4aa:323f:e850 with SMTP id q2-20020ac24a62000000b004aa323fe850mr3123560lfp.492.1668814369953; Fri, 18 Nov 2022 15:32:49 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:49 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Rob Herring , Johan Hovold Subject: [PATCH v4 2/8] dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings Date: Sat, 19 Nov 2022 01:32:36 +0200 Message-Id: <20221118233242.2904088-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add bindings for the PCIe QMP PHYs found on SM8350. Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 80aa8d2507fb..8a85318d9c92 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -19,15 +19,18 @@ properties: - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy reg: minItems: 1 maxItems: 2 clocks: + minItems: 5 maxItems: 6 clock-names: + minItems: 5 items: - const: aux - const: cfg_ahb @@ -104,6 +107,25 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-qmp-gen3x1-pcie-phy + then: + properties: + clocks: + maxItems: 5 + clock-names: + maxItems: 5 + else: + properties: + clocks: + minItems: 6 + clock-names: + minItems: 6 + examples: - | #include From patchwork Fri Nov 18 23:32:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049278 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B69AC43217 for ; Sat, 19 Nov 2022 00:09:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237496AbiKSAJ4 (ORCPT ); Fri, 18 Nov 2022 19:09:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233639AbiKSAJg (ORCPT ); Fri, 18 Nov 2022 19:09:36 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAAF79E978 for ; Fri, 18 Nov 2022 15:32:53 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id d3so8657096ljl.1 for ; Fri, 18 Nov 2022 15:32:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gC1JYQfoCecKGmw1NdVlsiCw+iUTbqYNq5AbGPIxayA=; b=MfqoiRzTYofGQVZcXORPTFGdr+9epJSWOEQ13gaxNazT7QanZDmp4LLgDgidpnPcQY akKWPRoBlV3bahOt75lUbrUbbMCEwrqAhEXfDLsuoLrTmnCDzJyEg66xAlTYO8/uIf0L AlTJ54umFdfW+fLeJenG6JoMyOJOy0jKicQJTY2BA0Nwm6LlLblhOP1JpcV2KTrqcbw/ oX2mDAliNvMwyAfT1I1Qzin0/XqJl6+MC2w1lmaRqreCPasgcG9rkp4L7uq1BsQl2aiA zsmi3rzwoQy8jhMUI0CTN3vUTEeG3VZl0VLqv9MZFxRVZVlcmcKf4oErMbSFrS3Z0gvH +wUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gC1JYQfoCecKGmw1NdVlsiCw+iUTbqYNq5AbGPIxayA=; b=oWHTtGPG18Bk4rrlw9+usmI09GxMyho7jpb6uNCNhADQOp6By/Hu8HIYU9bpmmDeZJ 2RLIwCTUoH8p5qGUe4q9t5gWaeFZHhA7hgKrpct99rhCnC9VjT3irFAEeLAsQ6AL773z 2tHyKeFweg5Qi5z7R7Gu32IamXzjaQdaIH8kxhVjfbUguybt/Umr5VcJvFWkQ3cvACKB NJ6kzY46yhYd1/+912DisxRfjHMZDCei3SJNhot2WSNrLpV2bZMWyHM4hkHZQdYA02EY a5F0S2sAst2xaez9XajDwdzrXEoo9+Wdk+1YAw7g0wIai7LTyO3tRvNtJKCusIiupV+Z lOBA== X-Gm-Message-State: ANoB5pnXhcKUbICrgZpqqmol3fPPOwRCobu6/CU48cKjAap83TFDo3Wu nwIM0j3dxB0OYezYBiTw8T92Tw== X-Google-Smtp-Source: AA0mqf5xkJVLCJ8TjZTzGV/e0MJTNmp6C8bsXgT51CxSeQ+sAETlolX3RqJEn0Mfc1sx9IOsrJ8TCQ== X-Received: by 2002:a2e:bd8a:0:b0:277:b4e:6286 with SMTP id o10-20020a2ebd8a000000b002770b4e6286mr3225209ljq.279.1668814371902; Fri, 18 Nov 2022 15:32:51 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:51 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 3/8] PCI: qcom: Add support for SM8350 Date: Sat, 19 Nov 2022 01:32:37 +0200 Message-Id: <20221118233242.2904088-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for the PCIe host on Qualcomm SM8350 platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..b9350d93b4ba 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1826,6 +1826,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, { } From patchwork Fri Nov 18 23:32:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D993CC4332F for ; Sat, 19 Nov 2022 00:10:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237563AbiKSAKD (ORCPT ); Fri, 18 Nov 2022 19:10:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234785AbiKSAJi (ORCPT ); Fri, 18 Nov 2022 19:09:38 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C9AC13E2B for ; Fri, 18 Nov 2022 15:32:55 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id l8so8591229ljh.13 for ; Fri, 18 Nov 2022 15:32:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3+ONmInHewy6MvbwX/y3/rZ6bIRRiJ+CsA99YGYkRuE=; b=qF/2exeE7Lw639IigPGQ7KihatP4QEfOrgy5iBrpjWStQA9AYdQhoQdJI4M6e0gYYB UWTaxOhm5esuq/HMbigiKjJqaxU785JOVydqoalDfUeREx3//XzoBbqDtM9ilQbTJpiG Ke96HPBdoa87bUj392XNy1a7ivWyEhaVYXI9FdN0E/p9b+PgRHfonB/KkuQjFOPDJEnH 0ExrmPB6bHOrN5LhYL4JBLHZ8qKh1kT7HDroqx70k1lKrFFaKcmP0RH6DZrLk6ouLAZe Cmv/3i6YdgF/5gV9D1pR6GqGNU7p2/US+B9bIjubCnncWYZ9xGJuuSVAmq8OLef3eh6p lLaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3+ONmInHewy6MvbwX/y3/rZ6bIRRiJ+CsA99YGYkRuE=; b=LJsQ4S8E9Mrpr0J5bOUE5MwlU01Lu5Z0Kn+n7YRtsVJGI8XIimSjEix5IN4xb4dmDo Kz+P+9A1b99bumm7J5H5MLAV9FTiVAllRWTABDQbIwOvqzduDHvXRVRD/xkVvHV5n3Z/ +XClv4vkHdjSX1fKkoqE/MvGmY/MOC6uzhMP0UDgLMwwv/5ILVTVgd9409HhaSKfUzL0 okgYFcPWpCjDDYXbl8x/n9spBjtfhiePKAIDgMCOKoUpSzdbqPymN9JqrXDJm7T7JOef y77HFCUrNrP1Z4GtlN4MRyQs6zUBAFTNdbAkrqP3Fy4+1wPRyMbkLqPVnEzNa+qHY8EJ SJEA== X-Gm-Message-State: ANoB5pkBIF0EsnT5dIUAZpro7njG/MV5VJk4HoQUxvmgcwfKNCT+Gkcf 9523g/aInT/p7Hrrn2nq/fqnew== X-Google-Smtp-Source: AA0mqf4JU4fQuo6rRla9bsSJiiou3glKwPxyPjUeL+2KwD7t8dZ6s+M/yC/wBZ6WqfM8+j2Q8PNYJw== X-Received: by 2002:a05:651c:49d:b0:26d:295f:dfe7 with SMTP id s29-20020a05651c049d00b0026d295fdfe7mr3224806ljc.70.1668814373936; Fri, 18 Nov 2022 15:32:53 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:53 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 4/8] phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tables Date: Sat, 19 Nov 2022 01:32:38 +0200 Message-Id: <20221118233242.2904088-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Split these tables to be used by SM8350 config. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 47cccc4b35b2..d9f8dffbe1da 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1252,7 +1252,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), - QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), @@ -1263,6 +1262,10 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), }; +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), +}; + static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), @@ -1274,8 +1277,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), @@ -1283,14 +1284,19 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), +}; + +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), @@ -2030,6 +2036,14 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), }, + + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), + .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, + .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), + }, + .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, From patchwork Fri Nov 18 23:32:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B9B6C4167E for ; Sat, 19 Nov 2022 00:10:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233732AbiKSAKG (ORCPT ); Fri, 18 Nov 2022 19:10:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231837AbiKSAJj (ORCPT ); Fri, 18 Nov 2022 19:09:39 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 922DAA13C5 for ; Fri, 18 Nov 2022 15:32:57 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id g12so10649791lfh.3 for ; Fri, 18 Nov 2022 15:32:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1xDiE8Bwh4Ikzuy5U7/SCqTlGH/WFHTyDSOulj4Kkk0=; b=JJ6v0JJYYWa8jgUBtPN9xCyQne9val3S1YfDZFMue7laW/7FIVlJV6474jkssWN+ZR nx8RCCT7LEG3R3cmEPrevcC/tdsrynQPLaip+Yt0Ajkp7JokPHbfxtprERYyDbgQapW2 2j6318UQNiwIwJFQBXurAdNyuR5GX8r3lklPkl8nDlfj49f6u2geW9kyOsnUk+GIW5Zq ytLi75CuSKcnIj/pYh1XqWLd9YlTIz1IDcm7IConLOak5Z0HBadL41Nlex4HemMsOEEJ 9DDMM3FueHhAkT0q1WKmuN0sv6QFJQXjJQjdqXGpNtU8LH6IEHVctSL+eRQFfsNJpchP oBLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1xDiE8Bwh4Ikzuy5U7/SCqTlGH/WFHTyDSOulj4Kkk0=; b=vqN6VqW9yiAJNGWppayiLjvTYrnZIxsnmCdd1eqYR7amBEcGQNluA7uak3AsJPtbGJ GDVFEoWcS01MGPeTDcJ2VbhRYPmVRPs2GYbrDNKhFrx2BR1OT30wIyLvPesQWK4CZNUU FIzKXsFPgFKY2iSpx5VD90MvhGMw7hux3uEf8wq8zHxXqIZTOP4j4ZuSJksMXaMi985s vnGJIggeTqwc0C7PM3WKS7Y7TDO6OKafJLeKKXFKVvkPjIXt/nUJnhiZzrkC52HhwZ5O oxHqiRiuN4pus+lJLS4deHPHR1n7nZr2cPPxomRE5s0o7FFlYD+w+gaAtWekqFfFKVY7 vFtA== X-Gm-Message-State: ANoB5plN3YlEg5efLd+BqNPWx+HDTvnvuoYiJ/DrGDZ0P9YkNW17Z5pY x4FutC+ZxPz+zI8rQ24i0hCZZg== X-Google-Smtp-Source: AA0mqf5YxhcVuevI0EQUNPCzj+Zpxr7hOfRkWCHRK+XogwQMTUTpF8SHlglkdVLQfR/srYQmyXkAKA== X-Received: by 2002:ac2:5455:0:b0:4a2:2d58:1a12 with SMTP id d21-20020ac25455000000b004a22d581a12mr3005429lfn.94.1668814375960; Fri, 18 Nov 2022 15:32:55 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 5/8] phy: qcom-qmp-pcie: rename the sm8450 gen3 PHY config tables Date: Sat, 19 Nov 2022 01:32:39 +0200 Message-Id: <20221118233242.2904088-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Rename generic tables to remove x1 suffix. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d9f8dffbe1da..4a55b2439952 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1218,7 +1218,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { +static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), @@ -1274,7 +1274,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), }; -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { +static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), @@ -1302,7 +1302,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), }; -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { +static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), @@ -2025,14 +2025,14 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .lanes = 1, .tbls = { - .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, - .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), + .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), - .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, - .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), - .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, - .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), + .rx = sm8450_qmp_gen3_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), + .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), }, From patchwork Fri Nov 18 23:32:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87208C4332F for ; Sat, 19 Nov 2022 00:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237586AbiKSAKI (ORCPT ); Fri, 18 Nov 2022 19:10:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237169AbiKSAJj (ORCPT ); Fri, 18 Nov 2022 19:09:39 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E14FA13D8 for ; Fri, 18 Nov 2022 15:32:58 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id d3so8657299ljl.1 for ; Fri, 18 Nov 2022 15:32:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tB9jFbThbMD2bOC/2HEirSrt55WjI9bnLTvqrvRkEJc=; b=ae0dy1tmBm6x569nAzpp3FvkFGGry1lw/7wqBC8kkg5krOAD6XL3KjSgFYe0dQX8U3 jNWRBcA7zheekituJpQOapbcLJXg3xfuizdK2wPaytAYqcL+/nLOBxEUIBld9xK9XvOv gftHocZWMc/GbH0T1O+SJKz66isASfcp5n5Jk3PPwMy4D644MNRxocqavrSDCEwGaXDk wEmvOBp4gXLupqWmbZ+SRwTdDje1YPTiQHQVc6wWp7MLuZB7dYTS6MYbZrAX6/Ti2w0D oAFpfVc71/4ET9Qy4cVYN5ID3RhQdkKKvrfH7QvRGNorLeWfDv6nv6CjNghPloL5zjxS 8PNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tB9jFbThbMD2bOC/2HEirSrt55WjI9bnLTvqrvRkEJc=; b=dTVz4F4RbpBuTjRhGaSyJUHUPm48sIVJ3l7Z8hcf9mGEq58DuoWE5uWSaB1BvVKJhi oX9QFZ0imDJow2df+kqn4swFHb22TURSaA+8Jsr3dhTLPbnxQasHJNHIlCoWk2xWyuVl 3HldIFaVpLjz/EslQN0UhdfW1sJvFryJFIO4cLtK1Q9ckgOH5cyYJtIwTo9ZzZawuF0H HLfWNu3wsM/S6OC1QZR0VwfI+duxPMSddPs7IvNDMEdoMtU2rYbKETwI6Dpf68kntRPs /CpfK/on9WSqmFoUFwiGi4/8jXBwCJk5v8hXbKqKpWetj3E2vj2PsXlKmUTLCbfU3ksr Bj1A== X-Gm-Message-State: ANoB5pmWYfl8G0PWdX3mW4merzcTuP/hrMIiGo3J4utohzS5BMLeqnB/ O1tbNmoAjYRiG0RYyC1tLq13bA== X-Google-Smtp-Source: AA0mqf7y3Li8XCDf2PJAOt8YCaoj4FUPWRWO5xFbL/yeQzc8i/nRwGsx9HfVHm33QK3vCxpVzID4DA== X-Received: by 2002:a2e:2ac3:0:b0:277:83e:9adf with SMTP id q186-20020a2e2ac3000000b00277083e9adfmr3162321ljq.399.1668814377862; Fri, 18 Nov 2022 15:32:57 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:57 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform Date: Sat, 19 Nov 2022 01:32:40 +0200 Message-Id: <20221118233242.2904088-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm SM8350 platform. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 120 ++++++++++++++++++++++- 1 file changed, 119 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 4a55b2439952..8fa66458c259 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1315,6 +1315,40 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), +}; + static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), @@ -2021,6 +2055,80 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { + .lanes = 1, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), + .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), + .rx = sm8450_qmp_gen3_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), + .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), + .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), + }, + + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), + .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, + .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), + }, + + .clk_list = sc8280xp_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), + .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), + .rx = sm8450_qmp_gen3_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), + .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), + .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, + .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), + .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), + }, + + .clk_list = sc8280xp_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .lanes = 1, @@ -2617,7 +2725,11 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->pipe_clks[0].id = "pipe"; qmp->pipe_clks[1].id = "pipediv2"; - ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks); + ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); + if (ret) + return ret; + + ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); if (ret) return ret; @@ -2737,6 +2849,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sm8250-qmp-modem-pcie-phy", .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", + .data = &sm8350_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", + .data = &sm8350_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", .data = &sm8450_qmp_gen3x1_pciephy_cfg, From patchwork Fri Nov 18 23:32:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8020C4321E for ; Sat, 19 Nov 2022 00:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237412AbiKSAKL (ORCPT ); Fri, 18 Nov 2022 19:10:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237450AbiKSAJr (ORCPT ); Fri, 18 Nov 2022 19:09:47 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E85EA6585 for ; Fri, 18 Nov 2022 15:33:01 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id g7so10649149lfv.5 for ; Fri, 18 Nov 2022 15:33:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8pAbiS6lBqPLTBQAcAr3asHy+jv2W84FxrwZ4/IZM2c=; b=MAvpYzp5110g/RTqk83/eVe762g3GTx3X9cCR8GCDxvX/DnEplzhBDQ6CmeBwi/ZYx oAFFg3lbrg+6dsNy6wDSBhGxkm/uVq1ua1P3uHcKuwqPdL+aDK355bc4qQ6wa+z19FrX IqD58DfYBE4FDImI1tke3sJBmG6IAx1F46WPf1h6uaqHtOCeo8Cnive3C+1MGfTvq89t CcXL7dSeHZfiHaXwbk58G83FxXeCKDF9c6iY28eul4RA9W8qaa9jBqujpwwmO0OXhnNd zTBNymMMWAbvTEgFWRLY9uiEArEhRY7Hu1eVv3lFSPWjlTvk2XBdxSclutjQeIYdBk7R JlNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8pAbiS6lBqPLTBQAcAr3asHy+jv2W84FxrwZ4/IZM2c=; b=NUC2Fevuvn9k2lf2FL7quxSw4LDqJNoN43cophrh6vk5lKcquKZOTtfpLtBCE4Qqhe 65UGNmEvOvQdV/MsXM1xb59sHcWw3o0QyYuAZtT+aSOz81CdaHbhfPDv7/GGF+Y2LzdY RtKdBnHPDTN/KTR5+yN/FuI6AzQnTUIRKgQxxNS+ZSPZ29q29EEy+SdxIR5kDoxgMqTB +5QdDBaQYK3UiJM7fLGBuqfK7LXPGwQ1fttJ1Zhb2GWYE6IAHBUII2lOUqOm20YAZHXd Udb6asK6LonAHI9kJiq+YesiZs6eo0B9FAizxW/fj8HDC8isawfg/TKY7Rb0Fml8ZTn5 nP+w== X-Gm-Message-State: ANoB5pmh7gd3tyUAXMO/bm5Svk4M03I4cdX9U35p0ccs4Gr6dTcpwITE ROoUgS91nGOX92qNrSzDiKJD2Q== X-Google-Smtp-Source: AA0mqf7ExWwmm80O/ytmrT1l0LNHAffZnMvq/uQ8H1mPb57wmybSjJZSMZSW6E2O4U0F5AYYMF3+nA== X-Received: by 2002:a05:6512:3f29:b0:4b4:af05:4a8d with SMTP id y41-20020a0565123f2900b004b4af054a8dmr2937633lfa.415.1668814379838; Fri, 18 Nov 2022 15:32:59 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:59 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 7/8] arm64: dts: qcom: sm8350: add PCIe devices Date: Sat, 19 Nov 2022 01:32:41 +0200 Message-Id: <20221118233242.2904088-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350 platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 182 ++++++++++++++++++++++++++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 49db223a0777..b68f30d43f8a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -656,8 +656,8 @@ gcc: clock-controller@100000 { "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -1582,6 +1582,184 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0f000 { + compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,sm8350-lpass-ag-noc"; reg = <0 0x03c40000 0 0xf080>; From patchwork Fri Nov 18 23:32:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13049283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B811C4167D for ; Sat, 19 Nov 2022 00:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237478AbiKSAKT (ORCPT ); Fri, 18 Nov 2022 19:10:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237480AbiKSAJt (ORCPT ); Fri, 18 Nov 2022 19:09:49 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7B7BA65A0 for ; Fri, 18 Nov 2022 15:33:03 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id b3so10653148lfv.2 for ; Fri, 18 Nov 2022 15:33:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZZW/KVp2AUxGQEWc2f/qSxCfb9I/iYgRFf9DDe1VokY=; b=jeYxOBAae0nkZMhCajRWxNl4BsHIp/gJUcfUlzn4W//+IRNZdt4c+u4xkFcSSrbpF4 sh037Zjjh6OBFnXtZv+L9j+5jwN0QKPZYxbyNd0iVqa6l+skXoNYza9N/xnry4guT1n1 JKAYszaPm8LSW405Fg3GX108MPQgibCf63zG4K/d7lfbEBaF/OPiBxSqiEQDyWn0V89u 3s/LkPs2lOO7+dT0hFtLBww8jCLoHgxPEgyNI/Y2eBpse3FLvWGxCCOhrA25KKbVtkLp ICnFJYDcnPyMQ3lTLyzzP6PnPu0dA/hI/rzUWoZ52tMD651+ax1umuzGfsq5zPTCwWLM zhIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZZW/KVp2AUxGQEWc2f/qSxCfb9I/iYgRFf9DDe1VokY=; b=s3q2vDgWM+TNbHmSIwgOIjA9TWi/AXeqnMWqFyq18eOJ7n3mMg2u/sj1Uk2BnuJ7eE xszvsvPtt2PMbCNkNVKWpGFa60r09BcIrvQOoQgEx6Dv9ieX8vGIB7iMmbUV7cUH8pDR WurO5+P/WqoxkrXJzLDFndP/wg53+FRkF3N6iDaJMNDSfsZCCicLtTskaMDrd/gUI0C+ JJjHaCZ+5w6w1FtjvEFAeYO75PFfWPUyhQCORXaZQjg6ZOULDPa+6F0/Te1+zkdg+TZU VqV4oPCBram1RxLeVyPESNHEuUu7KqhQjukIVJOvYvBDrjOTPmkIxuEX1oeu4Jw+CRYR MwSA== X-Gm-Message-State: ANoB5pnUxJX2/+gKvJaISHH0AIIHbHJ1a/yv8P8Ht3VCrm7iBrImsFlP aRjspcfndbbwJTzYrRcADf5tJA== X-Google-Smtp-Source: AA0mqf4jXbJTDhzUsg9iV+s2DbbmtyvSGp9egr4e4Kb0jNBK31FGHn1NPHnPzzzMdZbTag2CRNWLMA== X-Received: by 2002:ac2:593c:0:b0:4b2:2cff:8448 with SMTP id v28-20020ac2593c000000b004b22cff8448mr2869937lfi.252.1668814381687; Fri, 18 Nov 2022 15:33:01 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:33:01 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 8/8] arm64: dts: qcom: sm8350-hdk: enable PCIe devices Date: Sat, 19 Nov 2022 01:32:42 +0200 Message-Id: <20221118233242.2904088-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIe0 and PCIe1 hosts found on SM8350 HDK board. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 80 +++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 69ae6503c2f6..bff75602303c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -234,6 +234,39 @@ &mpss { firmware-name = "qcom/sm8350/modem.mbn"; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -245,6 +278,53 @@ &slpi { &tlmm { gpio-reserved-ranges = <52 8>; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; &uart2 {