From patchwork Sat Nov 19 05:55:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13049610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 699B2C4332F for ; Sat, 19 Nov 2022 05:56:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1owGpy-000707-3D; Sat, 19 Nov 2022 00:56:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGpw-0006zj-1P for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:20 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGpu-0003CU-5I for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:19 -0500 Received: from [127.0.1.1] (unknown [62.118.138.151]) by mail.ispras.ru (Postfix) with ESMTPSA id 7FEC340737C9; Sat, 19 Nov 2022 05:55:54 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 7FEC340737C9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1668837354; bh=lopgE0Ztaf5xd+Ce41J0Qzs4CnNliZvUDcGDp4IkyFY=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=M44dHtdQPdILuhwPhkYPk2hnbNW40nOltu91t17KIO7DvgflParb/SA/UvbBFb+WU WBRTxvXmPins2cnshfxb8kbClHzvo8OrKUpxPx9k28P6YBA4JQ5LG7ijdqySU+aqGg WLZ52fXRreLwYCOR1XT079LO0MTCB7p3v8Etze14= Subject: [PATCH 1/4] target/avr: fix long address calculation From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Sat, 19 Nov 2022 08:55:54 +0300 Message-ID: <166883735424.1540909.1819992647141291951.stgit@pasha-ThinkPad-X280> In-Reply-To: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> References: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org AVR ELPMX instruction (and some others) use three registers to form long 24-bit address from RAMPZ and two 8-bit registers. RAMPZ stores shifted 8 bits like ff0000 to simplify address calculation. This patch fixes full address calculation in function gen_get_addr by changing the mess in offsets of deposit tcg instructions. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Richard Henderson Reviewed-by: Michael Rolnik --- target/avr/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index e65b6008c0..c9a0a39c2d 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1572,8 +1572,8 @@ static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) { TCGv addr = tcg_temp_new_i32(); - tcg_gen_deposit_tl(addr, M, H, 8, 8); - tcg_gen_deposit_tl(addr, L, addr, 8, 16); + tcg_gen_deposit_tl(addr, H, M, 8, 8); + tcg_gen_deposit_tl(addr, addr, L, 0, 8); return addr; } From patchwork Sat Nov 19 05:55:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13049614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32575C433FE for ; Sat, 19 Nov 2022 05:57:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1owGq3-00070g-FL; Sat, 19 Nov 2022 00:56:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGq0-00070G-UD for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:24 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGpy-0003Cx-Sw for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:24 -0500 Received: from [127.0.1.1] (unknown [62.118.138.151]) by mail.ispras.ru (Postfix) with ESMTPSA id F3EE040737CA; Sat, 19 Nov 2022 05:55:59 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru F3EE040737CA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1668837360; bh=XlZmL9qDLD0IhAjhBCIBkVUFND5Sk1/nWxHMaR2ZER4=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=Tc0pAjDvM1PEAsZ0rdYpRXWY9fb2x93lUl6gLDSbFbm2XFvhldMBCfxLs7wdnKh+2 oLw9u7fKNTscyOR2PZMmUB8p0rb+0NwQWluVx2GllxsGtq29tyBXtT6He76u6IGq52 hORDejFsSO62W1j5YUo+RTVvRDX3n36x/GD4KJz8= Subject: [PATCH 2/4] target/avr: implement small RAM/large RAM feature From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Sat, 19 Nov 2022 08:55:59 +0300 Message-ID: <166883735975.1540909.16334439765982123298.stgit@pasha-ThinkPad-X280> In-Reply-To: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> References: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org translate.c functions use RAMPZ for RAM access. This register is also used for ROM reads. However, in MCUs with 64k RAM support RAMPZ is used for ROM only. Therefore when RAMPZ is set, addressing the RAM becomes incorrect in the emulator. This patch adds LARGE RAM feature which can be used in xmega controllers, that could be added later. For the currently supported MCUs this feature is disabled and RAMPZ is not used for RAM access. Signed-off-by: Pavel Dovgalyuk --- target/avr/cpu.h | 2 ++ target/avr/translate.c | 63 ++++++++++++++++++++++++++++++------------------ 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 96419c0c2b..cfdc0ecb70 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -106,6 +106,8 @@ typedef enum AVRFeature { AVR_FEATURE_RAMPX, AVR_FEATURE_RAMPY, AVR_FEATURE_RAMPZ, + + AVR_FEATURE_LARGE_RAM, } AVRFeature; typedef struct CPUArchState { diff --git a/target/avr/translate.c b/target/avr/translate.c index c9a0a39c2d..e4900d630f 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1542,13 +1542,17 @@ static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) * M assumed to be in 0x000000ff format * L assumed to be in 0x000000ff format */ -static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) +static void gen_set_addr_short(TCGv addr, TCGv M, TCGv L) { - tcg_gen_andi_tl(L, addr, 0x000000ff); tcg_gen_andi_tl(M, addr, 0x0000ff00); tcg_gen_shri_tl(M, M, 8); +} + +static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) +{ + gen_set_addr_short(addr, M, L); tcg_gen_andi_tl(H, addr, 0x00ff0000); } @@ -1563,9 +1567,13 @@ static void gen_set_yaddr(TCGv addr) gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]); } -static void gen_set_zaddr(TCGv addr) +static void gen_set_zaddr(DisasContext *ctx, TCGv addr, bool ram) { - gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); + if (!ram || avr_feature(ctx->env, AVR_FEATURE_LARGE_RAM)) { + gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); + } else { + gen_set_addr_short(addr, cpu_r[31], cpu_r[30]); + } } static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) @@ -1588,9 +1596,16 @@ static TCGv gen_get_yaddr(void) return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]); } -static TCGv gen_get_zaddr(void) +static TCGv gen_get_zaddr(DisasContext *ctx, bool ram) { - return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); + if (!ram || avr_feature(ctx->env, AVR_FEATURE_LARGE_RAM)) { + return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); + } else { + TCGv zero = tcg_const_i32(0); + TCGv res = gen_get_addr(zero, cpu_r[31], cpu_r[30]); + tcg_temp_free_i32(zero); + return res; + } } /* @@ -1868,12 +1883,12 @@ static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); gen_data_load(ctx, Rd, addr); tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -1883,12 +1898,12 @@ static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ gen_data_load(ctx, Rd, addr); - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -1898,7 +1913,7 @@ static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ gen_data_load(ctx, Rd, addr); @@ -2088,12 +2103,12 @@ static bool trans_STDY(DisasContext *ctx, arg_STDY *a) static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); gen_data_store(ctx, Rd, addr); tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -2103,12 +2118,12 @@ static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ gen_data_store(ctx, Rd, addr); - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -2118,7 +2133,7 @@ static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ gen_data_store(ctx, Rd, addr); @@ -2228,7 +2243,7 @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) } TCGv Rd = cpu_r[0]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, false); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ @@ -2244,7 +2259,7 @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) } TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, false); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ @@ -2260,11 +2275,11 @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) } TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, false); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, false); tcg_temp_free_i32(addr); @@ -2402,7 +2417,7 @@ static bool trans_XCH(DisasContext *ctx, arg_XCH *a) TCGv Rd = cpu_r[a->rd]; TCGv t0 = tcg_temp_new_i32(); - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); gen_data_load(ctx, t0, addr); gen_data_store(ctx, Rd, addr); @@ -2432,7 +2447,7 @@ static bool trans_LAS(DisasContext *ctx, arg_LAS *a) } TCGv Rr = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); TCGv t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new_i32(); @@ -2467,7 +2482,7 @@ static bool trans_LAC(DisasContext *ctx, arg_LAC *a) } TCGv Rr = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); TCGv t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new_i32(); @@ -2502,7 +2517,7 @@ static bool trans_LAT(DisasContext *ctx, arg_LAT *a) } TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); TCGv t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new_i32(); From patchwork Sat Nov 19 05:56:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13049615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B41DC4332F for ; Sat, 19 Nov 2022 05:57:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1owGqQ-0007Cp-F1; Sat, 19 Nov 2022 00:56:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGq6-00070v-JK for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:31 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGq4-0003DA-MI for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:30 -0500 Received: from [127.0.1.1] (unknown [62.118.138.151]) by mail.ispras.ru (Postfix) with ESMTPSA id 70C7E40737CB; Sat, 19 Nov 2022 05:56:05 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 70C7E40737CB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1668837365; bh=yQAkQJtHjFZu7TmYoV6sC2gg5E0S7fZNsYpwZU15jdg=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=s59hxGnm2rQZJ8nuUDI/2/DOmcz8p2DAgc3iqVWMqI2K8Qehz6f8EFcmliHPKDDI3 xyevMRHYEZJhhEq+En2miIrd6t+fQtD6x9uSz3BmyBwkm9bT87Uo3aV4/xWGo0+jRi LOfa705UrZUuZg08JZxH8Fecun8l2zrQGVQSeWQw= Subject: [PATCH 3/4] target/avr: fix avr features processing From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Sat, 19 Nov 2022 08:56:05 +0300 Message-ID: <166883736523.1540909.13390410919692851470.stgit@pasha-ThinkPad-X280> In-Reply-To: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> References: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Bit vector for features has 64 bits. This patch fixes bit shifts in avr_feature and set_avr_feature functions to be 64-bit too. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Michael Rolnik --- target/avr/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index cfdc0ecb70..8295e50fa0 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -166,12 +166,12 @@ vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); static inline int avr_feature(CPUAVRState *env, AVRFeature feature) { - return (env->features & (1U << feature)) != 0; + return (env->features & (1ULL << feature)) != 0; } static inline void set_avr_feature(CPUAVRState *env, int feature) { - env->features |= (1U << feature); + env->features |= (1ULL << feature); } #define cpu_list avr_cpu_list From patchwork Sat Nov 19 05:56:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13049611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2692C4332F for ; Sat, 19 Nov 2022 05:56:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1owGqB-00074e-Si; Sat, 19 Nov 2022 00:56:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGq7-00070w-Bu for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:31 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1owGq5-0003DZ-RI for qemu-devel@nongnu.org; Sat, 19 Nov 2022 00:56:31 -0500 Received: from [127.0.1.1] (unknown [62.118.138.151]) by mail.ispras.ru (Postfix) with ESMTPSA id E7E3A40737D8; Sat, 19 Nov 2022 05:56:10 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru E7E3A40737D8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1668837371; bh=7bAqsqrVbTWaQc+AhA/m5Q6ztD9STpF91vF/3tnrKbs=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=kDXYqJhuTd7Yvakyr4Av4H8fCevSr3xg30E79F4+Fx4ZFrCAN8Zmpxhk5QSkL6UAY qOwt4rPBJ/dnyN1HzbAOkUbVoxojJybA8mS7Ots1449/H5GSYCgrdmfjZ2PoZMTy1t f2EvNGZpzk8gFsGdHQiOTLNImeoxZ3CsX50r9oc8= Subject: [PATCH 4/4] target/avr: fix interrupt processing From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Sat, 19 Nov 2022 08:56:10 +0300 Message-ID: <166883737070.1540909.16280727343064648296.stgit@pasha-ThinkPad-X280> In-Reply-To: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> References: <166883734868.1540909.6779276759642478650.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Interrupt bit vector has 64 bits, but interrupt vector is found with ctz32 function. This patch replaces it with ctz64. Signed-off-by: Pavel Dovgalyuk --- target/avr/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 156dde4e92..61ab6feb25 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -51,7 +51,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } if (interrupt_request & CPU_INTERRUPT_HARD) { if (cpu_interrupts_enabled(env) && env->intsrc != 0) { - int index = ctz32(env->intsrc); + int index = ctz64(env->intsrc); cs->exception_index = EXCP_INT(index); avr_cpu_do_interrupt(cs); @@ -78,7 +78,7 @@ void avr_cpu_do_interrupt(CPUState *cs) if (cs->exception_index == EXCP_RESET) { vector = 0; } else if (env->intsrc != 0) { - vector = ctz32(env->intsrc) + 1; + vector = ctz64(env->intsrc) + 1; } if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {