From patchwork Mon Nov 21 13:04:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13050886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5923AC43219 for ; Mon, 21 Nov 2022 13:04:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230043AbiKUNEW (ORCPT ); Mon, 21 Nov 2022 08:04:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229480AbiKUNEV (ORCPT ); Mon, 21 Nov 2022 08:04:21 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9D57326DA for ; Mon, 21 Nov 2022 05:04:18 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id l14so872907wrw.13 for ; Mon, 21 Nov 2022 05:04:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lcQAjzVivIzQj2w9iKAgRK1Du16HBMevQocYIlmnioc=; b=vX4H259eD8RhoO4kSAXbSzSeRlhQTv2XGt9JgkZ3WQhcZbREpLqO1IdxqMo+hwGhRO HYdGMaecdNg4KL2cEsqS76uSE/JVoZOvIlE4m5GSjPazcQgz46AolmzPACXeWTD0tfe1 3LwBvSNI0Ta54mPgYgRXTuzHixYeO3eNk6UEjBUak1s/Z3ZHAwLNB2JvgvB2VXt6fguW BPtRdXxcdf/JgirPEqQAs6Za8OEKUf2F8fosPtb4cf8J20Muzhb2k2QmPb+FqxDyWt9P KygKL+P9kmbMma/jCxfSM/pq1ubB3Akru6BWp5HlEFdoftosqzxZecf1AMqsoXMABEfO f+qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lcQAjzVivIzQj2w9iKAgRK1Du16HBMevQocYIlmnioc=; b=RMbrA7OFzRtGxxEMDzF2JNwhAdZkQH+O8SvJ28akAQcyqlEEuKN5qRcm85nKb5R9Fj rdPr3+qaG4k2jqkO4DqS3uH4z1W9Us0ROEsB5d9WAti1WQ4XdY/T39xKyQ/3gwl8DLBY L/mpicLxrHNxl3m2m/ewwcTADj2FZ2Gv1TqnUTvZkSTUaMaNKNAZ+YByvYg/GD0q9gKP lhSfyTaItPOa9ycTHZgg66HtmdOLR0ExJVhGt3X+NzU/xUdolF3fax4HErUbYxXDfpjc f/MGhJNeww5oC4r6egUNVLM4yJSfB9BLhdzDzYPyv4q4CZEuyk1tXQJhDp8mNvtBvME2 0niA== X-Gm-Message-State: ANoB5pnqiQtcu/WzzQ6EC9hxhG00nRJfNkeZ/Jqorp9gTrW/4S+TibaC bq2NUQMY2sbB79l8pZ0sfgUUjA== X-Google-Smtp-Source: AA0mqf4FxFE9yBJ+aw2hFn8IjkppIm3a/2jPd4xhwPRB69GMpY1Jz04V6UA8DrfZiRGiek+7dEL9tQ== X-Received: by 2002:a5d:5d0b:0:b0:241:9e29:17cd with SMTP id ch11-20020a5d5d0b000000b002419e2917cdmr11008044wrb.167.1669035857195; Mon, 21 Nov 2022 05:04:17 -0800 (PST) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id a13-20020a5d53cd000000b002383edcde09sm11133898wrw.59.2022.11.21.05.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:04:16 -0800 (PST) From: Srinivas Kandagatla To: agross@kernel.org, andersson@kernel.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 1/3] arm64: dts: qcom: sc8280xp/sa8540p: add gpr node Date: Mon, 21 Nov 2022 13:04:01 +0000 Message-Id: <20221121130403.161817-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130403.161817-1-srinivas.kandagatla@linaro.org> References: <20221121130403.161817-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add GPR node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index be72b1f7ad61..65b657f73ebb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include / { @@ -1626,6 +1627,44 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x0c01 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + clock-controller; + #clock-cells = <2>; + }; + }; + }; }; }; From patchwork Mon Nov 21 13:04:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13050887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E56BC4167D for ; Mon, 21 Nov 2022 13:04:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229677AbiKUNEX (ORCPT ); Mon, 21 Nov 2022 08:04:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229531AbiKUNEV (ORCPT ); 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Mon, 21 Nov 2022 05:04:17 -0800 (PST) From: Srinivas Kandagatla To: agross@kernel.org, andersson@kernel.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Krzysztof Kozlowski Subject: [PATCH v3 2/3] arm64: dts: qcom: sc8280xp/sa8540p: add SoundWire and LPASS Date: Mon, 21 Nov 2022 13:04:02 +0000 Message-Id: <20221121130403.161817-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130403.161817-1-srinivas.kandagatla@linaro.org> References: <20221121130403.161817-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add LPASS Codecs along with SoundWire controller for TX, RX, WSA and VA macros along with LPASS LPI pinctrl node. Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 320 +++++++++++++++++++++++++ 1 file changed, 320 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 65b657f73ebb..19b79c601417 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include / { @@ -1668,6 +1669,322 @@ q6prmcc: clock-controller { }; }; + rxmacro: rxmacro@3200000 { + compatible = "qcom,sc8280xp-lpass-rx-macro"; + reg = <0 0x03200000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + clock-output-names = "mclk"; + #clock-cells = <0>; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_default>; + }; + + /* RX */ + swr1: soundwire-controller@3210000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03210000 0 0x2000>; + interrupts = ; + clocks = <&rxmacro>; + clock-names = "iface"; + label = "RX"; + + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + txmacro: txmacro@3220000 { + compatible = "qcom,sc8280xp-lpass-tx-macro"; + reg = <0 0x03220000 0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_default>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + clock-output-names = "mclk"; + + #clock-cells = <0>; + #address-cells = <2>; + #size-cells = <2>; + #sound-dai-cells = <1>; + }; + + wsamacro: codec@3240000 { + compatible = "qcom,sc8280xp-lpass-wsa-macro"; + reg = <0 0x03240000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_default>; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + reg = <0 0x03250000 0 0x2000>; + compatible = "qcom,soundwire-v1.6.0"; + interrupts = ; + clocks = <&wsamacro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + /* TX */ + swr2: soundwire-controller@3330000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03330000 0 0x2000>; + interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wake"; + + clocks = <&vamacro>; + clock-names = "iface"; + label = "TX"; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>; + }; + + vamacro: codec@3370000 { + compatible = "qcom,sc8280xp-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec", "npl"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; + reg = <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 18>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + tx_swr_default: tx-swr-default-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_default: rx-swr-default-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic02_sleep: dmic02-sleep-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + wsa_swr_default: wsa-swr-default-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + + }; + }; + + wsa2_swr_default: wsa2-swr-default-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + usb_0_qmpphy: phy-wrapper@88ec000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x088ec000 0 0x1e4>, @@ -2507,6 +2824,9 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + sound: sound { + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; From patchwork Mon Nov 21 13:04:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13050888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5528FC433FE for ; Mon, 21 Nov 2022 13:04:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229847AbiKUNEY (ORCPT ); Mon, 21 Nov 2022 08:04:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230035AbiKUNEW (ORCPT ); Mon, 21 Nov 2022 08:04:22 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92BE24092F for ; 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This patch adds support for Headset Playback, record and 2 DMICs on the Panel along with the regulators required for powering up the LPASS codecs. Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 568c6be1ceaa..eefa22ea1ed7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -172,6 +172,14 @@ vreg_wwan: regulator-wwan { regulator-boot-on; }; + + vreg_vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "VPH_VCC3R9"; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + regulator-always-on; + }; }; &apps_rsc { @@ -181,6 +189,13 @@ pmc8280-1-rpmh-regulators { vdd-l3-l5-supply = <&vreg_s11b>; + vreg_s10b: smps10 { + regulator-name = "vreg_s10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + vreg_s11b: smps11 { regulator-name = "vreg_s11b"; regulator-min-microvolt = <1272000>; @@ -188,6 +203,13 @@ vreg_s11b: smps11 { regulator-initial-mode = ; }; + vreg_s12b: smps12 { + regulator-name = "vreg_s12b"; + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + vreg_l3b: ldo3 { regulator-name = "vreg_l3b"; regulator-min-microvolt = <1200000>; @@ -216,6 +238,7 @@ vreg_l6b: ldo6 { pmc8280c-rpmh-regulators { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; + vdd-bob-supply = <&vreg_vph_pwr>; vreg_l1c: ldo1 { regulator-name = "vreg_l1c"; @@ -237,6 +260,13 @@ vreg_l13c: ldo13 { regulator-max-microvolt = <3072000>; regulator-initial-mode = ; }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; }; pmc8280-2-rpmh-regulators { @@ -596,6 +626,161 @@ &remoteproc_nsp0 { status = "okay"; }; +&soc { + wcd938x: codec { + compatible = "qcom,wcd9380-codec"; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s10b>; + vdd-rxtx-supply = <&vreg_s10b>; + vdd-io-supply = <&vreg_s10b>; + vdd-mic-bias-supply = <&vreg_bob>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + }; +}; + +&sound { + compatible = "qcom,sc8280xp-sndcard"; + model = "SC8280XP-LENOVO-X13S"; + audio-routing = + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + + codec { + sound-dai = <&vamacro 0>; + }; + }; +}; + +&swr0 { + left_spkr: wsa8830-left@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_1_sd_n_default>; + powerdown-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + vdd-supply = <&vreg_s10b>; + }; + + right_spkr: wsa8830-right@0,2{ + compatible = "sdw10217020200"; + reg = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_default>; + powerdown-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + vdd-supply = <&vreg_s10b>; + }; +}; + +&swr1 { + status = "okay"; + + wcd_rx: wcd9380-rx@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + wcd_tx: wcd9380-tx@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-names = "default"; + vdd-micb-supply = <&vreg_s10b>; + qcom,dmic-sample-rate = <600000>; +}; + &usb_0 { status = "okay"; }; @@ -808,6 +993,26 @@ qup2_i2c5_default: qup2-i2c5-default-state { drive-strength = <16>; }; + spkr_1_sd_n_default: spkr-1-sd-n-default-state { + perst-n-pins { + pins = "gpio178"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spkr_2_sd_n_default: spkr-2-sd-n-default-state { + perst-n-pins { + pins = "gpio179"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + tpad_default: tpad-default-state { int-n-pins { pins = "gpio182"; @@ -830,4 +1035,12 @@ reset-n-pins { drive-strength = <16>; }; }; + + wcd_default: wcd-default-state { + reset-pins { + pins = "gpio106"; + function = "gpio"; + bias-disable; + }; + }; };