From patchwork Wed Nov 23 22:34:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E96F0C46467 for ; Wed, 23 Nov 2022 22:32:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FE5710E64E; Wed, 23 Nov 2022 22:31:46 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7AB7F10E650 for ; Wed, 23 Nov 2022 22:31:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669242701; x=1700778701; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=vWK2JgHEt3U6r/YQD33iBXdvfVjAGp9r9LBw9Tv6srk=; b=PiNR/CDsadTP5zRNxtQyLgBDmjEK0l1CYFZhlkFPe1miDqSOT8ftlsV/ x2Brs5tRWZF3vXNDzTbYATvMtdDsqdUYz+ABMCVWO0URfDG5Qm9ue4YH8 kEceywzhzeU1q2yLGqmERm4c4VPx9C89Y6R82N+D0RnNV17+99OZKyc67 UcYKFsVNPtIAmtAKpaz35ls8CJdk34DlgFeYxAfoobTDjdq4h/shX+SYu 1zmz81H4jiDoH6FD2bV887PW4SfwTSYN99+HRl3uiy0TiHACU/v4wfkeE og6VULMQLtrCY3iXZrYDdrLvYIdZf1YGCaz3K1HJZoNero8yv9TBR2v40 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="293875377" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="293875377" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 14:31:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="784404449" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404449" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:04 -0800 Message-Id: <20221123223410.2846296-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/7] HAX: drm/i915/pxp: Prepare intel_pxp entry points for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Squash of all the patches from the series: https://patchwork.freedesktop.org/series/109429/ Above series is not a prerequisite to showcase the design changes being proposed in the next set of patches but will be in the same order dependency as here. NOTE: that series will be going through a major redesign based on the latest review comments. Signed-off-by: Alan Previn --- .../drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 - drivers/gpu/drm/i915/pxp/intel_pxp.c | 83 ++++++++++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 18 +++- 12 files changed, 114 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 76490cc59d8f..3436bf433c10 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1848,7 +1848,7 @@ static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - return intel_pxp_key_check(&to_gt(i915)->pxp, obj, false) == 0; + return intel_pxp_key_check(i915, obj, false) == 0; } static bool pxp_is_borked(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 7f2831efc798..15c3d435093a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -257,7 +257,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, if (!protected) { pc->uses_protected_content = false; - } else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) { + } else if (!intel_pxp_is_enabled(i915)) { ret = -ENODEV; } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) || !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) { @@ -271,8 +271,8 @@ static int proto_context_set_protected(struct drm_i915_private *i915, */ pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); - if (!intel_pxp_is_active(&to_gt(i915)->pxp)) - ret = intel_pxp_start(&to_gt(i915)->pxp); + if (!intel_pxp_is_active(i915)) + ret = intel_pxp_start(i915); } return ret; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 33673fe7ee0a..e44803f9bec4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data if (ext.flags) return -EINVAL; - if (!intel_pxp_is_enabled(&to_gt(ext_data->i915)->pxp)) + if (!intel_pxp_is_enabled(ext_data->i915)) return -ENODEV; ext_data->flags |= I915_BO_PROTECTED; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 29e9e8d5b6fe..9943d5827300 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -869,7 +869,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) */ if (i915_gem_context_uses_protected_content(eb->gem_context) && i915_gem_object_is_protected(obj)) { - err = intel_pxp_key_check(&vm->gt->pxp, obj, true); + err = intel_pxp_key_check(vm->gt->i915, obj, true); if (err) { i915_gem_object_put(obj); return ERR_PTR(err); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a380db36d52c..a171ad57fe73 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -918,10 +918,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) -#define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \ - INTEL_INFO(dev_priv)->has_pxp) && \ - VDBOX_MASK(to_gt(dev_priv))) - #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 5efe61f67546..58219beecfa4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -9,6 +9,7 @@ #include "intel_pxp_tee.h" #include "gem/i915_gem_context.h" #include "gt/intel_context.h" +#include "gt/intel_gt.h" #include "i915_drv.h" /** @@ -44,16 +45,63 @@ struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) return container_of(pxp, struct intel_gt, pxp); } -bool intel_pxp_is_enabled(const struct intel_pxp *pxp) +static bool _gt_needs_teelink(struct intel_gt *gt) +{ + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && intel_huc_is_loaded_by_gsc(>->uc.huc) && + intel_uc_uses_huc(>->uc)); +} + +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp) +{ + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_DRM_I915_PXP) && + INTEL_INFO((pxp_to_gt(pxp))->i915)->has_pxp && VDBOX_MASK(pxp_to_gt(pxp))); +} + +bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp) { return pxp->ce; } -bool intel_pxp_is_active(const struct intel_pxp *pxp) +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915) +{ + struct intel_gt *gt = NULL; + int i = 0; + + for_each_gt(gt, i915, i) { + /* There can be only one GT that supports PXP */ + if (intel_pxp_supported_on_gt(>->pxp)) + return gt; + } + return NULL; +} + +bool intel_pxp_is_enabled(struct drm_i915_private *i915) +{ + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + + if (!gt) + return false; + + return intel_pxp_is_enabled_on_gt(>->pxp); +} + +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp) { return pxp->arb_is_valid; } +bool intel_pxp_is_active(struct drm_i915_private *i915) +{ + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + + if (!gt) + return false; + + return intel_pxp_is_active_on_gt(>->pxp); +} + /* KCR register definitions */ #define KCR_INIT _MMIO(0x320f0) /* Setting KCR Init bit is required after system boot */ @@ -142,17 +190,13 @@ void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = pxp_to_gt(pxp); - /* we rely on the mei PXP module */ - if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP)) - return; - /* * If HuC is loaded by GSC but PXP is disabled, we can skip the init of * the full PXP session/object management and just init the tee channel. */ - if (HAS_PXP(gt->i915)) + if (intel_pxp_supported_on_gt(pxp)) pxp_init_full(pxp); - else if (intel_huc_is_loaded_by_gsc(>->uc.huc) && intel_uc_uses_huc(>->uc)) + else if (_gt_needs_teelink(gt)) intel_pxp_tee_component_init(pxp); } @@ -202,11 +246,18 @@ static bool pxp_component_bound(struct intel_pxp *pxp) * the arb session is restarted from the irq work when we receive the * termination completion interrupt */ -int intel_pxp_start(struct intel_pxp *pxp) +int intel_pxp_start(struct drm_i915_private *i915) { + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; int ret = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!gt) + return -ENODEV; + + pxp = >->pxp; + + if (!intel_pxp_is_enabled_on_gt(pxp)) return -ENODEV; if (wait_for(pxp_component_bound(pxp), 250)) @@ -249,11 +300,19 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp) intel_pxp_irq_disable(pxp); } -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign) { - if (!intel_pxp_is_active(pxp)) + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; + + if (!gt) + return -ENODEV; + + pxp = >->pxp; + + if (!intel_pxp_is_active_on_gt(pxp)) return -ENODEV; if (!i915_gem_object_is_protected(obj)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 2da309088c6d..6fe1595a84d6 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -11,10 +11,18 @@ struct intel_pxp; struct drm_i915_gem_object; +struct drm_i915_private; + +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915); struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); -bool intel_pxp_is_enabled(const struct intel_pxp *pxp); -bool intel_pxp_is_active(const struct intel_pxp *pxp); + +bool intel_pxp_supported_on_gt(const struct intel_pxp *pxp); + +bool intel_pxp_is_enabled_on_gt(const struct intel_pxp *pxp); +bool intel_pxp_is_enabled(struct drm_i915_private *i915); +bool intel_pxp_is_active_on_gt(const struct intel_pxp *pxp); +bool intel_pxp_is_active(struct drm_i915_private *i915); void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); @@ -24,9 +32,9 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); -int intel_pxp_start(struct intel_pxp *pxp); +int intel_pxp_start(struct drm_i915_private *i915); -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c index f41e45763d0d..f322a49ebadc 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -99,7 +99,7 @@ int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id) u32 *cs; int err = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return 0; rq = i915_request_create(ce); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4359e8be4101..52a808fd4704 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -18,14 +18,14 @@ static int pxp_info_show(struct seq_file *m, void *data) { struct intel_pxp *pxp = m->private; struct drm_printer p = drm_seq_file_printer(m); - bool enabled = intel_pxp_is_enabled(pxp); + bool enabled = intel_pxp_is_enabled_on_gt(pxp); if (!enabled) { drm_printf(&p, "pxp disabled\n"); return 0; } - drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp))); + drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active_on_gt(pxp))); drm_printf(&p, "instance counter: %u\n", pxp->key_instance); return 0; @@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val) struct intel_pxp *pxp = data; struct intel_gt *gt = pxp_to_gt(pxp); - if (!intel_pxp_is_active(pxp)) + if (!intel_pxp_is_active_on_gt(pxp)) return -ENODEV; /* simulate a termination interrupt */ @@ -70,7 +70,7 @@ void intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *gt_root) if (!gt_root) return; - if (!HAS_PXP((pxp_to_gt(pxp)->i915))) + if (!intel_pxp_supported_on_gt(pxp)) return; root = debugfs_create_dir("pxp", gt_root); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index c28be430718a..c25c1979cccc 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -22,7 +22,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { struct intel_gt *gt = pxp_to_gt(pxp); - if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) + if (GEM_WARN_ON(!intel_pxp_is_enabled_on_gt(pxp))) return; lockdep_assert_held(gt->irq_lock); @@ -86,7 +86,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp) * called in a path were the driver consider the session as valid and * doesn't call a termination on restart. */ - GEM_WARN_ON(intel_pxp_is_active(pxp)); + GEM_WARN_ON(intel_pxp_is_active_on_gt(pxp)); spin_lock_irq(gt->irq_lock); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 6a7d4e2ee138..19ac8828cbde 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -11,7 +11,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; pxp->arb_is_valid = false; @@ -23,7 +23,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) { intel_wakeref_t wakeref; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; with_intel_runtime_pm(&pxp_to_gt(pxp)->i915->runtime_pm, wakeref) { @@ -34,7 +34,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) void intel_pxp_resume(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; /* @@ -50,7 +50,7 @@ void intel_pxp_resume(struct intel_pxp *pxp) void intel_pxp_runtime_suspend(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled_on_gt(pxp)) return; pxp->arb_is_valid = false; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index b0c9170b1395..b9198e961cb6 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -20,8 +20,12 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); - return &to_gt(i915)->pxp; + if (!gt) + return NULL; + + return >->pxp; } static int intel_pxp_tee_io_message(struct intel_pxp *pxp, @@ -128,10 +132,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); - struct intel_uc *uc = &pxp_to_gt(pxp)->uc; + struct intel_uc *uc; intel_wakeref_t wakeref; int ret = 0; + if (!pxp) { + drm_warn(&i915->drm, "tee comp binding without a PXP-owner GT\n"); + return -ENODEV; + } + uc = &pxp_to_gt(pxp)->uc; + mutex_lock(&pxp->tee_mutex); pxp->pxp_component = data; pxp->pxp_component->tee_dev = tee_kdev; @@ -152,7 +162,7 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, return 0; /* the component is required to fully start the PXP HW */ - if (intel_pxp_is_enabled(pxp)) + if (intel_pxp_is_enabled_on_gt(pxp)) intel_pxp_init_hw(pxp); intel_runtime_pm_put(&i915->runtime_pm, wakeref); @@ -167,7 +177,7 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); intel_wakeref_t wakeref; - if (intel_pxp_is_enabled(pxp)) + if (intel_pxp_is_enabled_on_gt(pxp)) with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) intel_pxp_fini_hw(pxp); From patchwork Wed Nov 23 22:34:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A574EC4332F for ; Wed, 23 Nov 2022 22:32:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E15E310E650; Wed, 23 Nov 2022 22:31:46 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9990D10E651 for ; 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a="784404452" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404452" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:05 -0800 Message-Id: <20221123223410.2846296-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 2/7] drm/i915/pxp: Refactor mei-teelink checks at init/fini X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In preparation of MTL-pxp support, add helper functions to determine if teelink is required and to determine the type of teelink for the current gt-pxp subsystem. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 6 +++--- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 26 ++++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 58219beecfa4..33f86bb05148 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -174,7 +174,7 @@ static void pxp_init_full(struct intel_pxp *pxp) if (ret) return; - ret = intel_pxp_tee_component_init(pxp); + ret = intel_pxp_teelink_init(pxp); if (ret) goto out_context; @@ -197,14 +197,14 @@ void intel_pxp_init(struct intel_pxp *pxp) if (intel_pxp_supported_on_gt(pxp)) pxp_init_full(pxp); else if (_gt_needs_teelink(gt)) - intel_pxp_tee_component_init(pxp); + intel_pxp_teelink_init(pxp); } void intel_pxp_fini(struct intel_pxp *pxp) { pxp->arb_is_valid = false; - intel_pxp_tee_component_fini(pxp); + intel_pxp_teelink_fini(pxp); destroy_vcs_context(pxp); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index b9198e961cb6..23a848b52c75 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -319,3 +319,29 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, return ret; } + +static bool gt_supports_teelink_via_mei(struct intel_gt *gt) +{ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0)); +} + +int intel_pxp_teelink_init(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + int ret = -ENOLINK; + + if (!gt_supports_teelink_via_mei(gt)) + return -ENODEV; + + ret = intel_pxp_tee_component_init(pxp); + if (ret) + drm_warn(>->i915->drm, "Teelink initialization failed with %d\n", ret); + + return ret; +} + +void intel_pxp_teelink_fini(struct intel_pxp *pxp) +{ + intel_pxp_tee_component_fini(pxp); +} + diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h index aeb3dfe7ce96..62995e95773f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -19,4 +19,7 @@ int intel_pxp_tee_stream_message(struct intel_pxp *pxp, void *msg_in, size_t msg_in_len, void *msg_out, size_t msg_out_len); +int intel_pxp_teelink_init(struct intel_pxp *pxp); +void intel_pxp_teelink_fini(struct intel_pxp *pxp); + #endif /* __INTEL_PXP_TEE_H__ */ From patchwork Wed Nov 23 22:34:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 156C0C4332F for ; Wed, 23 Nov 2022 22:32:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC45B10E652; Wed, 23 Nov 2022 22:31:49 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B444310E653 for ; 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a="784404453" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404453" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:06 -0800 Message-Id: <20221123223410.2846296-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 3/7] drm/i915/pxp: Abstract mei-teelink function access via backend ptrs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Abstract mei-teelink function access via backend ptrs Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 9 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 107 ++++++++++++++----- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 15 ++- drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 22 ++++ 5 files changed, 112 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c index 2e1165522950..043344dbf566 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c @@ -23,8 +23,6 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp) struct pxp43_start_huc_auth_in huc_in = {0}; struct pxp43_start_huc_auth_out huc_out = {0}; dma_addr_t huc_phys_addr; - u8 client_id = 0; - u8 fence_id = 0; int err; if (!pxp->pxp_component) @@ -39,9 +37,10 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp) huc_in.header.buffer_len = sizeof(huc_in.huc_base_address); huc_in.huc_base_address = huc_phys_addr; - err = intel_pxp_tee_stream_message(pxp, client_id, fence_id, - &huc_in, sizeof(huc_in), - &huc_out, sizeof(huc_out)); + err = intel_pxp_teelink_send_message(pxp, + &huc_in, sizeof(huc_in), + &huc_out, sizeof(huc_out), + NULL); if (err < 0) { drm_err(>->i915->drm, "Failed to send HuC load and auth command to GSC [%d]!\n", diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c index 85572360c71a..dec209e57596 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -66,7 +66,7 @@ static int pxp_create_arb_session(struct intel_pxp *pxp) return -EEXIST; } - ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION); + ret = intel_pxp_teelink_create_session(pxp, ARB_SESSION); if (ret) { drm_err(>->i915->drm, "tee cmd for arb session creation failed\n"); return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 23a848b52c75..fa41f4224333 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -28,10 +28,10 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) return >->pxp; } -static int intel_pxp_tee_io_message(struct intel_pxp *pxp, - void *msg_in, u32 msg_in_size, - void *msg_out, u32 msg_out_max_size, - u32 *msg_out_rcv_size) +static int mei_tee_io_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_max_size, + size_t *msg_out_size) { struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; struct i915_pxp_component *pxp_component = pxp->pxp_component; @@ -67,8 +67,8 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp, goto unlock; } - if (msg_out_rcv_size) - *msg_out_rcv_size = ret; + if (msg_out_size) + *msg_out_size = ret; ret = 0; unlock: @@ -76,10 +76,10 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp, return ret; } -int intel_pxp_tee_stream_message(struct intel_pxp *pxp, - u8 client_id, u32 fence_id, - void *msg_in, size_t msg_in_len, - void *msg_out, size_t msg_out_len) +static int mei_tee_gsc_stream_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_max_size, + size_t *msg_out_size) { /* TODO: for bigger objects we need to use a sg of 4k pages */ const size_t max_msg_size = PAGE_SIZE; @@ -89,7 +89,7 @@ int intel_pxp_tee_stream_message(struct intel_pxp *pxp, struct scatterlist *sg; int ret; - if (msg_in_len > max_msg_size || msg_out_len > max_msg_size) + if (msg_in_size > max_msg_size || msg_out_max_size > max_msg_size) return -ENOSPC; mutex_lock(&pxp->tee_mutex); @@ -103,14 +103,14 @@ int intel_pxp_tee_stream_message(struct intel_pxp *pxp, sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, &offset); - memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_len); + memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_size); - ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, client_id, - fence_id, sg, msg_in_len, sg); + ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, 0, 0, + sg, msg_in_size, sg); if (ret < 0) drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); else - memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_len); + memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_max_size); unlock: mutex_unlock(&pxp->tee_mutex); @@ -251,7 +251,7 @@ static void free_streaming_command(struct intel_pxp *pxp) i915_gem_object_put(obj); } -int intel_pxp_tee_component_init(struct intel_pxp *pxp) +static int mei_tee_component_init(struct intel_pxp *pxp) { int ret; struct intel_gt *gt = pxp_to_gt(pxp); @@ -279,7 +279,7 @@ int intel_pxp_tee_component_init(struct intel_pxp *pxp) return ret; } -void intel_pxp_tee_component_fini(struct intel_pxp *pxp) +static void mei_tee_component_fini(struct intel_pxp *pxp) { struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; @@ -292,8 +292,8 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp) free_streaming_command(pxp); } -int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, - int arb_session_id) +static int mei_tee_create_session(struct intel_pxp *pxp, + int session_id) { struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; struct pxp42_create_arb_in msg_in = {0}; @@ -304,12 +304,12 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, msg_in.header.command_id = PXP42_CMDID_INIT_SESSION; msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); msg_in.protection_mode = PXP42_ARB_SESSION_MODE_HEAVY; - msg_in.session_id = arb_session_id; + msg_in.session_id = session_id; - ret = intel_pxp_tee_io_message(pxp, - &msg_in, sizeof(msg_in), - &msg_out, sizeof(msg_out), - NULL); + ret = mei_tee_io_message(pxp, + &msg_in, sizeof(msg_in), + &msg_out, sizeof(msg_out), + NULL); if (ret) drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret); @@ -320,6 +320,54 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, return ret; } +int intel_pxp_teelink_create_session(struct intel_pxp *pxp, + int arb_session_id) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + int ret; + + if (!pxp->tee_link.create_session) + ret = -ENOLINK; + else + ret = pxp->tee_link.create_session(pxp, arb_session_id); + + if (ret) + drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret); + + return ret; +} + +int intel_pxp_teelink_send_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_size, + size_t *msg_out_max_size) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + + if (!pxp->tee_link.send_message) { + drm_dbg(&i915->drm, "Failed on func ptr for TEE send_message\n"); + return -ENOLINK; + } + + return pxp->tee_link.send_message(pxp, + msg_in, msg_in_size, + msg_out, msg_out_size, + msg_out_max_size); +} + +static void mei_tee_init_hooks(struct intel_pxp *pxp) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + + pxp->tee_link.init = mei_tee_component_init; + pxp->tee_link.fini = mei_tee_component_fini; + pxp->tee_link.create_session = mei_tee_create_session; + if (IS_DG2(i915)) + pxp->tee_link.send_message = mei_tee_gsc_stream_message; + else + pxp->tee_link.send_message = mei_tee_io_message; +} + static bool gt_supports_teelink_via_mei(struct intel_gt *gt) { return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0)); @@ -333,15 +381,18 @@ int intel_pxp_teelink_init(struct intel_pxp *pxp) if (!gt_supports_teelink_via_mei(gt)) return -ENODEV; - ret = intel_pxp_tee_component_init(pxp); + mei_tee_init_hooks(pxp); + + if (pxp->tee_link.init) + ret = pxp->tee_link.init(pxp); if (ret) - drm_warn(>->i915->drm, "Teelink initialization failed with %d\n", ret); + drm_warn(>->i915->drm, "Tee transport initialization failed with %d\n", ret); return ret; } void intel_pxp_teelink_fini(struct intel_pxp *pxp) { - intel_pxp_tee_component_fini(pxp); + if (pxp->tee_link.fini) + pxp->tee_link.fini(pxp); } - diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h index 62995e95773f..4c1d38fa314a 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -8,16 +8,13 @@ #include "intel_pxp.h" -int intel_pxp_tee_component_init(struct intel_pxp *pxp); -void intel_pxp_tee_component_fini(struct intel_pxp *pxp); +int intel_pxp_teelink_send_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_size, + size_t *msg_out_max_size); -int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, - int arb_session_id); - -int intel_pxp_tee_stream_message(struct intel_pxp *pxp, - u8 client_id, u32 fence_id, - void *msg_in, size_t msg_in_len, - void *msg_out, size_t msg_out_len); +int intel_pxp_teelink_create_session(struct intel_pxp *pxp, + int arb_session_id); int intel_pxp_teelink_init(struct intel_pxp *pxp); void intel_pxp_teelink_fini(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index f74b1e11a505..6de79a46ceed 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -82,6 +82,28 @@ struct intel_pxp { #define PXP_TERMINATION_REQUEST BIT(0) #define PXP_TERMINATION_COMPLETE BIT(1) #define PXP_INVAL_REQUIRED BIT(2) + + /** + * @tee_link: function pointers to backend tee transport layer. + * These hooks will point to device specific implementations. + */ + struct { + /* Called to initialize the backend transport resources.*/ + int (*init)(struct intel_pxp *pxp); + + /* Called to free the backend transport resources.*/ + void (*fini)(struct intel_pxp *pxp); + + /* Called to create a pxp session.*/ + int (*create_session)(struct intel_pxp *pxp, int session_id); + + /* Called to send message packets to pxp firmware.*/ + int (*send_message)(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_len, + void *msg_out, size_t msg_out_max_len, + size_t *msg_out_len); + } tee_link; + }; #endif /* __INTEL_PXP_TYPES_H__ */ From patchwork Wed Nov 23 22:34:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E532C4332F for ; Wed, 23 Nov 2022 22:32:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F04110E65B; Wed, 23 Nov 2022 22:32:11 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id CE51F10E654 for ; Wed, 23 Nov 2022 22:31:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669242701; x=1700778701; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WyfDOr600m1RGX7lOCGjlX04ktu4blLPTFArHQixwKg=; b=ebzOq2dRszvF9igufVxSYB7ASr5qrzZfupPA+/FQEf+n3eHyMJpjPs+X YPfnj9qdq4Ch0+RbOB7I4abkIBsJOSp0hHYeZibZ+uDB3BLhMJBdLVfIz UrdwoirG7cn7PgBnNXJatROp20WNnZs/+k1OhLwWYDJPY9Z8RZnXnaUoB FzHynNZDZ0aWtIUdmcDk/3CUMyfFaBnhd/csoWpgG526IP7jwtj2HKJaE gKYrswRKSUDn7IUqY8CHX0FRoIlUJrK67SceGafClmNNoEfDdpmuksi9N kFZwk9A4Q6KmGXMcJMKRG6tn/3URGBVNEaW6GQhQM7fyGz6V3E7jylOeE Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="293875380" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="293875380" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 14:31:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="784404454" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404454" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:07 -0800 Message-Id: <20221123223410.2846296-5-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 4/7] drm/i915/pxp: Separate tee-link front end interfaces from backend implementation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Separate tee-link front end interfaces from backend implementation. Duplicate intel_pxp_tee to intel_pxp_tee_mei keep the front end side (like populating the backend hooks) in the former while keeping the mei backend (like send_message) in the _mei variant. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 329 +----------------- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 16 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c | 334 +++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h | 13 + 5 files changed, 359 insertions(+), 334 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 01974b82d205..6ed45d9145e8 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -319,6 +319,7 @@ i915-y += i915_perf.o i915-y += \ pxp/intel_pxp.o \ pxp/intel_pxp_tee.o \ + pxp/intel_pxp_tee_mei.o \ pxp/intel_pxp_huc.o i915-$(CONFIG_DRM_I915_PXP) += \ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index fa41f4224333..034e2eee5075 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -3,322 +3,10 @@ * Copyright(c) 2020 Intel Corporation. */ -#include - -#include -#include - -#include "gem/i915_gem_lmem.h" - #include "i915_drv.h" #include "intel_pxp.h" -#include "intel_pxp_session.h" #include "intel_pxp_tee.h" -#include "intel_pxp_cmd_interface_42.h" -#include "intel_pxp_huc.h" - -static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) -{ - struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); - struct intel_gt *gt = intel_pxp_get_owning_gt(i915); - - if (!gt) - return NULL; - - return >->pxp; -} - -static int mei_tee_io_message(struct intel_pxp *pxp, - void *msg_in, size_t msg_in_size, - void *msg_out, size_t msg_out_max_size, - size_t *msg_out_size) -{ - struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - struct i915_pxp_component *pxp_component = pxp->pxp_component; - int ret = 0; - - mutex_lock(&pxp->tee_mutex); - - /* - * The binding of the component is asynchronous from i915 probe, so we - * can't be sure it has happened. - */ - if (!pxp_component) { - ret = -ENODEV; - goto unlock; - } - - ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in, msg_in_size); - if (ret) { - drm_err(&i915->drm, "Failed to send PXP TEE message\n"); - goto unlock; - } - - ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out, msg_out_max_size); - if (ret < 0) { - drm_err(&i915->drm, "Failed to receive PXP TEE message\n"); - goto unlock; - } - - if (ret > msg_out_max_size) { - drm_err(&i915->drm, - "Failed to receive PXP TEE message due to unexpected output size\n"); - ret = -ENOSPC; - goto unlock; - } - - if (msg_out_size) - *msg_out_size = ret; - - ret = 0; -unlock: - mutex_unlock(&pxp->tee_mutex); - return ret; -} - -static int mei_tee_gsc_stream_message(struct intel_pxp *pxp, - void *msg_in, size_t msg_in_size, - void *msg_out, size_t msg_out_max_size, - size_t *msg_out_size) -{ - /* TODO: for bigger objects we need to use a sg of 4k pages */ - const size_t max_msg_size = PAGE_SIZE; - struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - struct i915_pxp_component *pxp_component = pxp->pxp_component; - unsigned int offset = 0; - struct scatterlist *sg; - int ret; - - if (msg_in_size > max_msg_size || msg_out_max_size > max_msg_size) - return -ENOSPC; - - mutex_lock(&pxp->tee_mutex); - - if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) { - ret = -ENODEV; - goto unlock; - } - - GEM_BUG_ON(!pxp->stream_cmd.obj); - - sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, &offset); - - memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_size); - - ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, 0, 0, - sg, msg_in_size, sg); - if (ret < 0) - drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); - else - memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_max_size); - -unlock: - mutex_unlock(&pxp->tee_mutex); - return ret; -} - -/** - * i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee - * @i915_kdev: pointer to i915 kernel device - * @tee_kdev: pointer to tee kernel device - * @data: pointer to pxp_tee_master containing the function pointers - * - * This bind function is called during the system boot or resume from system sleep. - * - * Return: return 0 if successful. - */ -static int i915_pxp_tee_component_bind(struct device *i915_kdev, - struct device *tee_kdev, void *data) -{ - struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); - struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); - struct intel_uc *uc; - intel_wakeref_t wakeref; - int ret = 0; - - if (!pxp) { - drm_warn(&i915->drm, "tee comp binding without a PXP-owner GT\n"); - return -ENODEV; - } - uc = &pxp_to_gt(pxp)->uc; - - mutex_lock(&pxp->tee_mutex); - pxp->pxp_component = data; - pxp->pxp_component->tee_dev = tee_kdev; - mutex_unlock(&pxp->tee_mutex); - - if (intel_uc_uses_huc(uc) && intel_huc_is_loaded_by_gsc(&uc->huc)) { - with_intel_runtime_pm(&i915->runtime_pm, wakeref) { - /* load huc via pxp */ - ret = intel_huc_fw_load_and_auth_via_gsc(&uc->huc); - if (ret < 0) - drm_err(&i915->drm, "failed to load huc via gsc %d\n", ret); - } - } - - /* if we are suspended, the HW will be re-initialized on resume */ - wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm); - if (!wakeref) - return 0; - - /* the component is required to fully start the PXP HW */ - if (intel_pxp_is_enabled_on_gt(pxp)) - intel_pxp_init_hw(pxp); - - intel_runtime_pm_put(&i915->runtime_pm, wakeref); - - return ret; -} - -static void i915_pxp_tee_component_unbind(struct device *i915_kdev, - struct device *tee_kdev, void *data) -{ - struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); - struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); - intel_wakeref_t wakeref; - - if (intel_pxp_is_enabled_on_gt(pxp)) - with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) - intel_pxp_fini_hw(pxp); - - mutex_lock(&pxp->tee_mutex); - pxp->pxp_component = NULL; - mutex_unlock(&pxp->tee_mutex); -} - -static const struct component_ops i915_pxp_tee_component_ops = { - .bind = i915_pxp_tee_component_bind, - .unbind = i915_pxp_tee_component_unbind, -}; - -static int alloc_streaming_command(struct intel_pxp *pxp) -{ - struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - struct drm_i915_gem_object *obj = NULL; - void *cmd; - int err; - - pxp->stream_cmd.obj = NULL; - pxp->stream_cmd.vaddr = NULL; - - if (!IS_DGFX(i915)) - return 0; - - /* allocate lmem object of one page for PXP command memory and store it */ - obj = i915_gem_object_create_lmem(i915, PAGE_SIZE, I915_BO_ALLOC_CONTIGUOUS); - if (IS_ERR(obj)) { - drm_err(&i915->drm, "Failed to allocate pxp streaming command!\n"); - return PTR_ERR(obj); - } - - err = i915_gem_object_pin_pages_unlocked(obj); - if (err) { - drm_err(&i915->drm, "Failed to pin gsc message page!\n"); - goto out_put; - } - - /* map the lmem into the virtual memory pointer */ - cmd = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(i915, obj, true)); - if (IS_ERR(cmd)) { - drm_err(&i915->drm, "Failed to map gsc message page!\n"); - err = PTR_ERR(cmd); - goto out_unpin; - } - - memset(cmd, 0, obj->base.size); - - pxp->stream_cmd.obj = obj; - pxp->stream_cmd.vaddr = cmd; - - return 0; - -out_unpin: - i915_gem_object_unpin_pages(obj); -out_put: - i915_gem_object_put(obj); - return err; -} - -static void free_streaming_command(struct intel_pxp *pxp) -{ - struct drm_i915_gem_object *obj = fetch_and_zero(&pxp->stream_cmd.obj); - - if (!obj) - return; - - i915_gem_object_unpin_map(obj); - i915_gem_object_unpin_pages(obj); - i915_gem_object_put(obj); -} - -static int mei_tee_component_init(struct intel_pxp *pxp) -{ - int ret; - struct intel_gt *gt = pxp_to_gt(pxp); - struct drm_i915_private *i915 = gt->i915; - - mutex_init(&pxp->tee_mutex); - - ret = alloc_streaming_command(pxp); - if (ret) - return ret; - - ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops, - I915_COMPONENT_PXP); - if (ret < 0) { - drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret); - goto out_free; - } - - pxp->pxp_component_added = true; - - return 0; - -out_free: - free_streaming_command(pxp); - return ret; -} - -static void mei_tee_component_fini(struct intel_pxp *pxp) -{ - struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - - if (!pxp->pxp_component_added) - return; - - component_del(i915->drm.dev, &i915_pxp_tee_component_ops); - pxp->pxp_component_added = false; - - free_streaming_command(pxp); -} - -static int mei_tee_create_session(struct intel_pxp *pxp, - int session_id) -{ - struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - struct pxp42_create_arb_in msg_in = {0}; - struct pxp42_create_arb_out msg_out = {0}; - int ret; - - msg_in.header.api_version = PXP_APIVER(4, 2); - msg_in.header.command_id = PXP42_CMDID_INIT_SESSION; - msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); - msg_in.protection_mode = PXP42_ARB_SESSION_MODE_HEAVY; - msg_in.session_id = session_id; - - ret = mei_tee_io_message(pxp, - &msg_in, sizeof(msg_in), - &msg_out, sizeof(msg_out), - NULL); - - if (ret) - drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret); - else if (msg_out.header.status != 0x0) - drm_warn(&i915->drm, "PXP firmware failed arb session init request ret=[0x%08x]\n", - msg_out.header.status); - - return ret; -} +#include "intel_pxp_tee_mei.h" int intel_pxp_teelink_create_session(struct intel_pxp *pxp, int arb_session_id) @@ -355,19 +43,6 @@ int intel_pxp_teelink_send_message(struct intel_pxp *pxp, msg_out_max_size); } -static void mei_tee_init_hooks(struct intel_pxp *pxp) -{ - struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - - pxp->tee_link.init = mei_tee_component_init; - pxp->tee_link.fini = mei_tee_component_fini; - pxp->tee_link.create_session = mei_tee_create_session; - if (IS_DG2(i915)) - pxp->tee_link.send_message = mei_tee_gsc_stream_message; - else - pxp->tee_link.send_message = mei_tee_io_message; -} - static bool gt_supports_teelink_via_mei(struct intel_gt *gt) { return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0)); @@ -381,7 +56,7 @@ int intel_pxp_teelink_init(struct intel_pxp *pxp) if (!gt_supports_teelink_via_mei(gt)) return -ENODEV; - mei_tee_init_hooks(pxp); + intel_pxp_init_mei_tee_hooks(pxp); if (pxp->tee_link.init) ret = pxp->tee_link.init(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h index 4c1d38fa314a..6c09fa11bcca 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -6,17 +6,19 @@ #ifndef __INTEL_PXP_TEE_H__ #define __INTEL_PXP_TEE_H__ -#include "intel_pxp.h" +#include "linux/types.h" -int intel_pxp_teelink_send_message(struct intel_pxp *pxp, - void *msg_in, size_t msg_in_size, - void *msg_out, size_t msg_out_size, - size_t *msg_out_max_size); +struct intel_pxp; + +int intel_pxp_teelink_init(struct intel_pxp *pxp); +void intel_pxp_teelink_fini(struct intel_pxp *pxp); int intel_pxp_teelink_create_session(struct intel_pxp *pxp, int arb_session_id); -int intel_pxp_teelink_init(struct intel_pxp *pxp); -void intel_pxp_teelink_fini(struct intel_pxp *pxp); +int intel_pxp_teelink_send_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_size, + size_t *msg_out_max_size); #endif /* __INTEL_PXP_TEE_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c new file mode 100644 index 000000000000..cd54219ced06 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include + +#include +#include + +#include "gem/i915_gem_lmem.h" + +#include "i915_drv.h" +#include "intel_pxp.h" +#include "intel_pxp_cmd_interface_42.h" +#include "intel_pxp_huc.h" +#include "intel_pxp_session.h" +#include "intel_pxp_tee_mei.h" + +static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + + if (!gt) + return NULL; + + return >->pxp; +} + +static int mei_tee_io_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_max_size, + size_t *msg_out_size) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct i915_pxp_component *pxp_component = pxp->pxp_component; + int ret = 0; + + mutex_lock(&pxp->tee_mutex); + + /* + * The binding of the component is asynchronous from i915 probe, so we + * can't be sure it has happened. + */ + if (!pxp_component) { + ret = -ENODEV; + goto unlock; + } + + ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in, msg_in_size); + if (ret) { + drm_err(&i915->drm, "Failed to send PXP TEE message\n"); + goto unlock; + } + + ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out, msg_out_max_size); + if (ret < 0) { + drm_err(&i915->drm, "Failed to receive PXP TEE message\n"); + goto unlock; + } + + if (ret > msg_out_max_size) { + drm_err(&i915->drm, + "Failed to receive PXP TEE message due to unexpected output size\n"); + ret = -ENOSPC; + goto unlock; + } + + if (msg_out_size) + *msg_out_size = ret; + + ret = 0; +unlock: + mutex_unlock(&pxp->tee_mutex); + return ret; +} + +static int mei_tee_gsc_stream_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_max_size, + size_t *msg_out_size) +{ + /* TODO: for bigger objects we need to use a sg of 4k pages */ + const size_t max_msg_size = PAGE_SIZE; + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct i915_pxp_component *pxp_component = pxp->pxp_component; + unsigned int offset = 0; + struct scatterlist *sg; + int ret; + + if (msg_in_size > max_msg_size || msg_out_max_size > max_msg_size) + return -ENOSPC; + + mutex_lock(&pxp->tee_mutex); + + if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) { + ret = -ENODEV; + goto unlock; + } + + GEM_BUG_ON(!pxp->stream_cmd.obj); + + sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, &offset); + + memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_size); + + ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, 0, 0, + sg, msg_in_size, sg); + if (ret < 0) + drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); + else + memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_max_size); + +unlock: + mutex_unlock(&pxp->tee_mutex); + return ret; +} + +/** + * i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee + * @i915_kdev: pointer to i915 kernel device + * @tee_kdev: pointer to tee kernel device + * @data: pointer to pxp_tee_master containing the function pointers + * + * This bind function is called during the system boot or resume from system sleep. + * + * Return: return 0 if successful. + */ +static int i915_pxp_tee_component_bind(struct device *i915_kdev, + struct device *tee_kdev, void *data) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); + struct intel_uc *uc; + intel_wakeref_t wakeref; + int ret = 0; + + if (!pxp) { + drm_warn(&i915->drm, "tee comp binding without a PXP-owner GT\n"); + return -ENODEV; + } + uc = &pxp_to_gt(pxp)->uc; + + mutex_lock(&pxp->tee_mutex); + pxp->pxp_component = data; + pxp->pxp_component->tee_dev = tee_kdev; + mutex_unlock(&pxp->tee_mutex); + + if (intel_uc_uses_huc(uc) && intel_huc_is_loaded_by_gsc(&uc->huc)) { + with_intel_runtime_pm(&i915->runtime_pm, wakeref) { + /* load huc via pxp */ + ret = intel_huc_fw_load_and_auth_via_gsc(&uc->huc); + if (ret < 0) + drm_err(&i915->drm, "failed to load huc via gsc %d\n", ret); + } + } + + /* if we are suspended, the HW will be re-initialized on resume */ + wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm); + if (!wakeref) + return 0; + + /* the component is required to fully start the PXP HW */ + if (intel_pxp_is_enabled_on_gt(pxp)) + intel_pxp_init_hw(pxp); + + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + + return ret; +} + +static void i915_pxp_tee_component_unbind(struct device *i915_kdev, + struct device *tee_kdev, void *data) +{ + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); + intel_wakeref_t wakeref; + + if (intel_pxp_is_enabled_on_gt(pxp)) + with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) + intel_pxp_fini_hw(pxp); + + mutex_lock(&pxp->tee_mutex); + pxp->pxp_component = NULL; + mutex_unlock(&pxp->tee_mutex); +} + +static const struct component_ops i915_pxp_tee_component_ops = { + .bind = i915_pxp_tee_component_bind, + .unbind = i915_pxp_tee_component_unbind, +}; + +static int alloc_streaming_command(struct intel_pxp *pxp) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct drm_i915_gem_object *obj = NULL; + void *cmd; + int err; + + pxp->stream_cmd.obj = NULL; + pxp->stream_cmd.vaddr = NULL; + + if (!IS_DGFX(i915)) + return 0; + + /* allocate lmem object of one page for PXP command memory and store it */ + obj = i915_gem_object_create_lmem(i915, PAGE_SIZE, I915_BO_ALLOC_CONTIGUOUS); + if (IS_ERR(obj)) { + drm_err(&i915->drm, "Failed to allocate pxp streaming command!\n"); + return PTR_ERR(obj); + } + + err = i915_gem_object_pin_pages_unlocked(obj); + if (err) { + drm_err(&i915->drm, "Failed to pin gsc message page!\n"); + goto out_put; + } + + /* map the lmem into the virtual memory pointer */ + cmd = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(i915, obj, true)); + if (IS_ERR(cmd)) { + drm_err(&i915->drm, "Failed to map gsc message page!\n"); + err = PTR_ERR(cmd); + goto out_unpin; + } + + memset(cmd, 0, obj->base.size); + + pxp->stream_cmd.obj = obj; + pxp->stream_cmd.vaddr = cmd; + + return 0; + +out_unpin: + i915_gem_object_unpin_pages(obj); +out_put: + i915_gem_object_put(obj); + return err; +} + +static void free_streaming_command(struct intel_pxp *pxp) +{ + struct drm_i915_gem_object *obj = fetch_and_zero(&pxp->stream_cmd.obj); + + if (!obj) + return; + + i915_gem_object_unpin_map(obj); + i915_gem_object_unpin_pages(obj); + i915_gem_object_put(obj); +} + +static int mei_tee_component_init(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = pxp_to_gt(pxp); + struct drm_i915_private *i915 = gt->i915; + + mutex_init(&pxp->tee_mutex); + + ret = alloc_streaming_command(pxp); + if (ret) + return ret; + + ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops, + I915_COMPONENT_PXP); + if (ret < 0) { + drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret); + goto out_free; + } + + pxp->pxp_component_added = true; + + return 0; + +out_free: + free_streaming_command(pxp); + return ret; +} + +static void mei_tee_component_fini(struct intel_pxp *pxp) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + + if (!pxp->pxp_component_added) + return; + + component_del(i915->drm.dev, &i915_pxp_tee_component_ops); + pxp->pxp_component_added = false; + + free_streaming_command(pxp); +} + +static int mei_tee_create_session(struct intel_pxp *pxp, + int session_id) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct pxp42_create_arb_in msg_in = {0}; + struct pxp42_create_arb_out msg_out = {0}; + int ret; + + msg_in.header.api_version = PXP_APIVER(4, 2); + msg_in.header.command_id = PXP42_CMDID_INIT_SESSION; + msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); + msg_in.protection_mode = PXP42_ARB_SESSION_MODE_HEAVY; + msg_in.session_id = session_id; + + ret = mei_tee_io_message(pxp, + &msg_in, sizeof(msg_in), + &msg_out, sizeof(msg_out), + NULL); + + if (ret) + drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret); + else if (msg_out.header.status != 0x0) + drm_warn(&i915->drm, "PXP firmware failed arb session init request ret=[0x%08x]\n", + msg_out.header.status); + + return ret; +} + +void intel_pxp_init_mei_tee_hooks(struct intel_pxp *pxp) +{ + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + + pxp->tee_link.init = mei_tee_component_init; + pxp->tee_link.fini = mei_tee_component_fini; + pxp->tee_link.create_session = mei_tee_create_session; + if (IS_DG2(i915)) + pxp->tee_link.send_message = mei_tee_gsc_stream_message; + else + pxp->tee_link.send_message = mei_tee_io_message; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h new file mode 100644 index 000000000000..e8d85ee5c698 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_TEE_MEI_H__ +#define __INTEL_PXP_TEE_MEI_H__ + +struct intel_pxp; + +void intel_pxp_init_mei_tee_hooks(struct intel_pxp *pxp); + +#endif /* __INTEL_PXP_TEE_MEI_H__ */ From patchwork Wed Nov 23 22:34:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D437FC433FE for ; Wed, 23 Nov 2022 22:32:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A093610E653; Wed, 23 Nov 2022 22:31:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id EC9F210E655 for ; Wed, 23 Nov 2022 22:31:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669242701; x=1700778701; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ewL94pPjF2En/3MY8fUOIpCj2aEWeCM2hlBMSYYtcQg=; b=bXpCaDNxY5nmeuadUzFIRdDYm4Icvv7MqPJueO4GWssCzGHE2JkSeZgn ojpMwXt9ZEZ8u1J7aHsBGGwwHNUFXiWreUOLOo6ctrAcOuewT4LnyxbyU 1qZA+O7pA+I/lyHjCX8H0SVU3cUfyLapfFlgsflxK/PJVCnOL0syhqv2h hEK07BRp7/jc3bchcI2JTYJjOQc4hB2cAj2Y4OCyo2BD89l4DI6hZN2wU 9xW3B7WILVHuh/duyG830+xUtmW9f/FfLQD0vEQr2aKgyZJ5tvl7ZN79M 1Ekh1vWmJPkZBsgHXKhOE3iSsTN73XAi0EBRMMSXWUF3WKF9qZZm/jhag w==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="293875381" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="293875381" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 14:31:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="784404455" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404455" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:08 -0800 Message-Id: <20221123223410.2846296-6-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 5/7] drm/i915/pxp: move mei-pxp and mei-gsc resources to be backend-private X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" drm/i915/pxp: move mei-pxp and mei-gsc resources to be backend-private Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 +- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 3 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 2 + drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c | 143 +++++++++++++------ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 ++--- 7 files changed, 132 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 33f86bb05148..49105bb1d694 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -230,18 +230,6 @@ static void pxp_queue_termination(struct intel_pxp *pxp) spin_unlock_irq(gt->irq_lock); } -static bool pxp_component_bound(struct intel_pxp *pxp) -{ - bool bound = false; - - mutex_lock(&pxp->tee_mutex); - if (pxp->pxp_component) - bound = true; - mutex_unlock(&pxp->tee_mutex); - - return bound; -} - /* * the arb session is restarted from the irq work when we receive the * termination completion interrupt @@ -260,7 +248,7 @@ int intel_pxp_start(struct drm_i915_private *i915) if (!intel_pxp_is_enabled_on_gt(pxp)) return -ENODEV; - if (wait_for(pxp_component_bound(pxp), 250)) + if (wait_for(intel_pxp_teelink_is_ready(pxp), 250)) return -ENXIO; mutex_lock(&pxp->arb_mutex); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c index 043344dbf566..69ee261a1f7e 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c @@ -11,10 +11,10 @@ #include "gt/intel_gt.h" #include "intel_pxp.h" +#include "intel_pxp_cmd_interface_43.h" #include "intel_pxp_huc.h" #include "intel_pxp_tee.h" #include "intel_pxp_types.h" -#include "intel_pxp_cmd_interface_43.h" int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp) { @@ -25,7 +25,7 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp) dma_addr_t huc_phys_addr; int err; - if (!pxp->pxp_component) + if (!intel_pxp_teelink_is_ready(pxp)) return -ENODEV; huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 19ac8828cbde..dc907a338fdb 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -7,6 +7,7 @@ #include "intel_pxp_irq.h" #include "intel_pxp_pm.h" #include "intel_pxp_session.h" +#include "intel_pxp_tee.h" #include "i915_drv.h" void intel_pxp_suspend_prepare(struct intel_pxp *pxp) @@ -42,7 +43,7 @@ void intel_pxp_resume(struct intel_pxp *pxp) * re-bound after we come out, so in that scenario we can defer the * hw init to the bind call. */ - if (!pxp->pxp_component) + if (!intel_pxp_teelink_is_ready(pxp)) return; intel_pxp_init_hw(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 034e2eee5075..1171f339643c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -43,6 +43,14 @@ int intel_pxp_teelink_send_message(struct intel_pxp *pxp, msg_out_max_size); } +bool intel_pxp_teelink_is_ready(struct intel_pxp *pxp) +{ + if (pxp->tee_link.is_ready) + return pxp->tee_link.is_ready(pxp); + + return false; +} + static bool gt_supports_teelink_via_mei(struct intel_gt *gt) { return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0)); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h index 6c09fa11bcca..46852f164e36 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h @@ -13,6 +13,8 @@ struct intel_pxp; int intel_pxp_teelink_init(struct intel_pxp *pxp); void intel_pxp_teelink_fini(struct intel_pxp *pxp); +bool intel_pxp_teelink_is_ready(struct intel_pxp *pxp); + int intel_pxp_teelink_create_session(struct intel_pxp *pxp, int arb_session_id); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c index cd54219ced06..a81e8859335e 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c @@ -17,6 +17,34 @@ #include "intel_pxp_session.h" #include "intel_pxp_tee_mei.h" +struct mei_teelink_priv { + /** + * @pxp_component: i915_pxp_component struct of the bound mei_pxp + * module. Only set and cleared inside component bind/unbind functions, + * which are protected by &tee_mutex. + */ + struct i915_pxp_component *pxp_component; + /** + * @pxp_component_added: track if the pxp component has been added. + * Set and cleared in tee init and fini functions respectively. + */ + bool pxp_component_added; + + /** @tee_mutex: protects the tee channel binding and messaging. */ + struct mutex tee_mutex; + + /** @stream_cmd: LMEM obj used to send stream PXP commands to the GSC */ + struct { + struct drm_i915_gem_object *obj; /* contains PXP command memory */ + void *vaddr; /* virtual memory for PXP command */ + } stream_cmd; +}; + +static inline struct mei_teelink_priv *pxp_to_mei_priv(struct intel_pxp *pxp) +{ + return (struct mei_teelink_priv *)pxp->tee_link.priv; +} + static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); @@ -34,10 +62,11 @@ static int mei_tee_io_message(struct intel_pxp *pxp, size_t *msg_out_size) { struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - struct i915_pxp_component *pxp_component = pxp->pxp_component; + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); + struct i915_pxp_component *pxp_component = mei->pxp_component; int ret = 0; - mutex_lock(&pxp->tee_mutex); + mutex_lock(&mei->tee_mutex); /* * The binding of the component is asynchronous from i915 probe, so we @@ -72,7 +101,7 @@ static int mei_tee_io_message(struct intel_pxp *pxp, ret = 0; unlock: - mutex_unlock(&pxp->tee_mutex); + mutex_unlock(&mei->tee_mutex); return ret; } @@ -84,7 +113,8 @@ static int mei_tee_gsc_stream_message(struct intel_pxp *pxp, /* TODO: for bigger objects we need to use a sg of 4k pages */ const size_t max_msg_size = PAGE_SIZE; struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; - struct i915_pxp_component *pxp_component = pxp->pxp_component; + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); + struct i915_pxp_component *pxp_component = mei->pxp_component; unsigned int offset = 0; struct scatterlist *sg; int ret; @@ -92,28 +122,28 @@ static int mei_tee_gsc_stream_message(struct intel_pxp *pxp, if (msg_in_size > max_msg_size || msg_out_max_size > max_msg_size) return -ENOSPC; - mutex_lock(&pxp->tee_mutex); + mutex_lock(&mei->tee_mutex); if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) { ret = -ENODEV; goto unlock; } - GEM_BUG_ON(!pxp->stream_cmd.obj); + GEM_BUG_ON(!mei->stream_cmd.obj); - sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, &offset); + sg = i915_gem_object_get_sg_dma(mei->stream_cmd.obj, 0, &offset); - memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_size); + memcpy(mei->stream_cmd.vaddr, msg_in, msg_in_size); ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, 0, 0, sg, msg_in_size, sg); if (ret < 0) drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); else - memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_max_size); + memcpy(msg_out, mei->stream_cmd.vaddr, msg_out_max_size); unlock: - mutex_unlock(&pxp->tee_mutex); + mutex_unlock(&mei->tee_mutex); return ret; } @@ -127,11 +157,12 @@ static int mei_tee_gsc_stream_message(struct intel_pxp *pxp, * * Return: return 0 if successful. */ -static int i915_pxp_tee_component_bind(struct device *i915_kdev, +static int i915_mei_tee_component_bind(struct device *i915_kdev, struct device *tee_kdev, void *data) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); struct intel_uc *uc; intel_wakeref_t wakeref; int ret = 0; @@ -142,10 +173,10 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, } uc = &pxp_to_gt(pxp)->uc; - mutex_lock(&pxp->tee_mutex); - pxp->pxp_component = data; - pxp->pxp_component->tee_dev = tee_kdev; - mutex_unlock(&pxp->tee_mutex); + mutex_lock(&mei->tee_mutex); + mei->pxp_component = data; + mei->pxp_component->tee_dev = tee_kdev; + mutex_unlock(&mei->tee_mutex); if (intel_uc_uses_huc(uc) && intel_huc_is_loaded_by_gsc(&uc->huc)) { with_intel_runtime_pm(&i915->runtime_pm, wakeref) { @@ -170,36 +201,38 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, return ret; } -static void i915_pxp_tee_component_unbind(struct device *i915_kdev, +static void i915_mei_tee_component_unbind(struct device *i915_kdev, struct device *tee_kdev, void *data) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); intel_wakeref_t wakeref; if (intel_pxp_is_enabled_on_gt(pxp)) with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) intel_pxp_fini_hw(pxp); - mutex_lock(&pxp->tee_mutex); - pxp->pxp_component = NULL; - mutex_unlock(&pxp->tee_mutex); + mutex_lock(&mei->tee_mutex); + mei->pxp_component = NULL; + mutex_unlock(&mei->tee_mutex); } -static const struct component_ops i915_pxp_tee_component_ops = { - .bind = i915_pxp_tee_component_bind, - .unbind = i915_pxp_tee_component_unbind, +static const struct component_ops i915_mei_tee_component_ops = { + .bind = i915_mei_tee_component_bind, + .unbind = i915_mei_tee_component_unbind, }; -static int alloc_streaming_command(struct intel_pxp *pxp) +static int mei_tee_alloc_streaming_command(struct intel_pxp *pxp) { struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); struct drm_i915_gem_object *obj = NULL; void *cmd; int err; - pxp->stream_cmd.obj = NULL; - pxp->stream_cmd.vaddr = NULL; + mei->stream_cmd.obj = NULL; + mei->stream_cmd.vaddr = NULL; if (!IS_DGFX(i915)) return 0; @@ -227,8 +260,8 @@ static int alloc_streaming_command(struct intel_pxp *pxp) memset(cmd, 0, obj->base.size); - pxp->stream_cmd.obj = obj; - pxp->stream_cmd.vaddr = cmd; + mei->stream_cmd.obj = obj; + mei->stream_cmd.vaddr = cmd; return 0; @@ -239,9 +272,9 @@ static int alloc_streaming_command(struct intel_pxp *pxp) return err; } -static void free_streaming_command(struct intel_pxp *pxp) +static void mei_tee_free_streaming_command(struct intel_pxp *pxp) { - struct drm_i915_gem_object *obj = fetch_and_zero(&pxp->stream_cmd.obj); + struct drm_i915_gem_object *obj = fetch_and_zero(&pxp_to_mei_priv(pxp)->stream_cmd.obj); if (!obj) return; @@ -251,45 +284,74 @@ static void free_streaming_command(struct intel_pxp *pxp) i915_gem_object_put(obj); } +static bool mei_tee_is_component_bound(struct intel_pxp *pxp) +{ + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); + bool bound = false; + + mutex_lock(&mei->tee_mutex); + if (mei->pxp_component) + bound = true; + mutex_unlock(&mei->tee_mutex); + + return bound; +} + static int mei_tee_component_init(struct intel_pxp *pxp) { int ret; struct intel_gt *gt = pxp_to_gt(pxp); struct drm_i915_private *i915 = gt->i915; + struct mei_teelink_priv *mei; + + mei = kzalloc(sizeof(*mei), GFP_KERNEL); + if (!mei) + return -ENOMEM; - mutex_init(&pxp->tee_mutex); + pxp->tee_link.priv = mei; - ret = alloc_streaming_command(pxp); + mutex_init(&mei->tee_mutex); + + ret = mei_tee_alloc_streaming_command(pxp); if (ret) - return ret; + goto out_free; - ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops, + ret = component_add_typed(i915->drm.dev, &i915_mei_tee_component_ops, I915_COMPONENT_PXP); if (ret < 0) { drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret); - goto out_free; + goto out_free_stream; } - pxp->pxp_component_added = true; + mei->pxp_component_added = true; return 0; +out_free_stream: + mei_tee_free_streaming_command(pxp); out_free: - free_streaming_command(pxp); + kfree(mei); + pxp->tee_link.priv = NULL; return ret; } static void mei_tee_component_fini(struct intel_pxp *pxp) { struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915; + struct mei_teelink_priv *mei = pxp_to_mei_priv(pxp); + + if (!mei) + return; - if (!pxp->pxp_component_added) + if (!mei->pxp_component_added) return; - component_del(i915->drm.dev, &i915_pxp_tee_component_ops); - pxp->pxp_component_added = false; + component_del(i915->drm.dev, &i915_mei_tee_component_ops); + mei->pxp_component_added = false; - free_streaming_command(pxp); + mei_tee_free_streaming_command(pxp); + kfree(mei); + pxp->tee_link.priv = NULL; } static int mei_tee_create_session(struct intel_pxp *pxp, @@ -326,6 +388,7 @@ void intel_pxp_init_mei_tee_hooks(struct intel_pxp *pxp) pxp->tee_link.init = mei_tee_component_init; pxp->tee_link.fini = mei_tee_component_fini; + pxp->tee_link.is_ready = mei_tee_is_component_bound; pxp->tee_link.create_session = mei_tee_create_session; if (IS_DG2(i915)) pxp->tee_link.send_message = mei_tee_gsc_stream_message; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index 6de79a46ceed..f1bddf8500d4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -18,17 +18,6 @@ struct i915_pxp_component; * struct intel_pxp - pxp state */ struct intel_pxp { - /** - * @pxp_component: i915_pxp_component struct of the bound mei_pxp - * module. Only set and cleared inside component bind/unbind functions, - * which are protected by &tee_mutex. - */ - struct i915_pxp_component *pxp_component; - /** - * @pxp_component_added: track if the pxp component has been added. - * Set and cleared in tee init and fini functions respectively. - */ - bool pxp_component_added; /** @ce: kernel-owned context used for PXP operations */ struct intel_context *ce; @@ -50,15 +39,6 @@ struct intel_pxp { */ u32 key_instance; - /** @tee_mutex: protects the tee channel binding and messaging. */ - struct mutex tee_mutex; - - /** @stream_cmd: LMEM obj used to send stream PXP commands to the GSC */ - struct { - struct drm_i915_gem_object *obj; /* contains PXP command memory */ - void *vaddr; /* virtual memory for PXP command */ - } stream_cmd; - /** * @hw_state_invalidated: if the HW perceives an attack on the integrity * of the encryption it will invalidate the keys and expect SW to @@ -88,16 +68,26 @@ struct intel_pxp { * These hooks will point to device specific implementations. */ struct { - /* Called to initialize the backend transport resources.*/ + /** @priv: Pointer exclusively for backend layer to store private context.*/ + void *priv; + + /** @init: Func-ptr called to initialize the backend transport resources.*/ int (*init)(struct intel_pxp *pxp); - /* Called to free the backend transport resources.*/ + /** @fini: Func-ptr called to free the backend transport resources.*/ void (*fini)(struct intel_pxp *pxp); - /* Called to create a pxp session.*/ + /** + * @is_ready: Func-ptr called to query if the backend transport is available + * for use. Depending on the backend, some, such as mei, have asyncronous workers + * or callbacks that setup the backend tee link to the security firmware. + **/ + bool (*is_ready)(struct intel_pxp *pxp); + + /** @init: Func-ptr called to create a pxp session.*/ int (*create_session)(struct intel_pxp *pxp, int session_id); - /* Called to send message packets to pxp firmware.*/ + /** @init: Func-ptr called to send message packets to pxp firmware.*/ int (*send_message)(struct intel_pxp *pxp, void *msg_in, size_t msg_in_len, void *msg_out, size_t msg_out_max_len, From patchwork Wed Nov 23 22:34:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0FC0C4332F for ; Wed, 23 Nov 2022 22:32:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B6DA910E654; Wed, 23 Nov 2022 22:31:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1421910E656 for ; Wed, 23 Nov 2022 22:31:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669242702; x=1700778702; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=J9HgDGD5IJxkimgaBXJuBD7w0at5GVRhjOLzOUBv8TQ=; b=XySchc1XkUhtYKUeTFQMDJcMkJu/vJ9eYlHIqRWDePBLGHdMXXvJyvwr IRAIF4tfJrkeCK/DOD5X+5GvRxOp/tUIsXiywoinFn5oNWAHcvXaOhjyV B/uasz0iboCkBnaaAsm4IsRORwFJ8bEn+3/VWsJMVRSRayNTL/B35TjYx KXowkcW3Ypa/wWphYSN1sKcStajjfROf5+PyT2fEiLpsQa7nVlQq8KRvE vKOgegOgEpxMoZDsAipAw+I4e3RtyMXcvD7Oqe4Ep6OfHGlaG0kjJQlpI ES4N8f5gQ3LwjNEOfTSbQdZnq7Ct2VU8NN1JWGfEHA4DPstvqbA9e8UNT Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="293875383" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="293875383" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 14:31:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="784404457" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404457" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:09 -0800 Message-Id: <20221123223410.2846296-7-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 6/7] drm/i915/pxp: Add PXP gsccs tee-link backend stubs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add PXP gsccs tee-link backend using empty stubs for now. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 46 ++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h | 13 ++++++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 +++++-- 4 files changed, 72 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 6ed45d9145e8..05072d7a4ba4 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -320,7 +320,8 @@ i915-y += \ pxp/intel_pxp.o \ pxp/intel_pxp_tee.o \ pxp/intel_pxp_tee_mei.o \ - pxp/intel_pxp_huc.o + pxp/intel_pxp_huc.o \ + pxp/intel_pxp_gsccs.o i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp_cmd.o \ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c new file mode 100644 index 000000000000..a4243272ca73 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2022 Intel Corporation. + */ + +#include "i915_drv.h" +#include "intel_pxp.h" +#include "intel_pxp_gsccs.h" + +static int gsccs_tee_send_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_size_max, + size_t *msg_out_len) +{ + return -ENODEV; +} + +static int +gsccs_tee_create_session(struct intel_pxp *pxp, + int session_id) +{ + return -ENODEV; +} + +static bool gsccs_tee_is_ready(struct intel_pxp *pxp) +{ + return false; +} + +static void gsccs_tee_fini(struct intel_pxp *pxp) +{ +} + +static int gsccs_tee_init(struct intel_pxp *pxp) +{ + return -ENODEV; +} + +void intel_pxp_init_gsccs_tee_hooks(struct intel_pxp *pxp) +{ + pxp->tee_link.init = gsccs_tee_init; + pxp->tee_link.fini = gsccs_tee_fini; + pxp->tee_link.is_ready = gsccs_tee_is_ready; + pxp->tee_link.create_session = gsccs_tee_create_session; + pxp->tee_link.send_message = gsccs_tee_send_message; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h new file mode 100644 index 000000000000..5fb9f2c042ff --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2022, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_TEE_GSCCS_H__ +#define __INTEL_PXP_TEE_GSCCS_H__ + +struct intel_pxp; + +void intel_pxp_init_gsccs_tee_hooks(struct intel_pxp *pxp); + +#endif /* __INTEL_PXP_TEE_GSCCS_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 1171f339643c..a4b7f6c7bc54 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "intel_pxp.h" +#include "intel_pxp_gsccs.h" #include "intel_pxp_tee.h" #include "intel_pxp_tee_mei.h" @@ -51,6 +52,11 @@ bool intel_pxp_teelink_is_ready(struct intel_pxp *pxp) return false; } +static bool gt_supports_teelink_via_gsccs(struct intel_gt *gt) +{ + return (HAS_ENGINE(gt, GSC0)); +} + static bool gt_supports_teelink_via_mei(struct intel_gt *gt) { return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && !HAS_ENGINE(gt, GSC0)); @@ -61,11 +67,13 @@ int intel_pxp_teelink_init(struct intel_pxp *pxp) struct intel_gt *gt = pxp_to_gt(pxp); int ret = -ENOLINK; - if (!gt_supports_teelink_via_mei(gt)) + if (gt_supports_teelink_via_mei(gt)) + intel_pxp_init_mei_tee_hooks(pxp); + else if (gt_supports_teelink_via_gsccs(gt)) + intel_pxp_init_gsccs_tee_hooks(pxp); + else return -ENODEV; - intel_pxp_init_mei_tee_hooks(pxp); - if (pxp->tee_link.init) ret = pxp->tee_link.init(pxp); if (ret) From patchwork Wed Nov 23 22:34:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13054392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B595C4167D for ; Wed, 23 Nov 2022 22:32:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C498810E65A; Wed, 23 Nov 2022 22:32:08 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E64810E657 for ; Wed, 23 Nov 2022 22:31:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669242702; x=1700778702; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=U5lJU8Z//Sjn02x8bMXZjzskufQCokCwaRBb1EE/Lvc=; b=OkCHuP2BefrQqFSp3eOzwUBD7L0dWJYKYPa1X7JYU4yGO+r7tguThjjJ Mp8i1es3QK+LuD6RQuKITeN1jxNqlCEB9nBBNjY/dVwIFPK1sqccL5Ced 8QFHYG82DP1bXbACPH/avTNVbuz7Z+6oo/KpO0rRCeVFnWsAkN0O3pIEq hHf2gyRalDfQ3aFFoKODFjBPSIXJB0YnaDzbtfi0ekNdHZZtolbxG21wR GdjzGTufnKnVdcFgLzulOKBwLFQOHatEtsJJBj9cJZmg1BjPasCKQ4oCy IcCL3dGGcjKLJf13KiDZi9neTe88E2GuB/ArHW/AnvE/tVRspvJu5tY0C w==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="293875384" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="293875384" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 14:31:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="784404458" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="784404458" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga001.fm.intel.com with ESMTP; 23 Nov 2022 14:31:40 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2022 14:34:10 -0800 Message-Id: <20221123223410.2846296-8-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> References: <20221123223410.2846296-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 7/7] drm/i915/pxp: Better hierarchy readibility - move backends to a backend folder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the mei and gsccs backend implementation files into a backend folder This would provide clearer readibility of file hiearchy with regards to this backend vs front end thus encouraging better code location selcection for future changes. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/Makefile | 6 +++--- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 ++-- .../drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.c | 6 ++++-- .../drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.h | 0 .../i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.c | 11 ++++++----- .../i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.h | 0 6 files changed, 15 insertions(+), 12 deletions(-) rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.c (92%) rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_gsccs.h (100%) rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.c (98%) rename drivers/gpu/drm/i915/pxp/{ => tee_backends}/intel_pxp_tee_mei.h (100%) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 05072d7a4ba4..10e252192b3f 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -318,10 +318,10 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support. Base support is required for HuC i915-y += \ pxp/intel_pxp.o \ - pxp/intel_pxp_tee.o \ - pxp/intel_pxp_tee_mei.o \ pxp/intel_pxp_huc.o \ - pxp/intel_pxp_gsccs.o + pxp/intel_pxp_tee.o \ + pxp/tee_backends/intel_pxp_tee_mei.o \ + pxp/tee_backends/intel_pxp_gsccs.o i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp_cmd.o \ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index a4b7f6c7bc54..9b6e48929e6c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -5,9 +5,9 @@ #include "i915_drv.h" #include "intel_pxp.h" -#include "intel_pxp_gsccs.h" #include "intel_pxp_tee.h" -#include "intel_pxp_tee_mei.h" +#include "tee_backends/intel_pxp_gsccs.h" +#include "tee_backends/intel_pxp_tee_mei.h" int intel_pxp_teelink_create_session(struct intel_pxp *pxp, int arb_session_id) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c similarity index 92% rename from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c index a4243272ca73..6441018f5207 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +++ b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.c @@ -4,8 +4,10 @@ */ #include "i915_drv.h" -#include "intel_pxp.h" -#include "intel_pxp_gsccs.h" + +#include "pxp/intel_pxp.h" + +#include "pxp/tee_backends/intel_pxp_gsccs.h" static int gsccs_tee_send_message(struct intel_pxp *pxp, void *msg_in, size_t msg_in_size, diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.h similarity index 100% rename from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_gsccs.h diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c similarity index 98% rename from drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c index a81e8859335e..881fc93b1cb0 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.c +++ b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.c @@ -11,11 +11,12 @@ #include "gem/i915_gem_lmem.h" #include "i915_drv.h" -#include "intel_pxp.h" -#include "intel_pxp_cmd_interface_42.h" -#include "intel_pxp_huc.h" -#include "intel_pxp_session.h" -#include "intel_pxp_tee_mei.h" + +#include "pxp/intel_pxp.h" +#include "pxp/intel_pxp_cmd_interface_42.h" +#include "pxp/intel_pxp_huc.h" +#include "pxp/intel_pxp_session.h" +#include "pxp/tee_backends/intel_pxp_tee_mei.h" struct mei_teelink_priv { /** diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h b/drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.h similarity index 100% rename from drivers/gpu/drm/i915/pxp/intel_pxp_tee_mei.h rename to drivers/gpu/drm/i915/pxp/tee_backends/intel_pxp_tee_mei.h