From patchwork Thu Nov 24 08:12:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13054677 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15BFFC4332F for ; Thu, 24 Nov 2022 08:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230012AbiKXIOS (ORCPT ); Thu, 24 Nov 2022 03:14:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229716AbiKXINQ (ORCPT ); Thu, 24 Nov 2022 03:13:16 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4509B28E3B; Thu, 24 Nov 2022 00:12:54 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8Cadh130275; Thu, 24 Nov 2022 02:12:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669277556; bh=THaNyo3HhYLvjcOyg5mmXhOiGWwB/c47R2AQOF2zeU8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rAICvLjqKFwDLHHRGoaCPr0oJ97AoqMEeIyD4sFkqaulzh0pslkKfB5TbO/rAUW57 LBCt3Pz0T6hKyTgZeHtDwq7Vc1i3dEISjCCc403Fez9kpKAZjZL2M2is2/kZak7ar+ eXZJVgmZ8stGnrUIHg3P9dpv8nAuWShrYq+34D3U= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AO8CaZn064024 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Nov 2022 02:12:36 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 24 Nov 2022 02:12:36 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 24 Nov 2022 02:12:35 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8CWih009876; Thu, 24 Nov 2022 02:12:34 -0600 From: Matt Ranostay To: , , , , , , , , , , CC: , , , , Matt Ranostay Subject: [PATCH v7 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Date: Thu, 24 Nov 2022 00:12:17 -0800 Message-ID: <20221124081221.1206167-2-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221124081221.1206167-1-mranostay@ti.com> References: <20221124081221.1206167-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add num-lanes schema checks based on compatible string on available lanes for that platform. Signed-off-by: Matt Ranostay --- .../bindings/pci/ti,j721e-pci-ep.yaml | 28 +++++++++++++++++-- .../bindings/pci/ti,j721e-pci-host.yaml | 28 +++++++++++++++++-- 2 files changed, 50 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 10e6eabdff53..1aeea168d3d0 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -10,9 +10,6 @@ title: TI J721E PCI EP (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I -allOf: - - $ref: "cdns-pcie-ep.yaml#" - properties: compatible: oneOf: @@ -65,6 +62,31 @@ properties: items: - const: link_state +allOf: + - $ref: "cdns-pcie-ep.yaml#" + - if: + properties: + compatible: + enum: + - ti,am64-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-ep + - ti,j721e-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index b0513b197d08..8eca0d08303f 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -10,9 +10,6 @@ title: TI J721E PCI Host (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I -allOf: - - $ref: "cdns-pcie-host.yaml#" - properties: compatible: oneOf: @@ -98,6 +95,31 @@ properties: interrupts: maxItems: 1 +allOf: + - $ref: "cdns-pcie-host.yaml#" + - if: + properties: + compatible: + enum: + - ti,am64-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-host + - ti,j721e-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + required: - compatible - reg From patchwork Thu Nov 24 08:12:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13054680 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 619B2C47088 for ; Thu, 24 Nov 2022 08:14:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229949AbiKXIOX (ORCPT ); Thu, 24 Nov 2022 03:14:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229954AbiKXINj (ORCPT ); Thu, 24 Nov 2022 03:13:39 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 079D013E05; Thu, 24 Nov 2022 00:13:01 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8CfWu048765; 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Thu, 24 Nov 2022 02:12:41 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8CcRc022226; Thu, 24 Nov 2022 02:12:40 -0600 From: Matt Ranostay To: , , , , , , , , , , CC: , , , , Matt Ranostay Subject: [PATCH v7 2/5] PCI: j721e: Add per platform maximum lane settings Date: Thu, 24 Nov 2022 00:12:18 -0800 Message-ID: <20221124081221.1206167-3-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221124081221.1206167-1-mranostay@ti.com> References: <20221124081221.1206167-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Various platforms have different maximum amount of lanes that can be selected. Add max_lanes to struct j721e_pcie to allow for detection of this which is needed to calculate the needed bitmask size for the possible lane count. Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra --- drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index cc83a8925ce0..8990f58d64d5 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -47,8 +47,6 @@ enum link_status { #define GENERATION_SEL_MASK GENMASK(1, 0) -#define MAX_LANES 2 - struct j721e_pcie { struct cdns_pcie *cdns_pcie; struct clk *refclk; @@ -71,6 +69,7 @@ struct j721e_pcie_data { unsigned int quirk_disable_flr:1; u32 linkdown_irq_regfield; unsigned int byte_access_allowed:1; + unsigned int max_lanes; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = { .quirk_retrain_flag = true, .byte_access_allowed = false, .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 2, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { .mode = PCI_MODE_EP, .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 2, }; static const struct j721e_pcie_data j7200_pcie_rc_data = { @@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = { .quirk_detect_quiet_flag = true, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .max_lanes = 2, }; static const struct j721e_pcie_data j7200_pcie_ep_data = { .mode = PCI_MODE_EP, .quirk_detect_quiet_flag = true, .quirk_disable_flr = true, + .max_lanes = 2, }; static const struct j721e_pcie_data am64_pcie_rc_data = { .mode = PCI_MODE_RC, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .max_lanes = 1, }; static const struct j721e_pcie_data am64_pcie_ep_data = { .mode = PCI_MODE_EP, .linkdown_irq_regfield = J7200_LINK_DOWN, + .max_lanes = 1, }; static const struct of_device_id of_j721e_pcie_match[] = { @@ -432,7 +437,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->user_cfg_base = base; ret = of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > MAX_LANES) + if (ret || num_lanes > data->max_lanes) num_lanes = 1; pcie->num_lanes = num_lanes; From patchwork Thu Nov 24 08:12:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13054678 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B68D6C46467 for ; Thu, 24 Nov 2022 08:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230016AbiKXIOT (ORCPT ); Thu, 24 Nov 2022 03:14:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229773AbiKXINQ (ORCPT ); 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Thu, 24 Nov 2022 02:12:46 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 24 Nov 2022 02:12:46 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8ChYt026061; Thu, 24 Nov 2022 02:12:45 -0600 From: Matt Ranostay To: , , , , , , , , , , CC: , , , , Matt Ranostay Subject: [PATCH v7 3/5] PCI: j721e: Add PCIe 4x lane selection support Date: Thu, 24 Nov 2022 00:12:19 -0800 Message-ID: <20221124081221.1206167-4-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221124081221.1206167-1-mranostay@ti.com> References: <20221124081221.1206167-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra Reviewed-by: Roger Quadros --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 8990f58d64d5..dab3db9be6d8 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = GENMASK(8, 8); u32 val = 0; int ret; + if (pcie->max_lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) ret = of_property_read_u32(node, "num-lanes", &num_lanes); if (ret || num_lanes > data->max_lanes) num_lanes = 1; + + pcie->max_lanes = data->max_lanes; pcie->num_lanes = num_lanes; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) From patchwork Thu Nov 24 08:12:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13054679 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95A7CC4708B for ; Thu, 24 Nov 2022 08:14:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbiKXIOW (ORCPT ); Thu, 24 Nov 2022 03:14:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229848AbiKXINj (ORCPT ); Thu, 24 Nov 2022 03:13:39 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 523B453EE1; Thu, 24 Nov 2022 00:13:00 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8CqZ7025091; Thu, 24 Nov 2022 02:12:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669277572; bh=32Ubr6pDmwWnVPRGFAMV+5MACScah3nsX53UXKG5qPs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=n5NJZjya4w2wmH047lBAXkjaTZVRRemzt5Erx6L8AAqofXpYdsN2KINByQnv75ZW9 xPfp0ZL3ZX9ArViPNswVlklLj+yAu1IS75sJOUDn7w05qPUzUJGu23XkO6ceXLZ3I0 WoNzVBkVxNK6LagtYV+PJKQi1Z65mkwAJqDHsIu4= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AO8Cqd7064121 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Nov 2022 02:12:52 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 24 Nov 2022 02:12:52 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 24 Nov 2022 02:12:52 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8Cm1D022325; Thu, 24 Nov 2022 02:12:50 -0600 From: Matt Ranostay To: , , , , , , , , , , CC: , , , , Matt Ranostay Subject: [PATCH v7 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Date: Thu, 24 Nov 2022 00:12:20 -0800 Message-ID: <20221124081221.1206167-5-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221124081221.1206167-1-mranostay@ti.com> References: <20221124081221.1206167-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add definition for j784s4-pci-ep + j784s4-pci-host devices along with schema checks for num-lanes. Signed-off-by: Matt Ranostay Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++++++ .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 1aeea168d3d0..2e6226cbd1d3 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - const: ti,j721e-pcie-ep + - const: ti,j784s4-pcie-ep - description: PCIe EP controller in AM64 items: - const: ti,am64-pcie-ep @@ -87,6 +88,17 @@ allOf: minimum: 1 maximum: 2 + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 8eca0d08303f..100d3f556adb 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - const: ti,j721e-pcie-host + - const: ti,j784s4-pcie-host - description: PCIe controller in AM64 items: - const: ti,am64-pcie-host @@ -120,6 +121,17 @@ allOf: minimum: 1 maximum: 2 + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg From patchwork Thu Nov 24 08:12:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13054681 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F8CC43219 for ; Thu, 24 Nov 2022 08:14:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230007AbiKXIOs (ORCPT ); Thu, 24 Nov 2022 03:14:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbiKXIOI (ORCPT ); Thu, 24 Nov 2022 03:14:08 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22F0991C2B; Thu, 24 Nov 2022 00:13:13 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8CvFH028202; Thu, 24 Nov 2022 02:12:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669277577; bh=pQRNSGirOQXjd3vm3b5fncqcHi4AeVKpPaZV1zeypiI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cNqv/qkfAfNjBdcTYA/5r4/6cQa59T0HTvpNacBRLazkMGNWIEO+hDP84Ti1rJd6V osB5tJKGP0Mp27hhZsPjwQk4fqmwjD/ne28eV7+UBGRgohCGr6v4d8cnhCTBwhvbUF 9E7NxVVnUKVH5h9Vr3mgFat+TrNCOFqk/W2FahTw= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AO8Cvx2021586 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Nov 2022 02:12:57 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 24 Nov 2022 02:12:57 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 24 Nov 2022 02:12:57 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AO8Cs01010102; Thu, 24 Nov 2022 02:12:56 -0600 From: Matt Ranostay To: , , , , , , , , , , CC: , , , , Matt Ranostay , Achal Verma Subject: [PATCH v7 5/5] PCI: j721e: add j784s4 PCIe configuration Date: Thu, 24 Nov 2022 00:12:21 -0800 Message-ID: <20221124081221.1206167-6-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221124081221.1206167-1-mranostay@ti.com> References: <20221124081221.1206167-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe configuration for j784s4 platform which has 4x lane support. Tested-by: Achal Verma Signed-off-by: Matt Ranostay Reviewed-by: Roger Quadros --- drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index dab3db9be6d8..c484d658c18a 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -330,6 +330,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .is_intc_v1 = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -355,6 +370,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, };