From patchwork Mon Nov 28 02:54:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13056999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C8A8C433FE for ; Mon, 28 Nov 2022 02:56:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=7ILIX1kvJeKLT9ybSoqt51rwdOkGS5nsh0W3yrtMCcQ=; b=hlfxKQYYHBR9JM bN0V8e0l35EepaAs3/rAglbl1uEmLo7ObI7owbU8urpbmM7RvMyEMw6tmNr6b6oDvQVsvHSAuSfT/ ZaSybNKaKrZ398F0NKj5WOAO50ofULsNPn4Lvh0BtP6v1M87BrpP9gc4Foj6ZXc7BL8PcDbblkHdP iEX3G4tcJrevRs4WdWm3P46zy0j2i7FsJB4HyaCLSsRlQPshwkHaTUiH8fJwqOND4f7m3AIoSEQ0e HiYXyIGXY+xPJADMpM6Oqz6nqq14gS2X0U0icdDs5rg/L14pNOAMWOBwiSQhdZseS22F5xtb9h7SI LC005gMkBg00+5QKImcg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozUIY-00FF6w-CT; Mon, 28 Nov 2022 02:55:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozUIU-00FF2F-JM for linux-arm-kernel@lists.infradead.org; Mon, 28 Nov 2022 02:55:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93449D6E; Sun, 27 Nov 2022 18:55:06 -0800 (PST) Received: from a077893.blr.arm.com (unknown [10.162.40.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 096A63F73D; Sun, 27 Nov 2022 18:54:56 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, will@kernel.org Cc: Anshuman Khandual , Arnaldo Carvalho de Melo , Mark Rutland , Catalin Marinas , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64/perf: Replace PMU version number '0' with ID_AA64DFR0_EL1_PMUVer_NI Date: Mon, 28 Nov 2022 08:24:49 +0530 Message-Id: <20221128025449.39085-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221127_185506_706535_F986DE2D X-CRM114-Status: UNSURE ( 9.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org __armv8pmu_probe_pmu() returns if detected PMU is either not implemented or implementation defined. Extracted ID_AA64DFR0_EL1_PMUVer value, when PMU is not implemented is '0' which can be replaced with ID_AA64DFR0_EL1_PMUVer_NI defined as '0b0000'. Cc: Arnaldo Carvalho de Melo Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Cc: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Anshuman Khandual Acked-by: Mark Rutland --- This applies on v6.1-rc6 arch/arm64/kernel/perf_event.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 85a3aaefc0fb..b638f584b4dd 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1188,7 +1188,8 @@ static void __armv8pmu_probe_pmu(void *info) dfr0 = read_sysreg(id_aa64dfr0_el1); pmuver = cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_PMUVer_SHIFT); - if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF || pmuver == 0) + if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF || + pmuver == ID_AA64DFR0_EL1_PMUVer_NI) return; cpu_pmu->pmuver = pmuver;