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Mon, 28 Nov 2022 05:49:37 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::28d6:1b8:94d9:89f5]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::28d6:1b8:94d9:89f5%7]) with mapi id 15.20.5857.023; Mon, 28 Nov 2022 05:49:37 +0000 From: Chester Lin To: Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Rob Herring , Krzysztof Kozlowski Cc: Chester Lin , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger , Jan Petrous Subject: [PATCH v2 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Date: Mon, 28 Nov 2022 13:49:16 +0800 Message-Id: <20221128054920.2113-2-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221128054920.2113-1-clin@suse.com> References: <20221128054920.2113-1-clin@suse.com> X-ClientProxiedBy: TYCP286CA0144.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::8) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: c6364fc4-c3ec-4107-033d-08dad104557e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The maxItems of clock and clock-names need be increased because S32CC has up to 11 clocks for its DWMAC. Signed-off-by: Chester Lin --- No change in v2. Documentation/devicetree/bindings/net/snps,dwmac.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 13b984076af5..c174d173591e 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -65,6 +65,7 @@ properties: - ingenic,x2000-mac - loongson,ls2k-dwmac - loongson,ls7a-dwmac + - nxp,s32cc-dwmac - renesas,r9a06g032-gmac - renesas,rzn1-gmac - rockchip,px30-gmac @@ -110,7 +111,7 @@ properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 11 additionalItems: true items: - description: GMAC main clock @@ -122,7 +123,7 @@ properties: clock-names: minItems: 1 - maxItems: 8 + maxItems: 11 additionalItems: true contains: enum: From patchwork Mon Nov 28 05:49:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 13057039 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74AD9C433FE for ; Mon, 28 Nov 2022 05:50:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229739AbiK1FuS (ORCPT ); Mon, 28 Nov 2022 00:50:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229683AbiK1FuA (ORCPT ); Mon, 28 Nov 2022 00:50:00 -0500 Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-db5eur01on2087.outbound.protection.outlook.com [40.107.15.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5187113F64; Sun, 27 Nov 2022 21:49:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WQp9PXoC5OOcy19E8Z86VgAFjls+H2EIc8G46tpo1ufkzR+k6GyG1tr7DgZt7KjmDtyQlEHmkWU7Biw7u9dTxv0sPc8OCOmK/ZJ1CZ96ezlCBkf6hcv1nBKf5axmKk6QNttJrz1kXB06j30VGuz3rKEzB67OWCzdKJLtDpvlNfhzf9rxSBgVQ2Iv8ST3/ydVsIZXb2eM5M7Lj8Ib/n5/kNuKioS9BoVubnEPiFRsrZAQbCuvJw+k2z9rPwstrpp6sO31NkdJAXs/GGvM7hIn11wrBky1TgzBFuWQM6R2VJmy6Q11q7YW2MJ1QN1Nmu+oYOp6cfr2+yLd25eopXY+uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AhXmGvpVPy984cYgkhg8LOOX/aSZ61B1z9C6x92i3Hc=; b=hVpt/lzVlM94MuNDs0iq4ExnbEtxDKGAN4UBok7yDpqEubzJ/WYBpGfi3mpLzTfVooChVt4z946k56Mafj4p/jPQUK+g13JbJBjZ8EZxDO6iT7G3VnmPYLlHS/gYXzVE5DDTxb67f39gKXdU/sqTjiZ5GaH7s4suyXBEpTTOezaDD+Z3uztjb8HmoDMHutx7rxermwe530/iAapMd+XTiek7ofUcVPStpmWXNH1CN16+JZDmAaIpDcEjDbTxZxWncROcFyN0Q4ku4QWVHF1JewfUj+iFERamh8XqPcKGHGYe7Q1SwxkR3fP3F99jOvnP8N3Fs9FEWEohT3taOWxXXQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AhXmGvpVPy984cYgkhg8LOOX/aSZ61B1z9C6x92i3Hc=; b=3LLJz5WoeCMJWa+c2Q8vZAaEmWBTPRM4kWfiqNQ5NUcElV3LU+ytuHDL3Wqy345xkaqHGRFd3UURnyC4j2hH2KR7EyN4dY46O8vAPcYfPvZMWZekh4h0293YgDGQ1eEqRQ1afIvZeL21+Qha/O8AXZOHjabTIXxf2cNMTuZJywUhlAzs31zi8ysqMK9yGr5JKS8kjguL+A1qTCd91Jf8MSjbRIB3VPb4SX3Nsvn8do24EIDOo0UxJ2b433GdAguv1ZUvgtV5GKujDFI+vSY61Mp4+Aa8apysdVOErx0tYqKYN4QS4Nwj3QNZeZ0XQ681FSC8ZKdUrHfH22Uu13dXlg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) by AS8PR04MB7655.eurprd04.prod.outlook.com (2603:10a6:20b:292::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19; Mon, 28 Nov 2022 05:49:51 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::28d6:1b8:94d9:89f5]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::28d6:1b8:94d9:89f5%7]) with mapi id 15.20.5857.023; Mon, 28 Nov 2022 05:49:51 +0000 From: Chester Lin To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous , Andrew Lunn Cc: Chester Lin , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH v2 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Date: Mon, 28 Nov 2022 13:49:17 +0800 Message-Id: <20221128054920.2113-3-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221128054920.2113-1-clin@suse.com> References: <20221128054920.2113-1-clin@suse.com> X-ClientProxiedBy: TYCP286CA0146.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::11) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: f3a04ac4-c047-4de7-c834-08dad1045da8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7t1WENTYLKuiITAQ9eRCK/TpAZbqmFZgbyqFP0bYOmHIoW3/Sa3hyPIT9DD/T8OYKyMIvWFt31GOv2j/YZjgw4GfhL+4LYxLFIGPqOkuOsMNe+HSH2UiXkUPzH22VA/RUqyPRPuPwb8Vf0zAW8qwop0VRC6+KVNsfDmp1KpkCPvMo8H9nd5Pb67eddTpNfBxgoQ07vvQnvBnmmUUh7mH1gvY8yVLD7Gj02hHg43WeDa0g/IVna4fiBvrScDB5x63UJvdjg+Ha6jeLB+JE/1hRflHkMx2/cpArjoDnLcjx5Jemiun3+6KIK6FIhguHzbarouEsYi9IZ6WKq00ozS757NjiVGDCUkWB6ndzf7aGk22oeGDvNfFtPjivJIFyly/3iEGtlNmOGf3b0czvsn49KJNM4K+1+LiO202NSO6XqxjGsZzIG2CEYjqx0fCyFyr5C0rOnRhxH4nmwzZtYL7vQY3KxMaHcav0876hkYMoAuj1l9ow+RvIn7EkDcoYoS1tfOo2c3sUXMU1OFm+5V/+dvEmyY1qawEUaImmHsLLgBemyb89qqgWbbfnWQUL4+YCKAsgZQf10Qu+mNFfZit1ywuQmXBn9hdlBVRY1+u66AZggBa4/G03i4LqCqgmI39d+p4pkiwofm8wVJR5jbQ4PAwXDpMOl2no+rZ7OXOOXY= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR0402MB3439.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(39860400002)(366004)(346002)(136003)(396003)(376002)(451199015)(2616005)(6506007)(6512007)(36756003)(7416002)(1076003)(186003)(5660300002)(54906003)(86362001)(110136005)(66476007)(8676002)(4326008)(66946007)(66556008)(2906002)(41300700001)(38100700002)(316002)(83380400001)(8936002)(478600001)(6486002)(107886003)(6666004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VLRxUtXycK94x6kM77Uwc3bkUS3kyXPSqtIQDGFzYUEeQJLUUEbIGNBWYKIPVHxJKiSeY28lzGoIlAx4ISRMJF08Jf+SVO3N67kSwOH3vmN/eTOdc5+wRYl4iaiHLdIcmaMZzjnF105SLhu0LvrQqOzUP4Ma7qXxPUgOA5m3LkzqvSmji6XLPIcC3TzZoCPp+XuWQya3r/lxDHX5r4kr58avhiLprCKRLEbkz6fGM4IJ0yp4x9hsie6X6M/YV6WJij7UdmANty408ClIwG2b3dJB37HQmAIPuiKhJdYP1EbUkE/5c8cl9YC8NcG9YARAO0igP4y77N3QL4/7MQZ+b0YuYG6ebkvx5/Ot9oJljUn3Pd1HyQVuiQmRqrVk9KO1ztelGxSGi/CyspA7iX1XJkkBADfonoPFl++6uuxffuHz84TlHEc3XBArc/rwY/gLPkwgQnsk9fadeh/5g6jxiq9u0tpxSn+1C6fRh+rBrzvomsJ8SSxs4iJvS+dyA6rryDWbN2/GorhkMxJxf5IlMCeGFWJPqSnyZk3GnjK/ZrXMBKTMmoyy3Qeam9IxflA/YG1XT05jxk2Fowi+7UE4VRM/DW+6PHA0S83ggMG9P0yySAUXxQtf+bzzRw7u0ITm1XQj7GPZqOKBCHy+mCkbh9BgUGLbREVQlY3q2Z3gKoNfjr5Egt9dnW9ttQMFUNDY6tQWrsn9QwD+A1u9kcuaDlDok9w7MirbymT1kJ35dxg+9vitcOkL5MnkC+q8uXE9/GGEu/QWoeEF4k9O8zHI/luKsAwuWaiC42HMA410aVCA3utbVSU+x/lzilCiVmJfNQ989bmam0ck8Vy5kWQiWGSV+CWnRhg1pg8lc4oa7V7wnlPzM5Vp36El38VfnZAAxaA/A7fHbTaY/lx+jO19gzxTMWTn9J2HaVhdxyQmor8+ugAffI5swGCtUONhbJcOamgZyekZboY1+ioDQkr0SGsz7GgNZRGGVDLSbN/KwtykyhlYtuw54Ga/PilfWE1vp1cRLEQg2RLkY8m7Sw/BikfulW7sP1MyL8LHMdkuS7mTwPu8PVzJ/TOllncw3u/PyVrcJcVjiBP68IXeP74Jo/SWTpSgFRXMhDe1+uN/VuqiCI7RhyAZS4MFHn7PTc605LM7Mqs9hdmtcZQzkUlMx8SRgC/2NoCj4Osk2eD9DGVZP7eVyAbUi3RqDYC7vgK+KDWApw7Q2DD72HM3I+mnQETgpa8x+o1z2jkhvu5NAmKh36jbzoUBiToLYDNwEs6ALg8zQ49PB7j/kcSZR7BF8MDWiLeNNwKv0YZAfOVo61VtUpzp2WAsVfDTf9sJyTl+acJ30z46iAK6bCU82b25RJtanFZdlrqW2reS4R0/A4zsLBva69cCKM85yAq16qsJDzFg6VLT7AUs1laf5JiGtJQiBjzuCOl85c7Pb2VaqVxsWzr5eazqS7MBZrGoU0iSxsSrQHKs/MjEiTrIDjuv8BKsiAusSEXGFuCibtLAk17g0/JP2gYko1PyNleShYLCFSFMJGtn9N07wwDpfhtKtejQnHdyPuPwoEeSAG6UawORmHtZo2dxw+LMWOXrsBom37UQ9Rdbv8i3ARmhP6p2qU1L7FJM9Mdz7UTWP/Bos8EHPzJOcWOn6dK2C14TVM7H X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: f3a04ac4-c047-4de7-c834-08dad1045da8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2022 05:49:51.1200 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zG4gk7q+fFeLbMx7WiBRsW1X0CM4AMkc7C1Eesen0NYWk5EhnpiSNwSzujmVFKPO X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7655 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common Chassis. Signed-off-by: Jan Petrous Signed-off-by: Chester Lin --- Changes in v2: - Fix schema issues. - Add minItems to clocks & clock-names. - Replace all sgmii/SGMII terms with pcs/PCS. .../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml new file mode 100644 index 000000000000..c6839fd3df40 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021-2022 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NXP S32CC DWMAC Ethernet controller + +maintainers: + - Jan Petrous + - Chester Lin + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + enum: + - nxp,s32cc-dwmac + + reg: + items: + - description: Main GMAC registers + - description: S32 MAC control registers + + dma-coherent: true + + clocks: + minItems: 5 + items: + - description: Main GMAC clock + - description: Peripheral registers clock + - description: Transmit PCS clock + - description: Transmit RGMII clock + - description: Transmit RMII clock + - description: Transmit MII clock + - description: Receive PCS clock + - description: Receive RGMII clock + - description: Receive RMII clock + - description: Receive MII clock + - description: + PTP reference clock. This clock is used for programming the + Timestamp Addend Register. If not passed then the system + clock will be used. + + clock-names: + minItems: 5 + items: + - const: stmmaceth + - const: pclk + - const: tx_pcs + - const: tx_rgmii + - const: tx_rmii + - const: tx_mii + - const: rx_pcs + - const: rx_rgmii + - const: rx_rmii + - const: rx_mii + - const: ptp_ref + + tx-fifo-depth: + const: 20480 + + rx-fifo-depth: + const: 20480 + +required: + - compatible + - reg + - tx-fifo-depth + - rx-fifo-depth + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + #define S32GEN1_SCMI_CLK_GMAC0_AXI + #define S32GEN1_SCMI_CLK_GMAC0_TX_PCS + #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_MII + #define S32GEN1_SCMI_CLK_GMAC0_RX_PCS + #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_MII + #define S32GEN1_SCMI_CLK_GMAC0_TS + + soc { + #address-cells = <1>; + #size-cells = <1>; + + gmac0: ethernet@4033c000 { + compatible = "nxp,s32cc-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007C004 0x4>; /* S32 CTRL_STS reg */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + tx-fifo-depth = <20480>; + rx-fifo-depth = <20480>; + dma-coherent; + clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, + <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_PCS>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_PCS>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TS>; + clock-names = "stmmaceth", "pclk", + "tx_pcs", "tx_rgmii", "tx_rmii", "tx_mii", + "rx_pcs", "rx_rgmii", "rx_rmii", "rx_mii", + "ptp_ref"; + + gmac0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethernet-phy@4 { + reg = <0x04>; + }; + }; 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Signed-off-by: Jan Petrous Signed-off-by: Chester Lin --- No change in v2. drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++ include/linux/stmmac.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 6b5d96bced47..5b7e8cc70439 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -222,6 +222,8 @@ struct stmmac_safety_stats { #define CSR_F_150M 150000000 #define CSR_F_250M 250000000 #define CSR_F_300M 300000000 +#define CSR_F_500M 500000000 +#define CSR_F_800M 800000000 #define MAC_CSR_H_FRQ_MASK 0x20 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 6b43da78cdf0..ff0b32c9e748 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -323,6 +323,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; + else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M)) + priv->clk_csr = STMMAC_CSR_300_500M; + else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M)) + priv->clk_csr = STMMAC_CSR_500_800M; } if (priv->plat->has_sun8i) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index fb2e88614f5d..307980c808f7 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -34,6 +34,8 @@ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ +#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */ +#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0 From patchwork Mon Nov 28 05:49:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 13057041 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23594C433FE for ; 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Signed-off-by: Ondrej Spacek Signed-off-by: Chester Lin --- No change in v2. drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 ++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +++- drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 +++++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++ include/linux/stmmac.h | 7 +++++++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index d99fa028c646..4e6e2952abfd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -517,6 +517,15 @@ static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) return 0; } +static void dwmac4_axi4_cc(void __iomem *ioaddr, + struct stmmac_axi4_ace_ctrl *acecfg) +{ + /* Configure AXI4 cache coherency for Tx/Rx DMA channels */ + writel(acecfg->tx_ar_reg, ioaddr + DMA_AXI4_TX_AR_ACE_CONTROL); + writel(acecfg->rx_aw_reg, ioaddr + DMA_AXI4_RX_AW_ACE_CONTROL); + writel(acecfg->txrx_awar_reg, ioaddr + DMA_AXI4_TXRX_AWAR_ACE_CONTROL); +} + const struct stmmac_dma_ops dwmac4_dma_ops = { .reset = dwmac4_dma_reset, .init = dwmac4_dma_init, @@ -574,4 +583,5 @@ const struct stmmac_dma_ops dwmac410_dma_ops = { .set_bfsize = dwmac4_set_bfsize, .enable_sph = dwmac4_enable_sph, .enable_tbs = dwmac4_enable_tbs, + .axi4_cc = dwmac4_axi4_cc, }; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h index 9321879b599c..7f491f2651b2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h @@ -21,7 +21,9 @@ #define DMA_DEBUG_STATUS_0 0x0000100c #define DMA_DEBUG_STATUS_1 0x00001010 #define DMA_DEBUG_STATUS_2 0x00001014 -#define DMA_AXI_BUS_MODE 0x00001028 +#define DMA_AXI4_TX_AR_ACE_CONTROL 0x00001020 +#define DMA_AXI4_RX_AW_ACE_CONTROL 0x00001024 +#define DMA_AXI4_TXRX_AWAR_ACE_CONTROL 0x00001028 #define DMA_TBS_CTRL 0x00001050 /* DMA Bus Mode bitmap */ diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h index 592b4067f9b8..bffe2ec36bb3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h @@ -212,6 +212,9 @@ struct stmmac_dma_ops { void (*set_bfsize)(void __iomem *ioaddr, int bfsize, u32 chan); void (*enable_sph)(void __iomem *ioaddr, bool en, u32 chan); int (*enable_tbs)(void __iomem *ioaddr, bool en, u32 chan); + /* Configure AXI4 cache coherency for Tx and Rx DMA channels */ + void (*axi4_cc)(void __iomem *ioaddr, + struct stmmac_axi4_ace_ctrl *acecfg); }; #define stmmac_reset(__priv, __args...) \ @@ -272,6 +275,8 @@ struct stmmac_dma_ops { stmmac_do_void_callback(__priv, dma, enable_sph, __args) #define stmmac_enable_tbs(__priv, __args...) \ stmmac_do_callback(__priv, dma, enable_tbs, __args) +#define stmmac_axi4_cc(__priv, __args...) \ + stmmac_do_void_callback(__priv, dma, axi4_cc, __args) struct mac_device_info; struct net_device; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index ff0b32c9e748..c689723c7d93 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2917,6 +2917,9 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) if (priv->plat->axi) stmmac_axi(priv, priv->ioaddr, priv->plat->axi); + if (priv->plat->axi4_ace_ctrl) + stmmac_axi4_cc(priv, priv->ioaddr, priv->plat->axi4_ace_ctrl); + /* DMA CSR Channel configuration */ for (chan = 0; chan < dma_csr_ch; chan++) { stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 307980c808f7..23e740c6c7b8 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -115,6 +115,12 @@ struct stmmac_axi { bool axi_rb; }; +struct stmmac_axi4_ace_ctrl { + u32 tx_ar_reg; + u32 rx_aw_reg; + u32 txrx_awar_reg; +}; + #define EST_GCL 1024 struct stmmac_est { struct mutex lock; @@ -248,6 +254,7 @@ struct plat_stmmacenet_data { struct reset_control *stmmac_rst; struct reset_control *stmmac_ahb_rst; struct stmmac_axi *axi; + struct stmmac_axi4_ace_ctrl *axi4_ace_ctrl; int has_gmac4; bool has_sun8i; bool tso_en; From patchwork Mon Nov 28 05:49:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 13057042 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8593EC433FE for ; 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This driver is mainly based on NXP's downstream implementation on CodeAurora[1]. [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/net/ethernet/stmicro/stmmac?h=bsp34.0-5.10.120-rt Signed-off-by: Jan Petrous Signed-off-by: Ghennadi Procopciuc Signed-off-by: Andra-Teodora Ilie Signed-off-by: Chester Lin --- Changes in v2: - Replace clock names tx_sgmii/rx_sgmii with tx_pcs/rx_pcs. - Adjust error handlings while calling devm_clk_get(). - Remove redundant dev_info messages. - Remove unnecessary if conditions. - Fix the copyright format suggested by NXP. drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 304 ++++++++++++++++++ 3 files changed, 318 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 31ff35174034..dd3fb5e462b7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -153,6 +153,19 @@ config DWMAC_ROCKCHIP This selects the Rockchip RK3288 SoC glue layer support for the stmmac device driver. +config DWMAC_S32CC + tristate "NXP S32 series GMAC support" + default ARCH_S32 + depends on OF && (ARCH_S32 || COMPILE_TEST) + select MFD_SYSCON + select PHYLINK + help + Support for ethernet controller on NXP S32 series SOCs. + + This selects NXP SoC glue layer support for the stmmac + device driver. This driver is used for the S32 series + SOCs GMAC ethernet controller. + config DWMAC_SOCFPGA tristate "SOCFPGA dwmac support" default ARCH_INTEL_SOCFPGA diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d4e12e9ace4f..ec92cc2becd7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o +obj-$(CONFIG_DWMAC_S32CC) += dwmac-s32cc.o stmmac-platform-objs:= stmmac_platform.o dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c new file mode 100644 index 000000000000..92a132ad985a --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DWMAC Specific Glue layer for NXP S32 Common Chassis + * + * Copyright 2019-2022 NXP + * Copyright (C) 2022 SUSE LLC + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define GMAC_TX_RATE_125M 125000000 /* 125MHz */ +#define GMAC_TX_RATE_25M 25000000 /* 25MHz */ +#define GMAC_TX_RATE_2M5 2500000 /* 2.5MHz */ + +/* S32 SRC register for phyif selection */ +#define PHY_INTF_SEL_MII 0x00 +#define PHY_INTF_SEL_SGMII 0x01 +#define PHY_INTF_SEL_RGMII 0x02 +#define PHY_INTF_SEL_RMII 0x08 + +/* AXI4 ACE control settings */ +#define ACE_DOMAIN_SIGNAL 0x2 +#define ACE_CACHE_SIGNAL 0xf +#define ACE_CONTROL_SIGNALS ((ACE_DOMAIN_SIGNAL << 4) | ACE_CACHE_SIGNAL) +#define ACE_PROTECTION 0x2 + +struct s32cc_priv_data { + void __iomem *ctrl_sts; + struct device *dev; + phy_interface_t intf_mode; + struct clk *tx_clk; + struct clk *rx_clk; +}; + +static int s32cc_gmac_init(struct platform_device *pdev, void *priv) +{ + struct s32cc_priv_data *gmac = priv; + u32 intf_sel; + int ret; + + ret = clk_prepare_enable(gmac->tx_clk); + if (ret) { + dev_err(&pdev->dev, "Can't enable tx clock\n"); + return ret; + } + + ret = clk_prepare_enable(gmac->rx_clk); + if (ret) { + dev_err(&pdev->dev, "Can't enable rx clock\n"); + return ret; + } + + /* set interface mode */ + switch (gmac->intf_mode) { + case PHY_INTERFACE_MODE_SGMII: + intf_sel = PHY_INTF_SEL_SGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + intf_sel = PHY_INTF_SEL_RGMII; + break; + case PHY_INTERFACE_MODE_RMII: + intf_sel = PHY_INTF_SEL_RMII; + break; + case PHY_INTERFACE_MODE_MII: + intf_sel = PHY_INTF_SEL_MII; + break; + default: + dev_err(&pdev->dev, "Unsupported PHY interface: %s\n", + phy_modes(gmac->intf_mode)); + return -EINVAL; + } + + writel(intf_sel, gmac->ctrl_sts); + + dev_dbg(&pdev->dev, "PHY mode set to %s\n", phy_modes(gmac->intf_mode)); + + return 0; +} + +static void s32cc_gmac_exit(struct platform_device *pdev, void *priv) +{ + struct s32cc_priv_data *gmac = priv; + + clk_disable_unprepare(gmac->tx_clk); + clk_disable_unprepare(gmac->rx_clk); +} + +static void s32cc_fix_speed(void *priv, unsigned int speed) +{ + struct s32cc_priv_data *gmac = priv; + + /* SGMII mode doesn't support the clock reconfiguration */ + if (gmac->intf_mode == PHY_INTERFACE_MODE_SGMII) + return; + + switch (speed) { + case SPEED_1000: + dev_info(gmac->dev, "Set TX clock to 125M\n"); + clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_125M); + break; + case SPEED_100: + dev_info(gmac->dev, "Set TX clock to 25M\n"); + clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_25M); + break; + case SPEED_10: + dev_info(gmac->dev, "Set TX clock to 2.5M\n"); + clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_2M5); + break; + default: + dev_err(gmac->dev, "Unsupported/Invalid speed: %d\n", speed); + return; + } +} + +static int s32cc_config_cache_coherency(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat) +{ + plat_dat->axi4_ace_ctrl = + devm_kzalloc(&pdev->dev, + sizeof(struct stmmac_axi4_ace_ctrl), + GFP_KERNEL); + + if (!plat_dat->axi4_ace_ctrl) + return -ENOMEM; + + plat_dat->axi4_ace_ctrl->tx_ar_reg = (ACE_CONTROL_SIGNALS << 16) + | (ACE_CONTROL_SIGNALS << 8) | ACE_CONTROL_SIGNALS; + + plat_dat->axi4_ace_ctrl->rx_aw_reg = (ACE_CONTROL_SIGNALS << 24) + | (ACE_CONTROL_SIGNALS << 16) | (ACE_CONTROL_SIGNALS << 8) + | ACE_CONTROL_SIGNALS; + + plat_dat->axi4_ace_ctrl->txrx_awar_reg = (ACE_PROTECTION << 20) + | (ACE_PROTECTION << 16) | (ACE_CONTROL_SIGNALS << 8) + | ACE_CONTROL_SIGNALS; + + return 0; +} + +static int s32cc_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct s32cc_priv_data *gmac; + struct resource *res; + const char *tx_clk, *rx_clk; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); + if (!gmac) + return PTR_ERR(gmac); + + gmac->dev = &pdev->dev; + + /* S32G control reg */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + gmac->ctrl_sts = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR_OR_NULL(gmac->ctrl_sts)) { + dev_err(&pdev->dev, "S32CC config region is missing\n"); + return PTR_ERR(gmac->ctrl_sts); + } + + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + plat_dat->bsp_priv = gmac; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + tx_clk = "tx_pcs"; + rx_clk = "rx_pcs"; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + tx_clk = "tx_rgmii"; + rx_clk = "rx_rgmii"; + break; + case PHY_INTERFACE_MODE_RMII: + tx_clk = "tx_rmii"; + rx_clk = "rx_rmii"; + break; + case PHY_INTERFACE_MODE_MII: + tx_clk = "tx_mii"; + rx_clk = "rx_mii"; + break; + default: + dev_err(&pdev->dev, "Not supported phy interface mode: [%s]\n", + phy_modes(plat_dat->phy_interface)); + return -EINVAL; + }; + + gmac->intf_mode = plat_dat->phy_interface; + + /* DMA cache coherency settings */ + if (of_dma_is_coherent(pdev->dev.of_node)) { + ret = s32cc_config_cache_coherency(pdev, plat_dat); + if (ret) + goto err_remove_config_dt; + } + + /* tx clock */ + gmac->tx_clk = devm_clk_get(&pdev->dev, tx_clk); + if (IS_ERR(gmac->tx_clk)) { + dev_err(&pdev->dev, "Get TX clock failed\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + + /* rx clock */ + gmac->rx_clk = devm_clk_get(&pdev->dev, rx_clk); + if (IS_ERR(gmac->rx_clk)) { + dev_err(&pdev->dev, "Get RX clock failed\n"); + ret = PTR_ERR(gmac->rx_clk); + goto err_remove_config_dt; + } + + ret = s32cc_gmac_init(pdev, gmac); + if (ret) + goto err_remove_config_dt; + + /* core feature set */ + plat_dat->has_gmac4 = true; + plat_dat->pmt = 1; + + plat_dat->init = s32cc_gmac_init; + plat_dat->exit = s32cc_gmac_exit; + plat_dat->fix_mac_speed = s32cc_fix_speed; + + /* safety feature config */ + plat_dat->safety_feat_cfg = + devm_kzalloc(&pdev->dev, sizeof(*plat_dat->safety_feat_cfg), + GFP_KERNEL); + + if (!plat_dat->safety_feat_cfg) { + dev_err(&pdev->dev, "Allocate safety_feat_cfg failed\n"); + goto err_gmac_exit; + } + + plat_dat->safety_feat_cfg->tsoee = 1; + plat_dat->safety_feat_cfg->mrxpee = 1; + plat_dat->safety_feat_cfg->mestee = 1; + plat_dat->safety_feat_cfg->mrxee = 1; + plat_dat->safety_feat_cfg->mtxee = 1; + plat_dat->safety_feat_cfg->epsi = 1; + plat_dat->safety_feat_cfg->edpp = 1; + plat_dat->safety_feat_cfg->prtyen = 1; + plat_dat->safety_feat_cfg->tmouten = 1; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_gmac_exit; + + return 0; + +err_gmac_exit: + s32cc_gmac_exit(pdev, plat_dat->bsp_priv); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + return ret; +} + +static const struct of_device_id s32_dwmac_match[] = { + { .compatible = "nxp,s32cc-dwmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, s32_dwmac_match); + +static struct platform_driver s32_dwmac_driver = { + .probe = s32cc_dwmac_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "s32cc-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = s32_dwmac_match, + }, +}; +module_platform_driver(s32_dwmac_driver); + +MODULE_AUTHOR("Jan Petrous "); +MODULE_DESCRIPTION("NXP S32 common chassis GMAC driver"); +MODULE_LICENSE("GPL v2");