From patchwork Mon Nov 28 09:22:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13057178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B10D3C433FE for ; Mon, 28 Nov 2022 09:24:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DhZj2/XUSbSYepETLet2n5JA7ggFOL4zF7MdkkVKaHg=; b=hMj+M6w3tdJiNg 0gWVmhz1pRYfYMiiLnREP8YCowIvEgm6Xft36cbVgQpX8r1XwkaYusLFaU6xfsinUCYiY0Dwi6mS6 m25cm/hSBLjDbGPFz1ThFl1UvFviv7jdv9dnHBf5M1NajGYYKmldN9jPTP8k4G15/uDU8GyntU47t vTEeYe3aqCLNMRkPsQXuJ8tc9xYydT4TErOFwYgJeTVrwLOIN/h4HNJ/qY0eB1ztmXODP6OrhLoCC CusYjToUZZZNge9oqRQSYJvoTXh84sM+f69OswG7ql91fvJXgV8yFxFCiUtPuAeddLAdSij+air2Z dC4LWDt/K+EVRhlkdUXg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozaLw-000b0K-1E; Mon, 28 Nov 2022 09:23:04 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozaLL-000akA-1o; Mon, 28 Nov 2022 09:22:29 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2ED796602A89; Mon, 28 Nov 2022 09:22:22 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669627342; bh=8E9V/iMHvBxjB98xrLavQ6uGlM/JoXxCkUogZXNGwB4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lUrC4WjzwumMeYZvcEh7NGbHTOaZphbCWSXFLGRsIXSbnFWikcmqvT0cncOmZxOxd KWD9siIn7IGBhe/BJUs7Lksl9o3KiHXGIaFB/0S/oQi6LKQwtBUj2mF0Hzetf5D9h7 4b7UG72zgRceULxQ+sqcKSMD2XYb58J7fg5m3SDNDRATU75JJVBMKu6IAOKw3rqjDP pPNPl/tnaoVRDUxLgiGO/47WCEQ8NYU4uh5aOiCURwxMoM6HktbXLHUtPpWOUPH5Oe rqc9VMbwGIYbyqm9CYc61MH6uVqJpcxgbNl8uvKQeESXUQOjXeH7/VLH4xG+1x/clw iQGaRLJ/Fg5SA== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno , Krzysztof Kozlowski Subject: [PATCH v3 1/4] dt-bindings: interrupt-controller: mediatek,cirq: Migrate to dt schema Date: Mon, 28 Nov 2022 10:22:14 +0100 Message-Id: <20221128092217.36552-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> References: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221128_012227_377700_1523CB21 X-CRM114-Status: GOOD ( 17.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Migrate mediatek,cirq.txt to dt schema as mediatek,mtk-cirq.yaml. While at it, I've also fixed some typos that were present in the original txt binding, as it was suggesting that the compatible string would have "mediatek,cirq" as compatible but, in reality, that's supposed to be "mediatek,mtk-cirq" instead. Little rewording on property descriptions also happened for them to be more concise. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Reviewed-by: Alexandre Mergnat --- .../interrupt-controller/mediatek,cirq.txt | 33 --------- .../mediatek,mtk-cirq.yaml | 67 +++++++++++++++++++ 2 files changed, 67 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt deleted file mode 100644 index 5865f4f2c69d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Mediatek 27xx cirq - -In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to -work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC. -The external interrupts (outside MCUSYS) will feed through CIRQ and connect -to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive -interrupts and generate a pulse signal to parent interrupt controller when -flush command is executed. With CIRQ, MCUSYS can be completely turned off -to improve the system power consumption without losing interrupts. - -Required properties: -- compatible: should be one of - - "mediatek,mt2701-cirq" for mt2701 CIRQ - - "mediatek,mt8135-cirq" for mt8135 CIRQ - - "mediatek,mt8173-cirq" for mt8173 CIRQ - and "mediatek,cirq" as a fallback. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the cirq registers and length of memory - mapped region. -- mediatek,ext-irq-range: Identifies external irq number range in different - SOCs. - -Example: - cirq: interrupt-controller@10204000 { - compatible = "mediatek,mt2701-cirq", - "mediatek,mtk-cirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&sysirq>; - reg = <0 0x10204000 0 0x400>; - mediatek,ext-irq-start = <32 200>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml new file mode 100644 index 000000000000..4f1132c077ff --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Interrupt Controller + +maintainers: + - Youlin Pei + +description: + In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to + work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC. + The external interrupts (outside MCUSYS) will feed through CIRQ and connect + to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive + interrupts and generate a pulse signal to parent interrupt controller when + flush command is executed. With CIRQ, MCUSYS can be completely turned off + to improve the system power consumption without losing interrupts. + + +properties: + compatible: + items: + - enum: + - mediatek,mt2701-cirq + - mediatek,mt8135-cirq + - mediatek,mt8173-cirq + - const: mediatek,mtk-cirq + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 3 + + interrupt-controller: true + + mediatek,ext-irq-range: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: First CIRQ interrupt + - description: Last CIRQ interrupt + description: + Identifies the range of external interrupts in different SoCs + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - mediatek,ext-irq-range + +additionalProperties: false + +examples: + - | + #include + + cirq: interrupt-controller@10204000 { + compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq"; + reg = <0x10204000 0x400>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&sysirq>; + mediatek,ext-irq-range = <32 200>; + }; From patchwork Mon Nov 28 09:22:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13057175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26783C4332F for ; Mon, 28 Nov 2022 09:23:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ziv7kaYbQIi9P8Gi8+f8MOy5DXyOwUz+iGQVHF/7XbE=; b=eiILLVnB+rKZxL 3GySvvNOCGZzpNqsoYqRDGgRnyWptqzMKSmDlsOHCMeP7sIS64wljZKZ5gncMoCuP/wV3zmRCQrjL EkEBj2G+TJlUyd5MFLh8Z73QdZtNewPUJYocRAKvLQApahAitN1O+8B13iEgT1YbOEm8JdLimd/l4 sSWOJwIIzp9hdppw1Ne2b5MG3gzxKIEByEWiLo9QdbsuKBAB2Lwum3MAZNtflzQqEyLaTd2WSLAZA 7vlSzXkNfxu5oX7qRWfTGIkD27z2oJHGzP++LgTpnxR6r1cwhdzTdEj03O6SD9i/E2OwSof+06GN8 gB4J3ivkLNwNRufRcR2Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozaLO-000ann-BL; Mon, 28 Nov 2022 09:22:30 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozaLL-000akH-1q; Mon, 28 Nov 2022 09:22:28 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 121016602ACB; Mon, 28 Nov 2022 09:22:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669627343; bh=NwKmpaNcpbD7LP5LEcTP4r+ZafVpwkZH2doF2FPT2FA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mdlperkZdsmfgcIUIG3STLumNuiVk9HOFU5Tw2htgFEcGiUprzqqOXarQGKuluf2T mOK4sn8gJ66G4sNaJkMO653vYEzyryhjgBhQ+2L7eu4dfm2Rojpyhtjmis8NNS7iOW raKkyAUQbCHX51QgurmvvQi6BH87nZbDmDyifl4Ixn6oIs1TwVA1OTUlV9TGRwZt7y I4sjxnK6US6qb0P/au5hOTofaSE4t7O0PK5e0A35UugaAH4SYKCw3CrQnSsiIOP2IB rCYVa4nEMZrS0RviavXPGK6ovKvXDAR7qcMxZaAneElaZAAYjDoSujJkcJ4EqcLLam Nm0MJHpGFVSCA== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno , Krzysztof Kozlowski Subject: [PATCH v3 2/4] dt-bindings: interrupt-controller: mediatek,cirq: Document MT8192 Date: Mon, 28 Nov 2022 10:22:15 +0100 Message-Id: <20221128092217.36552-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> References: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221128_012227_292247_AE11D0C7 X-CRM114-Status: UNSURE ( 7.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add compatible to support the SYS_CIRQ controller found on MT8192. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/interrupt-controller/mediatek,mtk-cirq.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml index 4f1132c077ff..fdcb4d8db818 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-cirq - mediatek,mt8135-cirq - mediatek,mt8173-cirq + - mediatek,mt8192-cirq - const: mediatek,mtk-cirq reg: From patchwork Mon Nov 28 09:22:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13057177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7B37C433FE for ; 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Mon, 28 Nov 2022 09:22:51 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozaLL-000akK-D3; Mon, 28 Nov 2022 09:22:29 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E4C4B6602ACD; Mon, 28 Nov 2022 09:22:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669627344; bh=32ufF8mWQ76mzZ5g0aMyF+USFsqUYsn/m1kjTdJpMXc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VYNdmUYHNRMqyBLOUgKC2BDNXZgGAoGOqzyaC5jO9VljbA9KpYMT8RA1U8CCT3vOy CoZZIDLoGUx2iSc++hXg7nCh9mar5rq5SbhuAmMUuzENmUz3o/lwdF8pxPAw8Zeiyf YFfpKKRrdg36K5bYBUqvtnMIqnQhJq/t8ZS1TzN3+IakoJfetGDvRnpZKY8w1uGz7j CfFsnhTJKZI3bJFYIW7nsR9803Vl6+WwwlPEV+DBKauzaA81lCHdXP1JwPLOOMYBg5 gS7RMMAgMD3UR9FwugwSPid9Gah0nLQFqjiL3qxtjUk2d/1lLjY4uSjwpm+Tgp8A0F mYcv5qp6/EyMg== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v3 3/4] irqchip: irq-mtk-cirq: Move register offsets to const array Date: Mon, 28 Nov 2022 10:22:16 +0100 Message-Id: <20221128092217.36552-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> References: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221128_012227_738478_D343310A X-CRM114-Status: GOOD ( 18.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In preparation to add support for new SoCs having a different register layout, add an enumeration that documents register offsets and move the definitions for the same to a u32 array; Selecting the right register offsets array is done by adding an of_device_id array containing all of the currently supported compatible strings pointing to the "v1" offsets array (as data): since no devicetree declares the `mediatek,mtk-cirq` compatible without a SoC-specific one, it wasn't necessary to provide any legacy fallback. Every usage of the aforemementioned definitions was changed to get a register address through a newly introduced `mtk_cirq_reg()` accessor. This change brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/irqchip/irq-mtk-cirq.c | 82 +++++++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 9bca0918078e..4776ed6492fb 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -15,14 +15,29 @@ #include #include -#define CIRQ_ACK 0x40 -#define CIRQ_MASK_SET 0xc0 -#define CIRQ_MASK_CLR 0x100 -#define CIRQ_SENS_SET 0x180 -#define CIRQ_SENS_CLR 0x1c0 -#define CIRQ_POL_SET 0x240 -#define CIRQ_POL_CLR 0x280 -#define CIRQ_CONTROL 0x300 +enum mtk_cirq_regoffs_index { + CIRQ_STA, + CIRQ_ACK, + CIRQ_MASK_SET, + CIRQ_MASK_CLR, + CIRQ_SENS_SET, + CIRQ_SENS_CLR, + CIRQ_POL_SET, + CIRQ_POL_CLR, + CIRQ_CONTROL +}; + +static const u32 mtk_cirq_regoffs_v1[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x40, + [CIRQ_MASK_SET] = 0xc0, + [CIRQ_MASK_CLR] = 0x100, + [CIRQ_SENS_SET] = 0x180, + [CIRQ_SENS_CLR] = 0x1c0, + [CIRQ_POL_SET] = 0x240, + [CIRQ_POL_CLR] = 0x280, + [CIRQ_CONTROL] = 0x300, +}; #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 @@ -32,18 +47,32 @@ struct mtk_cirq_chip_data { void __iomem *base; unsigned int ext_irq_start; unsigned int ext_irq_end; + const u32 *offsets; struct irq_domain *domain; }; static struct mtk_cirq_chip_data *cirq_data; -static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset) +static void __iomem *mtk_cirq_reg(struct mtk_cirq_chip_data *chip_data, + enum mtk_cirq_regoffs_index idx) +{ + return chip_data->base + chip_data->offsets[idx]; +} + +static void __iomem *mtk_cirq_irq_reg(struct mtk_cirq_chip_data *chip_data, + enum mtk_cirq_regoffs_index idx, + unsigned int cirq_num) +{ + return mtk_cirq_reg(chip_data, idx) + (cirq_num / 32) * 4; +} + +static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_regoffs_index idx) { struct mtk_cirq_chip_data *chip_data = data->chip_data; unsigned int cirq_num = data->hwirq; u32 mask = 1 << (cirq_num % 32); - writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); + writel_relaxed(mask, mtk_cirq_irq_reg(chip_data, idx, cirq_num)); } static void mtk_cirq_mask(struct irq_data *data) @@ -160,6 +189,7 @@ static const struct irq_domain_ops cirq_domain_ops = { #ifdef CONFIG_PM_SLEEP static int mtk_cirq_suspend(void) { + void __iomem *reg; u32 value, mask; unsigned int irq, hwirq_num; bool pending, masked; @@ -200,31 +230,34 @@ static int mtk_cirq_suspend(void) continue; } + reg = mtk_cirq_irq_reg(cirq_data, CIRQ_ACK, i); mask = 1 << (i % 32); - writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4); + writel_relaxed(mask, reg); } /* set edge_only mode, record edge-triggerd interrupts */ /* enable cirq */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); + reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL); + value = readl_relaxed(reg); value |= (CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, reg); return 0; } static void mtk_cirq_resume(void) { + void __iomem *reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL); u32 value; /* flush recorded interrupts, will send signals to parent controller */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); - writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); + value = readl_relaxed(reg); + writel_relaxed(value | CIRQ_FLUSH, reg); /* disable cirq */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); + value = readl_relaxed(reg); value &= ~(CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, reg); } static struct syscore_ops mtk_cirq_syscore_ops = { @@ -240,10 +273,18 @@ static void mtk_cirq_syscore_init(void) static inline void mtk_cirq_syscore_init(void) {} #endif +static const struct of_device_id mtk_cirq_of_match[] = { + { .compatible = "mediatek,mt2701-cirq", .data = &mtk_cirq_regoffs_v1 }, + { .compatible = "mediatek,mt8135-cirq", .data = &mtk_cirq_regoffs_v1 }, + { .compatible = "mediatek,mt8173-cirq", .data = &mtk_cirq_regoffs_v1 }, + { /* sentinel */ } +}; + static int __init mtk_cirq_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain, *domain_parent; + const struct of_device_id *match; unsigned int irq_num; int ret; @@ -274,6 +315,13 @@ static int __init mtk_cirq_of_init(struct device_node *node, if (ret) goto out_unmap; + match = of_match_node(mtk_cirq_of_match, node); + if (!match) { + ret = -ENODEV; + goto out_unmap; + } + cirq_data->offsets = match->data; + irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1; domain = irq_domain_add_hierarchy(domain_parent, 0, irq_num, node, From patchwork Mon Nov 28 09:22:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13057179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 390B5C4332F for ; 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Mon, 28 Nov 2022 09:23:37 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozaLM-000aks-77; Mon, 28 Nov 2022 09:22:29 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B950C6602ACE; Mon, 28 Nov 2022 09:22:24 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669627345; bh=l7ZG9TkqTdWaBRyskK4GczkMCb93J8ROfY3OVmuNmtg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oInpZUHXB7zOPYbBezlIZaWdf4PJgphAs20BHl/Gd0PfZj6uUQ/Xa3Zozwx68YaEV ny2z2PDfEjPaPXJkTuFd8/sVLlKe2qp+URst9xrhokjCaCEVGzAAAGt+erk8Ec1/R/ AuINwOOSWAZPl9KXcI/K7C+029TB3hyAmf2blEZhiqmnsZcap23pG8rCg38UKi7vOR uyzdZl1Lah7K5fb+f3WK8/kB5QBkoKAPO3IKfL4JZBGrsbUpvvB4Fia0/G/ghi1nWg ijPdoxi227Ax/6l2osmpAXJeLP92bmqHNuqgU8v9uWD0knIB7D2etLp6sRvisWqqu9 BhG1zWyDniF1g== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v3 4/4] irqchip: irq-mtk-cirq: Add support for System CIRQ on MT8192 Date: Mon, 28 Nov 2022 10:22:17 +0100 Message-Id: <20221128092217.36552-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> References: <20221128092217.36552-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221128_012228_431733_F0C4FCF1 X-CRM114-Status: GOOD ( 12.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On some SoCs the System CIRQ register layout is slightly different, as there are more registers per function and in some cases other differences later in the layout: this is seen on at least MT8192, but it's also valid for some other "contemporary" SoCs both for Chromebooks and for smartphones. Add the new "v2" register layout and use it if the compatible "mediatek,mt8192-cirq" is found. Signed-off-by: AngeloGioacchino Del Regno --- drivers/irqchip/irq-mtk-cirq.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 4776ed6492fb..76bc0283e3b9 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -39,6 +39,18 @@ static const u32 mtk_cirq_regoffs_v1[] = { [CIRQ_CONTROL] = 0x300, }; +static const u32 mtk_cirq_regoffs_v2[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x80, + [CIRQ_MASK_SET] = 0x180, + [CIRQ_MASK_CLR] = 0x200, + [CIRQ_SENS_SET] = 0x300, + [CIRQ_SENS_CLR] = 0x380, + [CIRQ_POL_SET] = 0x480, + [CIRQ_POL_CLR] = 0x500, + [CIRQ_CONTROL] = 0x600, +}; + #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 #define CIRQ_FLUSH 0x4 @@ -277,6 +289,7 @@ static const struct of_device_id mtk_cirq_of_match[] = { { .compatible = "mediatek,mt2701-cirq", .data = &mtk_cirq_regoffs_v1 }, { .compatible = "mediatek,mt8135-cirq", .data = &mtk_cirq_regoffs_v1 }, { .compatible = "mediatek,mt8173-cirq", .data = &mtk_cirq_regoffs_v1 }, + { .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regoffs_v2 }, { /* sentinel */ } };