From patchwork Mon Nov 28 16:14:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6E5BC4332F for ; Mon, 28 Nov 2022 16:14:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232561AbiK1QOp (ORCPT ); Mon, 28 Nov 2022 11:14:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232458AbiK1QOm (ORCPT ); Mon, 28 Nov 2022 11:14:42 -0500 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FA95BC1A for ; Mon, 28 Nov 2022 08:14:39 -0800 (PST) Received: by mail-pf1-x42e.google.com with SMTP id 9so10931805pfx.11 for ; Mon, 28 Nov 2022 08:14:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uRYTh3DpQ80LeZuXMwrf/BBG8HZ9tRsbrJY4o7VrTgs=; b=e1sLIlmJiHEANPq+U54eAHf3W4Nh0ttJp7jgZEIsl19CGXzTS5KTdXxdGnZVN95VOm +fAjj4XJIlDcHqh/lhmM2cKyH8S7xnJ6+xt9Xoc3zF1xyNHKqfxdMk+nr7kzDY35QfXJ sXCb4pmj60ibe5fwRoceD8yLBnBMr8xYrO8nlMwYwUpdcrzfzC0l9xsHZAejcc0BYvlG mSYPf0SqDvsN/0nnevlQ3Ndz/freshRH8YX0YTQfmVaUuKSzIelx2EoRE/8e5aVkTNKg oNksB5v1mkmr1c36OgBHsAdJ7725WTdLQuwabxSvQntLoGYMzYNq2l5CjNVxBGc/URnO hkUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uRYTh3DpQ80LeZuXMwrf/BBG8HZ9tRsbrJY4o7VrTgs=; b=EUUPHJa2cZgviu9wQJD7a3RmyZroMmudiNfilzl0QYlXI8HPyFgTTEJoXNgdi1vXW2 QFFx4rAucw1GMsBEjU+0cqo5YrLFHfFUkp9+YQwBBGdqQ5EKcC9/rHSCbHW9jIiss13B SArbBXQm7h+ONCh9vrvgpTcq1UO/DN/WnVlrP1cngTJFyjqMWz5g8UWPfWk5Gp6LtEbK xf9VMJuq2rGmbbzVK2YcSM2LZ6I3goM9cCPK6V3aHzCC+ttJXjKMrhVE9ZGx7oBCD8Jn Ngu5oDgYZRfugun46FLKalYBDcRT4UYM2qZXvLYeV6uVUhTRJkrEQKiy+anK1x48cNu9 olFQ== X-Gm-Message-State: ANoB5pkeqBrjrD4dvU/OgoIrqQiH82cKeZ1k/7ZDt7QdrQQiFDXZ44S7 QtDKmNXcVrs0hQU2gGkqVLCoqg== X-Google-Smtp-Source: AA0mqf6vP9RNcrwrw3LdbjlhLu/1pbC3GRsHHYss/6pjysHf8CgIMVkMyhfjH/kOyyBMFMTwZ7i6GQ== X-Received: by 2002:a63:5c0f:0:b0:470:8e8a:8e11 with SMTP id q15-20020a635c0f000000b004708e8a8e11mr28249402pgb.490.1669652078905; Mon, 28 Nov 2022 08:14:38 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:14:38 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config() Date: Mon, 28 Nov 2022 21:44:16 +0530 Message-Id: <20221128161424.608889-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The reg_val check in kvm_riscv_vcpu_set_reg_config() should only be done for isa config register. Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap") Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 17d5b3f8c2ee..982a3f5e7130 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; - /* This ONE REG interface is only defined for single letter extensions */ - if (fls(reg_val) >= RISCV_ISA_EXT_BASE) - return -EINVAL; - switch (reg_num) { case KVM_REG_RISCV_CONFIG_REG(isa): + /* + * This ONE REG interface is only defined for + * single letter extensions. + */ + if (fls(reg_val) >= RISCV_ISA_EXT_BASE) + return -EINVAL; + if (!vcpu->arch.ran_atleast_once) { /* Ignore the enable/disable request for certain extensions */ for (i = 0; i < RISCV_ISA_EXT_BASE; i++) { From patchwork Mon Nov 28 16:14:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCFADC433FE for ; Mon, 28 Nov 2022 16:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232623AbiK1QOq (ORCPT ); Mon, 28 Nov 2022 11:14:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231343AbiK1QOo (ORCPT ); Mon, 28 Nov 2022 11:14:44 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2D775F76 for ; Mon, 28 Nov 2022 08:14:43 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id hd14-20020a17090b458e00b0021909875bccso6631950pjb.1 for ; Mon, 28 Nov 2022 08:14:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S7x0oTKpsWp1eBMVcd2HvR7GLV5FrDh1MXNEuBtWibU=; b=GdZOldmSeoejY/4MEdz+TDxR+dEPbxAHB2nFoU0GWyxVoxQhUERCL+ZxaQCp1JkRK0 KhzMcM1nrUYd9KYVlLYnbC17ODw/dUbnRoGsYGB7y8iw08CP2OMlbZ3Tdu9Ag7j8rSoN QOUXNtJ7qcbTfXaMrwQ05eXW3JnpLDLGReoYynXAGlFdrLOjgPNGnBBxxoLDR2kwPy2B vD+qzpsMtpHy8F1xF7IG3RsR+xK1Ofxq2aXVIUqCjhZC8W0HpDEbv39lHq38zVTbxttZ rDWQtzL4WRfsED+a1UfPwP1DqwSyIvz7n72G4HGVBcspcAQCONIAtb+597M9SqvswxVw GmRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S7x0oTKpsWp1eBMVcd2HvR7GLV5FrDh1MXNEuBtWibU=; b=znyMOmI4iY+ZLyXum+hZwkSlTRjeqzR0l3B6dguif1T0YzLJ6CEy02dy/02K8M7CgG 6VQZ5th9PNb3Abb0ME4oEHB8h3kN+nZ6C8C7LoixYPql+hQZjWcXp1cW42j6vmfxuLr9 EwcDwRLIwUlAAG8aOCBvgf+yLK/zPbUxhp2uZb3ZeSC7XI33DsKd/jKGE5BBA0OozAwp js6P6tbVNVEYCNoVGGc29173nuEiZVPTnIjvUXH+HpaXSsjUEh4ICpGxwTyy9xaXRJ25 KivG44XODqMYZBD5HgL+vOkUu3YOIXlURGbVvPH0Hmy8v7YNkPTX0BVm8ymLJNI4F63G YfUg== X-Gm-Message-State: ANoB5pmRmoHkSpI9ULqJ+lXedbTV6y4hyBiBO9gGnYHKcBm1uHJnog4x xCvf7jOCEuYulx7L4tA6MR0+hg== X-Google-Smtp-Source: AA0mqf6a4nNMoI9Pp6ntgyunakgkDq9LNUMsEe3B51BBv8WT18Ot9XuFrO2+cmOg/sKUyAgU98S8SQ== X-Received: by 2002:a17:902:e886:b0:188:fb19:5f39 with SMTP id w6-20020a170902e88600b00188fb195f39mr36071752plg.21.1669652083071; Mon, 28 Nov 2022 08:14:43 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:14:42 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h Date: Mon, 28 Nov 2022 21:44:17 +0530 Message-Id: <20221128161424.608889-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c so let us remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_sbi_base.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c index 48f431091cdb..22b9126e2872 100644 --- a/arch/riscv/kvm/vcpu_sbi_base.c +++ b/arch/riscv/kvm/vcpu_sbi_base.c @@ -12,7 +12,6 @@ #include #include #include -#include #include static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, From patchwork Mon Nov 28 16:14:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C1C2C4332F for ; Mon, 28 Nov 2022 16:14:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232646AbiK1QO4 (ORCPT ); Mon, 28 Nov 2022 11:14:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232628AbiK1QOt (ORCPT ); Mon, 28 Nov 2022 11:14:49 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24AE522B1B for ; Mon, 28 Nov 2022 08:14:47 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso14533098pjt.0 for ; Mon, 28 Nov 2022 08:14:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7G5jJwuL5a/PRNCMiCmBEuKFRdtzizPv7c8U41zNCGg=; b=lrhiGfsIfOZZ6ZSUfqLx0rHc7pIdz7RcfT9qTrum1U7zEbSdCBeuIAffCX9Zp8ALzF QijgFUXavVRujVGmYAnKR1lA7+nl0rsXn93dezLwx1IfkYQzPwSBifIe80oHP5YPSNfc knJREFODU6y9oD6lGpxSJe1Z11OJ6f2uhBT+lDLN5hl+0oVV4AfxOOWa3kwft1/6s6lx aTDoavz9I3OMPVZ9lBIUtc5Ojne1pFtIbwfL9S3hme8LFnTWMBEPkv0ZxJO9IERhQXKD LrpdyEUC76y9Wc7Qr2xmmRCricyYcugnKM711T3L0zNHCOD60LH6Nf7/CUcYy2YCLjPs 1heg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7G5jJwuL5a/PRNCMiCmBEuKFRdtzizPv7c8U41zNCGg=; b=veTrDt1yciY58+k9sEK/OFH0pM1Q2LKBS1j5UNJ3mDRMpqfO0fxg1IZO7xx7brnKws iEfYZ1dn6ODI8S3aT7WJbWkQ+vwwk3+NBSNs18RI77D9ttei/jB1Y2+yUhHmtm+EZEAB Rtfj7Zu9lsW886OO9DhlaVIwopOxbFS9xS1ChkFCsokwWBrIdKWNZDaBKyMqIIQCBFrz kkuRHzwzf5SAv9mRB2swjFKGzBa5i3RjrMTRqBUe3pQdL3HqmuIqEbDUFJBactIFCd2f md7hjWHqDZ+QghfD6wjphjH5bJifurG1fGhyiJ5JfvReLySScCeCMymYe91+3gt5ImOX AwmQ== X-Gm-Message-State: ANoB5pnDHpDWGVzPivZqrUs6BPOiHu1EhCzSgfUiiMBLuxJR/GdSkoI5 mnu0/0M9zxsKE81TV2UpQ5h/hQ== X-Google-Smtp-Source: AA0mqf4SMYv7flwkn7gbi28fGz5UIiTwFY/3HWCe4s9O1TbUPNOiBEY7kreAHjSDAfxZZdMvCv4byA== X-Received: by 2002:a17:902:9307:b0:189:9284:2140 with SMTP id bc7-20020a170902930700b0018992842140mr2574760plb.111.1669652087098; Mon, 28 Nov 2022 08:14:47 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:14:46 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h Date: Mon, 28 Nov 2022 21:44:18 +0530 Message-Id: <20221128161424.608889-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We should include asm/csr.h only where required so let us remove redundant includes of this header. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 1 - arch/riscv/kvm/vcpu_sbi_base.c | 1 - arch/riscv/kvm/vcpu_sbi_hsm.c | 1 - arch/riscv/kvm/vcpu_sbi_replace.c | 1 - arch/riscv/kvm/vcpu_sbi_v01.c | 1 - 5 files changed, 5 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index dbbf43d52623..6502f9099965 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c index 22b9126e2872..0c806f61c629 100644 --- a/arch/riscv/kvm/vcpu_sbi_base.c +++ b/arch/riscv/kvm/vcpu_sbi_base.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c index 239dec0a628a..2e915cafd551 100644 --- a/arch/riscv/kvm/vcpu_sbi_hsm.c +++ b/arch/riscv/kvm/vcpu_sbi_hsm.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c index 4c034d8a606a..03a0198389f0 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c index 8a91a14e7139..489f225ee66d 100644 --- a/arch/riscv/kvm/vcpu_sbi_v01.c +++ b/arch/riscv/kvm/vcpu_sbi_v01.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include From patchwork Mon Nov 28 16:14:19 2022 Content-Type: text/plain; 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Mon, 28 Nov 2022 08:14:51 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:14:50 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg() Date: Mon, 28 Nov 2022 21:44:19 +0530 Message-Id: <20221128161424.608889-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions because the else-if ladder is quite big now. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 982a3f5e7130..68c86f632d37 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG) + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { + case KVM_REG_RISCV_CONFIG: return kvm_riscv_vcpu_set_reg_config(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE) + case KVM_REG_RISCV_CORE: return kvm_riscv_vcpu_set_reg_core(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) + case KVM_REG_RISCV_CSR: return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER) + case KVM_REG_RISCV_TIMER: return kvm_riscv_vcpu_set_reg_timer(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + case KVM_REG_RISCV_FP_F: return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_F); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + case KVM_REG_RISCV_FP_D: return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT) + case KVM_REG_RISCV_ISA_EXT: return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); + default: + break; + } return -EINVAL; } @@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG) + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { + case KVM_REG_RISCV_CONFIG: return kvm_riscv_vcpu_get_reg_config(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE) + case KVM_REG_RISCV_CORE: return kvm_riscv_vcpu_get_reg_core(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) + case KVM_REG_RISCV_CSR: return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER) + case KVM_REG_RISCV_TIMER: return kvm_riscv_vcpu_get_reg_timer(vcpu, reg); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + case KVM_REG_RISCV_FP_F: return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_F); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + case KVM_REG_RISCV_FP_D: return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT) + case KVM_REG_RISCV_ISA_EXT: return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); + default: + break; + } return -EINVAL; } From patchwork Mon Nov 28 16:14:20 2022 Content-Type: text/plain; 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Mon, 28 Nov 2022 08:14:55 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:14:55 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h Date: Mon, 28 Nov 2022 21:44:20 +0530 Message-Id: <20221128161424.608889-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct and functions in asm/kvm_vcpu_sbi.h. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 10 ++-------- arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 ++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 6502f9099965..91c74b09a970 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #define KVM_MAX_VCPUS 1024 @@ -94,10 +95,6 @@ struct kvm_arch { struct kvm_guest_timer timer; }; -struct kvm_sbi_context { - int return_handled; -}; - struct kvm_cpu_trap { unsigned long sepc; unsigned long scause; @@ -216,7 +213,7 @@ struct kvm_vcpu_arch { struct kvm_csr_decode csr_decode; /* SBI context */ - struct kvm_sbi_context sbi_context; + struct kvm_vcpu_sbi_context sbi_context; /* Cache pages needed to program page tables with spinlock held */ struct kvm_mmu_memory_cache mmu_page_cache; @@ -326,7 +323,4 @@ bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask); void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); -int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); -int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); - #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index d4e3e600beef..f79478a85d2d 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -14,6 +14,10 @@ #define KVM_SBI_VERSION_MAJOR 1 #define KVM_SBI_VERSION_MINOR 0 +struct kvm_vcpu_sbi_context { + int return_handled; +}; + struct kvm_vcpu_sbi_extension { unsigned long extid_start; unsigned long extid_end; @@ -31,7 +35,9 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu, struct kvm_run *run, u32 type, u64 flags); +int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid); +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); #ifdef CONFIG_RISCV_SBI_V01 extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01; From patchwork Mon Nov 28 16:14:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 219ADC433FE for ; Mon, 28 Nov 2022 16:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232746AbiK1QPX (ORCPT ); Mon, 28 Nov 2022 11:15:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232691AbiK1QPH (ORCPT ); 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Mon, 28 Nov 2022 08:14:59 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends Date: Mon, 28 Nov 2022 21:44:21 +0530 Message-Id: <20221128161424.608889-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid() can be used by KVM module so let us export these functions. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones Acked-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- arch/riscv/kernel/sbi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 775d3322b422..5c87db8fdff2 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); } +EXPORT_SYMBOL_GPL(sbi_get_mvendorid); long sbi_get_marchid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID); } +EXPORT_SYMBOL_GPL(sbi_get_marchid); long sbi_get_mimpid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID); } +EXPORT_SYMBOL_GPL(sbi_get_mimpid); static void sbi_send_cpumask_ipi(const struct cpumask *target) { From patchwork Mon Nov 28 16:14:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C07DEC433FE for ; Mon, 28 Nov 2022 16:15:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232749AbiK1QP1 (ORCPT ); Mon, 28 Nov 2022 11:15:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232700AbiK1QPK (ORCPT ); Mon, 28 Nov 2022 11:15:10 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6495E25282 for ; Mon, 28 Nov 2022 08:15:04 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id io19so10612938plb.8 for ; Mon, 28 Nov 2022 08:15:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ji6gUrAoWYT3XHk2lFOFtFs8PLEDbbIx9YYSf+S6VSU=; b=AjDuDNL8yAH4u64rbRauvAnfDwFYGSkUwRQHNT35gUX2qBC27sLneXYjLxoHThqaMD 2XKsXAk0kyRCA8MF5ECg+7l/bjOsfAhXTdcnUzQKToxbZCG0Q2GZmXEWxCxO4g2snJLE foNXnRy9leX4WRty4LXz7pmeQJLWIQ1A8NVw+F5ctpUmMQ32/SLtKOmvjs1GkJ1qwusW lUuvExjF232MPQ4MgVW27YlIZHN8VjhclqVGFcw/FodzbFb00xTqWaAgx20VQEApxtLr oLMdXe0Q9PX7jsop2JH5Pb0TXuCxBMNa4l83br5MLpo/XVe6m/rYKBz4/sQHPpIOH9uW tAaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ji6gUrAoWYT3XHk2lFOFtFs8PLEDbbIx9YYSf+S6VSU=; b=rWfr/QMY60ONMopDmHKbIZZKRieZAn6Lhwwjtj6rIFfSdmAn8Smy4FeSNd4bA73Gn3 S5lrQzQGJNxuyGtbMrs+ltlaDSVvP8MSwDeNOgqKcw7+sKH6BqQxCTewFhuI4zYa+x76 xg4YNEFdVXQBXMRDekBmgBOgo8le9+xdM4gEqIOk2XfiEr7AEWtSEwYjgPpfoZw4YNMo UAtoC5J59Pd6d1+x2DoJuyfU2arbhSASUgBV2JWRbXDwz4w5oLCM/9DFAcz5TaRTifJo THEP5hMgpPfrdTay5nrdGU1UsBREo/m1ur9QSKuDmVhEolgiLhlLEEmCYbuS0ZpluQGc b+Ew== X-Gm-Message-State: ANoB5pnLWssaYr0lm7KV4OpMPoe1aXeeBEjSREPLyXLw1aVcn5EQkGS0 x8TAtrGkqgyTHm3s88raErKDxbZfW56sxQ== X-Google-Smtp-Source: AA0mqf7yAshre1MYiIFD0k1ifqLxcshH2Yv8NLWThlH1BDV1OaAOo4j6oo9TJuEJSkDguwxkCNaAag== X-Received: by 2002:a17:902:c702:b0:189:4bde:53c1 with SMTP id p2-20020a170902c70200b001894bde53c1mr25593754plp.1.1669652103621; Mon, 28 Nov 2022 08:15:03 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:15:03 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU Date: Mon, 28 Nov 2022 21:44:22 +0530 Message-Id: <20221128161424.608889-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We should save VCPU mvendorid, marchid, and mimpid at the time of creating VCPU so that we don't have to do host SBI call every time Guest/VM ask for these details. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 5 +++++ arch/riscv/kvm/vcpu.c | 6 ++++++ arch/riscv/kvm/vcpu_sbi_base.c | 11 +++++------ 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 91c74b09a970..93f43a3e7886 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -165,6 +165,11 @@ struct kvm_vcpu_arch { /* ISA feature bits (similar to MISA) */ DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX); + /* Vendor, Arch, and Implementation details */ + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; + /* SSCRATCH, STVEC, and SCOUNTEREN of Host */ unsigned long host_sscratch; unsigned long host_stvec; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 68c86f632d37..312a8a926867 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -21,6 +21,7 @@ #include #include #include +#include const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { KVM_GENERIC_VCPU_STATS(), @@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) set_bit(host_isa, vcpu->arch.isa); } + /* Setup vendor, arch, and implementation details */ + vcpu->arch.mvendorid = sbi_get_mvendorid(); + vcpu->arch.marchid = sbi_get_marchid(); + vcpu->arch.mimpid = sbi_get_mimpid(); + /* Setup VCPU hfence queue */ spin_lock_init(&vcpu->arch.hfence_lock); diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c index 0c806f61c629..5d65c634d301 100644 --- a/arch/riscv/kvm/vcpu_sbi_base.c +++ b/arch/riscv/kvm/vcpu_sbi_base.c @@ -19,7 +19,6 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, { int ret = 0; struct kvm_cpu_context *cp = &vcpu->arch.guest_context; - struct sbiret ecall_ret; switch (cp->a6) { case SBI_EXT_BASE_GET_SPEC_VERSION: @@ -48,13 +47,13 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0; break; case SBI_EXT_BASE_GET_MVENDORID: + *out_val = vcpu->arch.mvendorid; + break; case SBI_EXT_BASE_GET_MARCHID: + *out_val = vcpu->arch.marchid; + break; case SBI_EXT_BASE_GET_MIMPID: - ecall_ret = sbi_ecall(SBI_EXT_BASE, cp->a6, 0, 0, 0, 0, 0, 0); - if (!ecall_ret.error) - *out_val = ecall_ret.value; - /*TODO: We are unnecessarily converting the error twice */ - ret = sbi_err_map_linux_errno(ecall_ret.error); + *out_val = vcpu->arch.mimpid; break; default: ret = -EOPNOTSUPP; From patchwork Mon Nov 28 16:14:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA8C7C4332F for ; Mon, 28 Nov 2022 16:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232766AbiK1QPl (ORCPT ); Mon, 28 Nov 2022 11:15:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232681AbiK1QPQ (ORCPT ); Mon, 28 Nov 2022 11:15:16 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC8A124BDC for ; Mon, 28 Nov 2022 08:15:08 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id j12so10617143plj.5 for ; Mon, 28 Nov 2022 08:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F1jSlqGdECL73YnDzNqagg9psRJkFm1roQJKa2djZKM=; b=L6a6o+4S9rBnv86Payvu0dzLCpF3lYvbi9NgJKV1CXCbWK/dyxbBu12WF2ZSV1keFB Be5L4CQlc7zjqpjF6lzrgrLKhGpxAdOBzvySlGKafYVqSgKttpVsj1iLemVo1nzzntgN adrM1WO3AfzgiuPqku8d6jS/TcuLI6wFqlCiL2toC0f0oEceRHbBRVpTlDsES0hjt864 fHMJji5dsKGR0hIfMjMzZqqaTDbprry/wE7FcXdxWIZLl63ov42CGsb46Ec2kk6xA0wh 211lCV2nNEEp/sQsDC2VVRnSPgg4aUVEnoUBcPgJcRATQeaiDIrVZv2n+d5zzrYJVl9H Qi/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F1jSlqGdECL73YnDzNqagg9psRJkFm1roQJKa2djZKM=; b=RtEIznJDvMiRiZn919cwfZp6EpY0u1ixuHOQ6SZnxrtpeOUCuIB+RhCTFq5LhqUip8 QCqKtFg2/3PtnSY/6eoqRTSxKz18OdUJtGcFAbIq1+ZT0fUuu/k/Ctj5GBiaeNDkiq22 zY/UYYo81YMwDnPlqBTA7dm60N0GdeSyo+k3phEpHoN8uijwBmHOnKFN7S6M27tOwZCY rQDxBEFUHbq/4AyCiDhB6/SrR8QpUDETV4IZmDwLs0kR5xEWlfbmFNM/aqdcpCI1ctb3 7DoCdUHU1zABc5v3ai4krd7C/PyLP0GF86JeahQtza9Pc9TA+e1hqhe596M/avqtTUdN /84g== X-Gm-Message-State: ANoB5pkF5cpIGZuyDFMQjKXPjnV1q7AWceOrJEKWv979Y9Iig6I1rAb3 l7ueb+0XEx+vgEHo21yEX8X3zA== X-Google-Smtp-Source: AA0mqf44Bf/aZc5leADbIBCjjLqyV0qnD7yKtTFR/swOhVKlth1mxLaJYewfn3xuWt7GGhaAU1AJZg== X-Received: by 2002:a17:90a:5801:b0:218:90b5:d1f2 with SMTP id h1-20020a17090a580100b0021890b5d1f2mr46721362pji.142.1669652108111; Mon, 28 Nov 2022 08:15:08 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.0]) by smtp.gmail.com with ESMTPSA id k145-20020a628497000000b0056246403534sm8210805pfd.88.2022.11.28.08.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 08:15:07 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid Date: Mon, 28 Nov 2022 21:44:23 +0530 Message-Id: <20221128161424.608889-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid so that KVM user-space can change this details to support migration across heterogeneous hosts. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 3 +++ arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 8985ff234c01..92af6f3f057c 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -49,6 +49,9 @@ struct kvm_sregs { struct kvm_riscv_config { unsigned long isa; unsigned long zicbom_block_size; + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; }; /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 312a8a926867..7c08567097f0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, return -EINVAL; reg_val = riscv_cbom_block_size; break; + case KVM_REG_RISCV_CONFIG_REG(mvendorid): + reg_val = vcpu->arch.mvendorid; + break; + case KVM_REG_RISCV_CONFIG_REG(marchid): + reg_val = vcpu->arch.marchid; + break; + case KVM_REG_RISCV_CONFIG_REG(mimpid): + reg_val = vcpu->arch.mimpid; + break; default: return -EINVAL; } @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, break; case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): return -EOPNOTSUPP; + case KVM_REG_RISCV_CONFIG_REG(mvendorid): + if (!vcpu->arch.ran_atleast_once) + vcpu->arch.mvendorid = reg_val; + else + return -EBUSY; + break; + case KVM_REG_RISCV_CONFIG_REG(marchid): + if (!vcpu->arch.ran_atleast_once) + vcpu->arch.marchid = reg_val; + else + return -EBUSY; + break; + case KVM_REG_RISCV_CONFIG_REG(mimpid): + if (!vcpu->arch.ran_atleast_once) + vcpu->arch.mimpid = reg_val; + else + return -EBUSY; + break; default: return -EINVAL; } From patchwork Mon Nov 28 16:14:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13057768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D87BAC433FE for ; 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Mon, 28 Nov 2022 08:15:11 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions Date: Mon, 28 Nov 2022 21:44:24 +0530 Message-Id: <20221128161424.608889-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128161424.608889-1-apatel@ventanamicro.com> References: <20221128161424.608889-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We add ONE_REG interface to enable/disable SBI extensions (just like the ONE_REG interface for ISA extensions). This allows KVM user-space to decide the set of SBI extension enabled for a Guest and by default all SBI extensions are enabled. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 8 +- arch/riscv/include/uapi/asm/kvm.h | 19 ++++ arch/riscv/kvm/vcpu.c | 2 + arch/riscv/kvm/vcpu_sbi.c | 145 +++++++++++++++++++++++--- arch/riscv/kvm/vcpu_sbi_base.c | 2 +- 5 files changed, 158 insertions(+), 18 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index f79478a85d2d..baa342dadf95 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -16,6 +16,7 @@ struct kvm_vcpu_sbi_context { int return_handled; + bool extension_disabled[KVM_RISCV_SBI_EXT_MAX]; }; struct kvm_vcpu_sbi_extension { @@ -36,7 +37,12 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu, struct kvm_run *run, u32 type, u64 flags); int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); -const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid); +int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg); +int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg); +const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( + struct kvm_vcpu *vcpu, unsigned long extid); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); #ifdef CONFIG_RISCV_SBI_V01 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 92af6f3f057c..71992ff1f9dd 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -108,6 +108,22 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_MAX, }; +/* + * SBI extension IDs specific to KVM. This is not the same as the SBI + * extension IDs defined by the RISC-V SBI specification. + */ +enum KVM_RISCV_SBI_EXT_ID { + KVM_RISCV_SBI_EXT_V01 = 0, + KVM_RISCV_SBI_EXT_TIME, + KVM_RISCV_SBI_EXT_IPI, + KVM_RISCV_SBI_EXT_RFENCE, + KVM_RISCV_SBI_EXT_SRST, + KVM_RISCV_SBI_EXT_HSM, + KVM_RISCV_SBI_EXT_EXPERIMENTAL, + KVM_RISCV_SBI_EXT_VENDOR, + KVM_RISCV_SBI_EXT_MAX, +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -152,6 +168,9 @@ enum KVM_RISCV_ISA_EXT_ID { /* ISA Extension registers are mapped as type 7 */ #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) +/* SBI extension registers are mapped as type 8 */ +#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567097f0..2260adaf2de8 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -594,6 +594,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, KVM_REG_RISCV_FP_D); case KVM_REG_RISCV_ISA_EXT: return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); + case KVM_REG_RISCV_SBI_EXT: + return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg); default: break; } diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index f96991d230bf..0abb44f8f4d1 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -40,16 +40,48 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = { }; #endif -static const struct kvm_vcpu_sbi_extension *sbi_ext[] = { - &vcpu_sbi_ext_v01, - &vcpu_sbi_ext_base, - &vcpu_sbi_ext_time, - &vcpu_sbi_ext_ipi, - &vcpu_sbi_ext_rfence, - &vcpu_sbi_ext_srst, - &vcpu_sbi_ext_hsm, - &vcpu_sbi_ext_experimental, - &vcpu_sbi_ext_vendor, +struct kvm_riscv_sbi_extension_entry { + enum KVM_RISCV_SBI_EXT_ID dis_idx; + const struct kvm_vcpu_sbi_extension *ext_ptr; +}; + +static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = { + { + .dis_idx = KVM_RISCV_SBI_EXT_V01, + .ext_ptr = &vcpu_sbi_ext_v01, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_MAX, /* Can't be disabled */ + .ext_ptr = &vcpu_sbi_ext_base, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_TIME, + .ext_ptr = &vcpu_sbi_ext_time, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_IPI, + .ext_ptr = &vcpu_sbi_ext_ipi, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_RFENCE, + .ext_ptr = &vcpu_sbi_ext_rfence, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_SRST, + .ext_ptr = &vcpu_sbi_ext_srst, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_HSM, + .ext_ptr = &vcpu_sbi_ext_hsm, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL, + .ext_ptr = &vcpu_sbi_ext_experimental, + }, + { + .dis_idx = KVM_RISCV_SBI_EXT_VENDOR, + .ext_ptr = &vcpu_sbi_ext_vendor, + }, }; void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run) @@ -108,14 +140,95 @@ int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run) return 0; } -const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid) +int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_SBI_EXT); + unsigned long i, reg_val; + const struct kvm_riscv_sbi_extension_entry *sext = NULL; + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + if (reg_num >= KVM_RISCV_SBI_EXT_MAX || + (reg_val != 1 && reg_val != 0)) + return -EINVAL; + + if (vcpu->arch.ran_atleast_once) + return -EBUSY; + + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { + if (sbi_ext[i].dis_idx == reg_num) { + sext = &sbi_ext[i]; + break; + } + } + if (!sext) + return -ENOENT; + + scontext->extension_disabled[sext->dis_idx] = !reg_val; + + return 0; +} + +int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_SBI_EXT); + unsigned long i, reg_val; + const struct kvm_riscv_sbi_extension_entry *sext = NULL; + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + if (reg_num >= KVM_RISCV_SBI_EXT_MAX) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { + if (sbi_ext[i].dis_idx == reg_num) { + sext = &sbi_ext[i]; + break; + } + } + if (!sext) + return -ENOENT; + + reg_val = !scontext->extension_disabled[sext->dis_idx]; + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( + struct kvm_vcpu *vcpu, unsigned long extid) { - int i = 0; + int i; + const struct kvm_riscv_sbi_extension_entry *sext; + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { - if (sbi_ext[i]->extid_start <= extid && - sbi_ext[i]->extid_end >= extid) - return sbi_ext[i]; + sext = &sbi_ext[i]; + if (sext->ext_ptr->extid_start <= extid && + sext->ext_ptr->extid_end >= extid) { + if (sext->dis_idx < KVM_RISCV_SBI_EXT_MAX && + scontext->extension_disabled[sext->dis_idx]) + return NULL; + return sbi_ext[i].ext_ptr; + } } return NULL; @@ -132,7 +245,7 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) unsigned long out_val = 0; bool ext_is_v01 = false; - sbi_ext = kvm_vcpu_sbi_find_ext(cp->a7); + sbi_ext = kvm_vcpu_sbi_find_ext(vcpu, cp->a7); if (sbi_ext && sbi_ext->handler) { #ifdef CONFIG_RISCV_SBI_V01 if (cp->a7 >= SBI_EXT_0_1_SET_TIMER && diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c index 5d65c634d301..a51ed0c615bf 100644 --- a/arch/riscv/kvm/vcpu_sbi_base.c +++ b/arch/riscv/kvm/vcpu_sbi_base.c @@ -44,7 +44,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, kvm_riscv_vcpu_sbi_forward(vcpu, run); *exit = true; } else - *out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0; + *out_val = kvm_vcpu_sbi_find_ext(vcpu, cp->a0) ? 1 : 0; break; case SBI_EXT_BASE_GET_MVENDORID: *out_val = vcpu->arch.mvendorid;