From patchwork Tue Nov 29 14:47:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13058686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EA6AC4321E for ; Tue, 29 Nov 2022 14:51:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zdk5Sc5Dd+pcexeGsu5hpSfsAiNbrl4nlPMrapz6gUo=; b=pz3Slq7BcSJ/NV HXtp6iheMtlXJdZ4GQAK+xXPMKqUvXIJhqzRE6YtLXu1Jp8RTWeoKgB+Kmel7NzO/vLn4VZVBl5Oq b4Nq78nc7O2fMwPf+8dQnc1pC0MN/4x1tFuOSq91dgB0AbQOFOxzTWv4g0qY9TuhGUvS4/YctWGzq lkwMFBNroNU9UE2/jYM43l7NxrgpQznBd2F2KR/EsOGmkbvWWxCy0fvEf1q2l7BllwdfCLa02OtRb Huw/GYXslk2zhmvRnPtQ8dRV0o45UCqzwfgbhsyS5v1IRe7TiurpZP+36oK4DZ77AefY1bGsclSVe bZgHPhlF387dw383nb5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01xI-009S2e-69; Tue, 29 Nov 2022 14:51:28 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01xB-009Rx4-7U for linux-riscv@lists.infradead.org; Tue, 29 Nov 2022 14:51:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669733481; x=1701269481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CX12l/BYcHckW0nxt5dW6uGaSf9bcCVSRsIUm2MrbaY=; b=CDp2w59xCD6LSvrcuyn7jgU/XJisFsNp5OYHfHt+XUN/Lh9Huk9pLsyn VIbg9WvVX0Hxwo+F6tu6LcTXcLboiXEAN51U57s44wmYPpE2iFv7P9Wvr HseJCXf59//A9EEjuRePeTAPz4m96xS/LqhchaZ0fHIpWL9wJvjuD9/ue 7b6fTi9eBq3Hk5YbrjpdXOqQECxRUOlW1ebPA6nLiZvdoGnVkwfV95qHa M7O535gVCL+k2EtDq/OqichGiAErpS6j2yS81UaPgoLUANxvk81T7u69B aUCEs7jkbmo0NI4UMqIgC5Gb9KcWMO8yRZechuso6TW9KJBjk9fYHAHe7 A==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="190983230" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:51:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:51:15 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:51:13 -0700 From: Conor Dooley To: CC: Conor Dooley , , , , , , , , , , , Subject: [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Date: Tue, 29 Nov 2022 14:47:42 +0000 Message-ID: <20221129144742.2935581-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_065121_364046_15B7D404 X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org While the list of rules may have been accurate when created, it now lacks some clarity in the face of isa-manual updates. Specifically: - there is no mention here of a distinction between regular 'Z' extensions which are "Additional Standard Extensions" and "Zxm" extensions which are "Standard Machine-Level Extensions" - there is also no explicit mention of where either should be sorted in the list - underscores are only required between two *multi-letter* extensions but the list of rules implies that this is required between a multi-letter extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a valid string Attempt to clean up the list of rules, by adding information on the above & sprinkling in some white space for readability. Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 852ecccd8920..5e42c92a8456 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); .uprop = #UPROP, \ .isa_ext_id = EXTID, \ } + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : - * 1. All extensions should be separated from other multi-letter extensions - * by an underscore. + * + * 1. All multi-letter extensions should be separated from other multi-letter + * extensions by an underscore. + * * 2. The first letter following the 'Z' conventionally indicates the most * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered first - * by category, then alphabetically within a category. + * 'Z' extensions should be sorted after single-letter extensions and before + * any higher-privileged extensions. + * If multiple 'Z' extensions are named, they should be ordered first by + * category, then alphabetically within a category. + * * 3. Standard supervisor-level extensions (starts with 'S') should be * listed after standard unprivileged extensions. If multiple * supervisor-level extensions are listed, they should be ordered * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after all + * + * 4 Standard machine-level extensions (starts with 'Zxm') should be + * listed after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they should be ordered + * alphabetically. + * + * 5. Non-standard extensions (starts with 'X') must be listed after all * standard extensions. They must be separated from other multi-letter * extensions by an underscore. */ From patchwork Tue Nov 29 14:47:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13058687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5C24C4321E for ; Tue, 29 Nov 2022 14:51:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pvoZDCcmkxHYGAiGrhC80nojGiSO9EMN1VCl1Qx8mmQ=; b=gPuZcGLoJUBhu7 QBg3C/J232//Y/KsQ7vW2MN52zu/bwXBjrJo+UHeemKthou+Q2W7FBhnaqCva/y1t9wunBIurdvWj bJpzj7pYnVrQdX9G0hLQHQvoi0nfjIrdE69H8uBZwFacYOcSgE+c0SzuvDVIUGYUOf17Hh4sjn+8w vZDlmitT7eqhe6NGu8DbATNB6+4p33VMb9ki+VGA1BhDS6LT461s0lht85W24trNKKSQh6kRCG8RT Y3cF9dlVm7XI3dFLFlJK10jQRFw3DL/WCTobtw+7oSp8M+tTHGp1scP1G1scAOhAWChPemgVLxSwt grNEUnWrAYCkQOtEkx7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01xM-009S5a-9a; Tue, 29 Nov 2022 14:51:32 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01xI-009S2b-AC for linux-riscv@lists.infradead.org; Tue, 29 Nov 2022 14:51:29 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669733489; x=1701269489; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ag9tRag2tCMnYNZ7PXKJUn99ayga3IWCVtRNMuIqp7c=; b=TaSlfA5E7ZXZuODOKRHGjddeteuBxpjVZA/wRfQ+tBbL1v6ByiDUeb0B zp66LmEPE1hX2bdTNzNHnHRKKaXk8DDV6K4/i8mCk2NVvZ6tVjxsV6If4 5M3OZQP6Wn+vgMPnahajU7lh9rMJEe7TezxAL26oq9p4QDWFojFBycVaj bjHGj7FI08ry5QbcVk91T7ILemHCAEmmKPJxEzFyGo1ygdjwjfQD+gOXQ 98LtbwVmCpohQDISLJ1Q9cP5Uvvmy8EBG7CfgdQKRI85y/DnVQ2iyFVIE qLZjfax/1+VEjDVUZnmEVUl1bIxEJhpbLHJho+MZxEhCMF/SYMPnMbhZw Q==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="185697717" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:51:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:51:18 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:51:16 -0700 From: Conor Dooley To: CC: Conor Dooley , , , , , , , , , , , Subject: [RFC 2/2] RISC-V: resort all extensions in "canonical" order Date: Tue, 29 Nov 2022 14:47:43 +0000 Message-ID: <20221129144742.2935581-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_065128_451561_A5040FD5 X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Per the comment in cpu.c, re-sort all lists/tables/enums/whatever in arch/riscv (apart from KVM) in the current edition of what the isa manual considers to be "canonical" order. None of this is in uapi, so we are free to re-order it? I'm never sure when it comes to hwcap... Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 4 ++-- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..d7d5f27619ee 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,12 +53,12 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZICBOM = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ZIHINTPAUSE, + RISCV_ISA_EXT_SSCOFPMF, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 5e42c92a8456..1d0fa0ebf6a8 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -150,12 +150,12 @@ device_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..d3df72c4b94f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,12 +199,12 @@ void __init riscv_fill_hwcap(void) this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); } else { - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); } #undef SET_ISA_EXT_MAP }