From patchwork Wed Nov 30 13:09:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25D57C4708A for ; Wed, 30 Nov 2022 13:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235552AbiK3NKI (ORCPT ); Wed, 30 Nov 2022 08:10:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235422AbiK3NKH (ORCPT ); Wed, 30 Nov 2022 08:10:07 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26A7C6C72A for ; Wed, 30 Nov 2022 05:10:06 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id c1so26848805lfi.7 for ; Wed, 30 Nov 2022 05:10:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UA5cLJUoGQO+gLaplXIgTCRJk4ThzDRj/ruKwPcYtJI=; b=W5A0G2iCAs2ROM7sP911zHqen7UJJ0p3I3gWWWfMM9m8DPJjKBcvuBVnCmTD8zKYDW ASNU31yagmnIjcIKt0V8kD2lXv9PVfTwGmcmi3SdTF/GiSowaU8PObO7Te9Isaauk4j+ XgB7XitvNWcvE3XV0XPbF1jYtMDknm0qo9uvqQworVAxu7QOB9zg4Goccw3zzQ1piRoW UDNen5vLq/2R4hp4Ftn97spEkpdOzC3e4KDAquLM4vSb+tmemYsyN0kkN65NRsBjOiA3 haCQb/BZhUKwOMDVLpZmjCN+jJUM+4pWkhIBrylpX027Td675Nn1fUQs7jrCtvWHxCtr hpFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UA5cLJUoGQO+gLaplXIgTCRJk4ThzDRj/ruKwPcYtJI=; b=X6rN2zY/cEPYf0knbDiTrkGXoyR3oZ9e9lX1eV8jJPPDrg5v1enrThIC1wpTU3KUNI 3hxgO3I1SMYQyJqJwNdp+holDVVmsMaootfgI5hzezQ2rXsvFJ5pKquzhha47bCM0iZ6 Ji9QvN2wloQSEc9AWlwoBj2dYo93RxLWRu/eg85NcGf0fly/A4tTsnuMpyYvj4N/nVGt qW39uexAKKRPruNz011r4xZvgmsCpje0x0P6zNi44Yfo9sSLdFKuP+AwzBXJq5IjQsNK W1E7Kig3jTw55PrUEVeQKS26ESfumX/kzfp/Bn/HfP8oyyuUsKX2OCkfCotltJ/DOses PCfQ== X-Gm-Message-State: ANoB5pnlINZi6sBZBSSK2xIMTpeCMv4ONnhNWexokqTEEh+6xAYnGXaB OuSq1GESjDCQGA1g0OtRLSrYoA== X-Google-Smtp-Source: AA0mqf4dJ4Ezw2WYWxbwjaUWzrJ3NjD1svr5ShAnv4kM66kEPuYea3TGMsduC9TsGohXt3gxkPcN5A== X-Received: by 2002:a05:6512:3992:b0:4ae:5dc5:82c5 with SMTP id j18-20020a056512399200b004ae5dc582c5mr23211363lfu.2.1669813804453; Wed, 30 Nov 2022 05:10:04 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 1/8] clk: qcom: rpmh: group clock definitions together Date: Wed, 30 Nov 2022 15:09:54 +0200 Message-Id: <20221130131001.20912-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparations to the further changes, group all RPMH clock definitions to ease review. Group the clocks by their type to make similar/duplicate clocks stand out. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 55 ++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 1da45a6e2f29..f13c9bd610d0 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -342,19 +342,45 @@ static const struct clk_ops clk_rpmh_bcm_ops = { }; /* Resource name must match resource id present in cmd-db */ +DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); +DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); +DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); + +DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); +DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); + +DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); + +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4); +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); + DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); + DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); + +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); + DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); +DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); +DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); +DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); +DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, @@ -398,11 +424,6 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), }; -DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); -DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); -DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); -DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); - static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, @@ -478,8 +499,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = { .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), }; -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); - static struct clk_hw *sm8250_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, @@ -500,12 +519,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), }; -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); -DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); -DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); - static struct clk_hw *sm8350_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, @@ -533,8 +546,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), }; -DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); - static struct clk_hw *sc8280xp_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, @@ -550,12 +561,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), }; -/* Resource name must match resource id present in cmd-db */ -DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); - -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); - static struct clk_hw *sm8450_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, @@ -600,10 +605,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = { .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), }; -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); -DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); - static struct clk_hw *sm6350_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, @@ -620,8 +621,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), }; -DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); - static struct clk_hw *sdx65_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, @@ -644,8 +643,6 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = { .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), }; -DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); - static struct clk_hw *qdu1000_rpmh_clocks[] = { [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw, From patchwork Wed Nov 30 13:09:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC596C4708B for ; Wed, 30 Nov 2022 13:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235437AbiK3NKI (ORCPT ); Wed, 30 Nov 2022 08:10:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234022AbiK3NKI (ORCPT ); Wed, 30 Nov 2022 08:10:08 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CBB46D4A4 for ; Wed, 30 Nov 2022 05:10:07 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id j16so26828974lfe.12 for ; Wed, 30 Nov 2022 05:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+gzH+UjDtpSN2TBOm25RZHMYv/xwDs6O2i9cPC2mgCU=; b=eY+/7qTN/ke0IJIRhLaQdTHqKlwokLfTeNURGyoiYWAUKm/VbRcFcQ2iqtm6t3krpm emlfdziAbzOacTaUtTt8Otvv4E9kr496/H9v+5MwNHeOSgSaruqP3wqH1gIJqJRw4Uzx l6oKdntjVOMabZ0KIQJvz6t0Hv9H2/6krIbmwNkHttv7Cw5+NFHTN5hIWfQ0J6MDGHtj 7ZCrfzZmGxmMHJVB69L/kx+77y84dE8u4ONrv/5UquC5eyZ6xUjZJOO9QN/aYgLDCZiJ a8C5kb5LtmOz9tglDH9xW3Rp/5YU4V/GHybjvsw6OYD4z8KIDKdRDecw6J/o1d5rhVOs M9Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+gzH+UjDtpSN2TBOm25RZHMYv/xwDs6O2i9cPC2mgCU=; b=xbbrfULNK9hvTMVvkFL+zXv6617m8oV8u8O6g1VDfIk8DQGAjMqaumdvWxzg9oUnY9 Lw8We5mCf8X4dFjmq+3p8uTGVu2AS+yCfPrWFbQ2J3RdiYZxKEmLtIgSnYTK/tDisNM5 8o6Pz9soTgthC+VjVcH2/02LccjoEcm6lAqwqNZCQolGHSu6WTf920/ttGhwu49YYoTh ar8bRrd7QKqJ+QzWuGXXEHdrtR/KIardMNjOtiXQ6VCQ7d2M680kMVqhuBndE783+Hzf pVRZkSIXvUBi89Yt2xLFegkbNcozD6YJr5zBmDV0BE2hA8/SdVOWOiI9uq2960SNWhOU zbUg== X-Gm-Message-State: ANoB5pkVSLG7rwOq7Z3UB/1hDoyORhMhp0zNJV3KsZxBgFfhBBiC3FVC xDngCdgJ9H18DJewiasskQlOyQ== X-Google-Smtp-Source: AA0mqf6/YD18aEE6rU8aUaZ4jctPLvx59/ZMaHo7Gsj1aDHJSrJpxqG/7rk5arlZC9ab/P2Dzxe2tg== X-Received: by 2002:ac2:5964:0:b0:4b4:b5d3:650f with SMTP id h4-20020ac25964000000b004b4b5d3650fmr22593861lfp.649.1669813805526; Wed, 30 Nov 2022 05:10:05 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 2/8] clk: qcom: rpmh: reuse common duplicate clocks Date: Wed, 30 Nov 2022 15:09:55 +0200 Message-Id: <20221130131001.20912-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After the grouping it is obvious that some of the clock definitions are pure duplicates. Rename them to use a single common name for the clock. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index f13c9bd610d0..c4852bbd00bf 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -350,9 +350,7 @@ DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); -DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); -DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); @@ -362,7 +360,6 @@ DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); -DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1); DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); @@ -370,14 +367,11 @@ DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1); -DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); -DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); -DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); @@ -427,12 +421,12 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, - [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, + [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, + [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, + [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, + [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, - [RPMH_IPA_CLK] = &sdx55_ipa.hw, + [RPMH_IPA_CLK] = &sdm845_ipa.hw, }; static const struct clk_rpmh_desc clk_rpmh_sdx55 = { @@ -549,8 +543,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { static struct clk_hw *sc8280xp_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, - [RPMH_LN_BB_CLK3] = &sc8280xp_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sc8280xp_ln_bb_clk3_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, [RPMH_IPA_CLK] = &sdm845_ipa.hw, [RPMH_PKA_CLK] = &sm8350_pka.hw, [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, @@ -624,8 +618,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { static struct clk_hw *sdx65_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, - [RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw, + [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, + [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, From patchwork Wed Nov 30 13:09:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 422A9C433FE for ; Wed, 30 Nov 2022 13:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235564AbiK3NKK (ORCPT ); Wed, 30 Nov 2022 08:10:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230415AbiK3NKJ (ORCPT ); Wed, 30 Nov 2022 08:10:09 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 387C26C709 for ; Wed, 30 Nov 2022 05:10:08 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id f13so26848995lfa.6 for ; Wed, 30 Nov 2022 05:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m2oMs5vaEGLYORCmKlXIqTDD4xJk1CYYtug6Dlff+bM=; b=i2oUKn98CeeGvXLJieXBiUcBhSxE/qkoB8WRVu9fwTdnNmYlQEyvZOU23qUsxVGurE rRQq9UQOvY9WqibZk+xi2AoP5nsgX4oHP8bYBO5UG3sG10udMnLuJY1AQPAwdiWVHcKa yugPeoNkRnHOjhqTHIw4ePtUWecA6EF7vMf1atst6RuVm+RtzgfiyRNbhFlypkZVufA3 JCGuMyzUzaDAcdUTphj3dnZPXIs0c4ZHnRrVMz7zUNyNvpYVfR54BLyFJG/nxRqwWjbS 2Xzpcg3g3S5Xfjm/6kfDNW8NaDpMQ72uRfai/odyPSUXW91BJ9GHGugl7cGCM1CgDNtl /6gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m2oMs5vaEGLYORCmKlXIqTDD4xJk1CYYtug6Dlff+bM=; b=TysSH8qNpujxYsXSSp4UJ0FjeIrcgFZS7KHDaJlwQuy6Ybfnhyou3unu+UG2mXMixA yFtLI6Suwz5VDxKWnaKVNhdxbdf1wpW0PjKHQyk/4EgvliGaUsl1/uZ8X5MKdn0eqDsv MzQoGtsHc8OtZAe1vXbbQSRnkDsYPW1sleIBnY7wnqfmvhPiKiW37/aWxTcBQerXpL7Z O73CTjeiN2axBPolWh0sQG/J9sjjdRmTHsxU9s6WCIrpIZ1TID84M9fRiS1Y9Dazlti3 J6gsHFDRiayvpvpyUnoe38yIvIYQqD4OKeVuX7xAJw7JbmiPdqGYECH9z3exVE8un49c w02g== X-Gm-Message-State: ANoB5pkXwDy4LDwHL/1pJMjjDQM545DPXtCKdQkZ8d2ElSepuqx+vZcW W9iC7pFBsXojQ1lBoAqhp7IEnw== X-Google-Smtp-Source: AA0mqf4xkkMJQioApK7ZQzY7KQkvPtLL42MdNghy8YBLJN6TAmAAxwxZORuCzi7WlgpBVZkG/Pg2pw== X-Received: by 2002:a05:6512:234c:b0:4b5:26e0:9d8d with SMTP id p12-20020a056512234c00b004b526e09d8dmr2661551lfu.165.1669813806515; Wed, 30 Nov 2022 05:10:06 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 3/8] clk: qcom: rpmh: drop all _ao names Date: Wed, 30 Nov 2022 15:09:56 +0200 Message-Id: <20221130131001.20912-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation for the further cleanup, remove the active only names, they can be easily generated from the standard ones. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Reviewed-by: Abel Vesa --- drivers/clk/qcom/clk-rpmh.c | 62 ++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index c4852bbd00bf..00c0c8f851bd 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -70,15 +70,15 @@ struct clk_rpmh_desc { static DEFINE_MUTEX(rpmh_clk_lock); -#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ +#define __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ _res_en_offset, _res_on, _div) \ - static struct clk_rpmh _platform##_##_name_active; \ + static struct clk_rpmh _platform##_##_name##_ao; \ static struct clk_rpmh _platform##_##_name = { \ .res_name = _res_name, \ .res_addr = _res_en_offset, \ .res_on_val = _res_on, \ .div = _div, \ - .peer = &_platform##_##_name_active, \ + .peer = &_platform##_##_name##_ao, \ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT(RPMH_ACTIVE_ONLY_STATE) | \ BIT(RPMH_SLEEP_STATE)), \ @@ -92,7 +92,7 @@ static DEFINE_MUTEX(rpmh_clk_lock); .num_parents = 1, \ }, \ }; \ - static struct clk_rpmh _platform##_##_name_active = { \ + static struct clk_rpmh _platform##_##_name##_ao= { \ .res_name = _res_name, \ .res_addr = _res_en_offset, \ .res_on_val = _res_on, \ @@ -102,7 +102,7 @@ static DEFINE_MUTEX(rpmh_clk_lock); BIT(RPMH_ACTIVE_ONLY_STATE)), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpmh_ops, \ - .name = #_name_active, \ + .name = #_name "_ao", \ .parent_data = &(const struct clk_parent_data){ \ .fw_name = "xo", \ .name = "xo_board", \ @@ -111,14 +111,12 @@ static DEFINE_MUTEX(rpmh_clk_lock); }, \ } -#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \ - _res_on, _div) \ - __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ +#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \ + __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) -#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \ - _div) \ - __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ +#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \ + __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ CLK_RPMH_VRM_EN_OFFSET, 1, _div) #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \ @@ -342,33 +340,33 @@ static const struct clk_ops clk_rpmh_bcm_ops = { }; /* Resource name must match resource id present in cmd-db */ -DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); -DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); -DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); -DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); +DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, "xo.lvl", 0x3, 1); +DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2); +DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4); +DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4); -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); +DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2); +DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2); +DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, "lnbclka3", 2); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, "lnbclka1", 4); +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, "lnbclka2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, "lnbclkg2", 4); +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, "lnbclkg3", 4); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, "rfclka1", 1); +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, "rfclka2", 1); +DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, "rfclka3", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, "rfclka4", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, "rfclka5", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, "rfclkd1", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, "rfclkd2", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, "rfclkd3", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2); DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); From patchwork Wed Nov 30 13:09:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0B65C4708D for ; Wed, 30 Nov 2022 13:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235571AbiK3NKL (ORCPT ); Wed, 30 Nov 2022 08:10:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235557AbiK3NKK (ORCPT ); Wed, 30 Nov 2022 08:10:10 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E379E6CA32 for ; Wed, 30 Nov 2022 05:10:08 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id g7so26873284lfv.5 for ; Wed, 30 Nov 2022 05:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IcjnLOxp/MVZG9kAvam77qBm0fRxGbijyapmGrNxfjQ=; b=YRNnUA417vKrQRUmSgaP//ALdZNfNRxR/T+1/Ose5piP3utwMUuGwNtD/qAjAsP0cR yk5bRixfpMq9zhGoeKzkk458QNlsdGx0iXqNectqCDlFj3Ja2Z2qghfGiGkgSv6N50yo 9eWOhCd0LIRT3+Zfhnqh/Yeg18KNAWZU2Gnx0KCquFd5XheFdEDC4SXV+kgOW+ejFRbe B/Dt6Ecw0bxQPl0XgGCQAi2Xmuc6UEiyIfbwbYXh9LTvYdaY+YnSK1Z4mxiXsgBCZMHS rYExL18XtDgiZeQ9rh2oZf2Pxs+Tq+3bStAQAhGeSL1xjUQtkxEhvAWwafDUvl2Qr9yI Cl0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IcjnLOxp/MVZG9kAvam77qBm0fRxGbijyapmGrNxfjQ=; b=D+PFiJF+uJ595GPG5LH80xJ8QmR6antZ1WfcS/Jwcr78LFH+ix9Y7K1LxzBt6nGT0b DhFwl0cE5D8kjSDeDJRg5Hh/QUdEpTG6kXm1dM0CrgKOTDSB3vu8EBdw5tzsXXOFF38M vudV0Vcf8/lH1RiW4gd7omLqmIfuGZczMerf0w6N/2ykuG44930GVkWioaPM5CpuVfKJ /eyNMTXqDRtTXw34ZIG4nHwViNab5A5OvzQwdYFzXEncsVwsPK/9bLXrNWtMrG0eHKiF 57kLkJe4ItrNyQ/9vtaDtmTSE2JL9zqpD2HMu+2oemGoDHWYwZATDkew0AA/B5d+Fz+h lyEQ== X-Gm-Message-State: ANoB5pm7QJTxklAv1uFGYjL21yWEWFqr82BGYYbIvqFAeBa/PeLIWV5i 5/U5bNqnVKeG2BYQStBcGngq2w== X-Google-Smtp-Source: AA0mqf7ShY1FeyaikPqo7Xx8K6ElHrlT+dANeBLWTHCyKpGg6q752cSixut9bMI3Eu+4cK6hGHW3TQ== X-Received: by 2002:ac2:508e:0:b0:4a2:2a60:ecda with SMTP id f14-20020ac2508e000000b004a22a60ecdamr20886967lfm.81.1669813807260; Wed, 30 Nov 2022 05:10:07 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 4/8] clk: qcom: rpmh: remove platform names from BCM clocks Date: Wed, 30 Nov 2022 15:09:57 +0200 Message-Id: <20221130131001.20912-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are no platform-specific parts in the BCM clocks, drop the platform name from the clock definitions, replacing it with clk_rpmh to have the common prefix. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder --- drivers/clk/qcom/clk-rpmh.c | 52 ++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 00c0c8f851bd..5044f9fa156d 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -119,8 +119,8 @@ static DEFINE_MUTEX(rpmh_clk_lock); __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ CLK_RPMH_VRM_EN_OFFSET, 1, _div) -#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \ - static struct clk_rpmh _platform##_##_name = { \ +#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ + static struct clk_rpmh clk_rpmh_##_name = { \ .res_name = _res_name, \ .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ .div = 1, \ @@ -368,11 +368,11 @@ DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1); DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2); -DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); -DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); -DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); -DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); -DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); +DEFINE_CLK_RPMH_BCM(ipa, "IP0"); +DEFINE_CLK_RPMH_BCM(ce, "CE0"); +DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); +DEFINE_CLK_RPMH_BCM(pka, "PKA0"); +DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, @@ -387,8 +387,8 @@ static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, - [RPMH_CE_CLK] = &sdm845_ce.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, + [RPMH_CE_CLK] = &clk_rpmh_ce.hw, }; static const struct clk_rpmh_desc clk_rpmh_sdm845 = { @@ -407,8 +407,8 @@ static struct clk_hw *sdm670_rpmh_clocks[] = { [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, - [RPMH_CE_CLK] = &sdm845_ce.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, + [RPMH_CE_CLK] = &clk_rpmh_ce.hw, }; static const struct clk_rpmh_desc clk_rpmh_sdm670 = { @@ -423,8 +423,8 @@ static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, - [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, + [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; static const struct clk_rpmh_desc clk_rpmh_sdx55 = { @@ -463,7 +463,7 @@ static struct clk_hw *sc7180_rpmh_clocks[] = { [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; static const struct clk_rpmh_desc clk_rpmh_sc7180 = { @@ -528,9 +528,9 @@ static struct clk_hw *sm8350_rpmh_clocks[] = { [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw, [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, - [RPMH_PKA_CLK] = &sm8350_pka.hw, - [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, + [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, + [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm8350 = { @@ -543,9 +543,9 @@ static struct clk_hw *sc8280xp_rpmh_clocks[] = { [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, - [RPMH_PKA_CLK] = &sm8350_pka.hw, - [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, + [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, + [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, }; static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { @@ -568,7 +568,7 @@ static struct clk_hw *sm8450_rpmh_clocks[] = { [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm8450 = { @@ -587,9 +587,9 @@ static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, - [RPMH_PKA_CLK] = &sm8350_pka.hw, - [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, + [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, + [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, }; static const struct clk_rpmh_desc clk_rpmh_sc7280 = { @@ -626,8 +626,8 @@ static struct clk_hw *sdx65_rpmh_clocks[] = { [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, - [RPMH_IPA_CLK] = &sdm845_ipa.hw, - [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, + [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, }; static const struct clk_rpmh_desc clk_rpmh_sdx65 = { From patchwork Wed Nov 30 13:09:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2766FC352A1 for ; Wed, 30 Nov 2022 13:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233781AbiK3NKM (ORCPT ); Wed, 30 Nov 2022 08:10:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234022AbiK3NKL (ORCPT ); Wed, 30 Nov 2022 08:10:11 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 072E56B3A4 for ; Wed, 30 Nov 2022 05:10:10 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id d3so20829463ljl.1 for ; Wed, 30 Nov 2022 05:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jrj5yVzQhvepfPvamvBCTAj0aEaeJCmjm0ZXV9chkw8=; b=Y6pvGfLiqNCB9LdfJqas9KKlsukXuOChEU62YQOUegDhu782g7bCWinNkaGH8oFmj+ a4CRHElqTwEMgKZcIZIqOzti92QDSmY58XjOCffYD9cUzXvB6dw6co9gu1b0dMNM2DSJ tGOhP75M2ecWvUNuLHjhmelvhDCFIYybs2+eObjGLecL56n4/TcM06/ERKGLjNQGnlZ5 LdXX0vF0zsmgN68np2ib8j64KVUI0sxKOXQ8Hg+sQFcQRW+lKaZdup70axXtMs8jmwHK /BfWutcPfbtix78BWWDCK+JGLkydo0ll9ApwUzD+vGCBLHfrs4AH84cnTfvdv05HwzSh 2BEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jrj5yVzQhvepfPvamvBCTAj0aEaeJCmjm0ZXV9chkw8=; b=QueMqA3iIewmGMztQWflY4HxAjCXtju11L6WlwfqOWYuVAvZbegnmJmUNlMSWfBfdX dwpBkxL1Oyzp0npCDx9iICJBOqV9vLdd6hkvNJpk33s1eigcbZBaqC0uR9s2jq87gqEj IFj6KE7pZpHsVhscJUb7K50pWeWUOshQ3CzPVEEYy6OeCH4SLxftjT6CfKbuQaWe+3pP zI6Fg5jYpCxgB3+JCb3sAZCSx4bsYezt9hSfFKHT5RokUiQDSadSC+h6wNA50KPjUOFY kPqhNksBaHjVDZyT9LvxfqgLtrS0WKMO8s2DAOJDp0t7yyLfTDfzvL8Nc1bdhLolI4Gn d/uA== X-Gm-Message-State: ANoB5pl0naSF47Mle2iWoKYeMKOWG6Kmzw0fDE7pzyOsLpIGo/FPVihe QXB6bmYRysvwRJlK1Cb2GD+B0w== X-Google-Smtp-Source: AA0mqf7uRkXiQL5azoAwl6VhRhFxssyKv1g7QSIDPVgC4zccpYKB8/ReG80pBpJC+apysUCfQ5tgBg== X-Received: by 2002:a05:651c:1a2b:b0:277:5545:2ee5 with SMTP id by43-20020a05651c1a2b00b0027755452ee5mr15187536ljb.313.1669813808344; Wed, 30 Nov 2022 05:10:08 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:07 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 5/8] clk: qcom: rpmh: rename ARC clock data Date: Wed, 30 Nov 2022 15:09:58 +0200 Message-Id: <20221130131001.20912-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org RPMH ARC clocks are frequently shared between several platfoms. It makes little sense to encode the SoC name into the clock name, if the same clock is used for other SoCs. Rework the ARC clocks defintions to remove the SoC name. Keep the userspace-visible clock name, but encode the divider into the variable name. This also make it obvious which divider is used by the platform, making the code less error-prone. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 86 ++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 5044f9fa156d..bd6cb07b6154 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -70,15 +70,15 @@ struct clk_rpmh_desc { static DEFINE_MUTEX(rpmh_clk_lock); -#define __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ +#define __DEFINE_CLK_RPMH(_platform, _name, _cname, _res_name, \ _res_en_offset, _res_on, _div) \ - static struct clk_rpmh _platform##_##_name##_ao; \ - static struct clk_rpmh _platform##_##_name = { \ + static struct clk_rpmh _platform##_##_cname##_ao; \ + static struct clk_rpmh _platform##_##_cname = { \ .res_name = _res_name, \ .res_addr = _res_en_offset, \ .res_on_val = _res_on, \ .div = _div, \ - .peer = &_platform##_##_name##_ao, \ + .peer = &_platform##_##_cname##_ao, \ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT(RPMH_ACTIVE_ONLY_STATE) | \ BIT(RPMH_SLEEP_STATE)), \ @@ -92,12 +92,12 @@ static DEFINE_MUTEX(rpmh_clk_lock); .num_parents = 1, \ }, \ }; \ - static struct clk_rpmh _platform##_##_name##_ao= { \ + static struct clk_rpmh _platform##_##_cname##_ao= { \ .res_name = _res_name, \ .res_addr = _res_en_offset, \ .res_on_val = _res_on, \ .div = _div, \ - .peer = &_platform##_##_name, \ + .peer = &_platform##_##_cname, \ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT(RPMH_ACTIVE_ONLY_STATE)), \ .hw.init = &(struct clk_init_data){ \ @@ -111,12 +111,12 @@ static DEFINE_MUTEX(rpmh_clk_lock); }, \ } -#define DEFINE_CLK_RPMH_ARC(_platform, _name, _res_name, _res_on, _div) \ - __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ +#define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \ + __DEFINE_CLK_RPMH(clk_rpmh, _name, _name##_##div##_div, _res_name, \ CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) #define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \ - __DEFINE_CLK_RPMH(_platform, _name, _res_name, \ + __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \ CLK_RPMH_VRM_EN_OFFSET, 1, _div) #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ @@ -340,10 +340,10 @@ static const struct clk_ops clk_rpmh_bcm_ops = { }; /* Resource name must match resource id present in cmd-db */ -DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, "xo.lvl", 0x3, 1); -DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, "xo.lvl", 0x3, 2); -DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, "xo.lvl", 0x3, 4); -DEFINE_CLK_RPMH_ARC(sm6350, qlink, "qphy.lvl", 0x1, 4); +DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1); +DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); +DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); +DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2); @@ -375,8 +375,8 @@ DEFINE_CLK_RPMH_BCM(pka, "PKA0"); DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); static struct clk_hw *sdm845_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, @@ -397,8 +397,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { }; static struct clk_hw *sdm670_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, @@ -417,8 +417,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { }; static struct clk_hw *sdx55_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, @@ -433,8 +433,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = { }; static struct clk_hw *sm8150_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, @@ -453,8 +453,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = { }; static struct clk_hw *sc7180_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, @@ -472,8 +472,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = { }; static struct clk_hw *sc8180x_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, @@ -492,8 +492,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = { }; static struct clk_hw *sm8250_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, @@ -512,8 +512,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { }; static struct clk_hw *sm8350_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw, [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw, [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, @@ -539,8 +539,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { }; static struct clk_hw *sc8280xp_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, @@ -554,8 +554,8 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { }; static struct clk_hw *sm8450_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw, @@ -577,8 +577,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { }; static struct clk_hw *sc7280_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, @@ -598,14 +598,14 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = { }; static struct clk_hw *sm6350_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw, [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw, [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw, [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw, - [RPMH_QLINK_CLK] = &sm6350_qlink.hw, - [RPMH_QLINK_CLK_A] = &sm6350_qlink_ao.hw, + [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw, + [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm6350 = { @@ -614,8 +614,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { }; static struct clk_hw *sdx65_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, @@ -636,8 +636,8 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = { }; static struct clk_hw *qdu1000_rpmh_clocks[] = { - [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw, - [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw, + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { From patchwork Wed Nov 30 13:09:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59DB8C433FE for ; Wed, 30 Nov 2022 13:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235587AbiK3NKO (ORCPT ); Wed, 30 Nov 2022 08:10:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235557AbiK3NKN (ORCPT ); Wed, 30 Nov 2022 08:10:13 -0500 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33F8F6C72A for ; Wed, 30 Nov 2022 05:10:11 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id z4so20822969ljq.6 for ; Wed, 30 Nov 2022 05:10:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f42umZ4L1MBU02pFMvVCYvy3gksip6eZq2uEh+sCsco=; b=pI0bk9HDR/tV7Rga1E+psscAYLmqw55BTekgVVrL/mp1ME/g3KPKWwguF5eyH9H6g8 apSZy0Ll7hmSABJHD6Nz7MoygEWQgAJypVdHIVDqDPXu/RzOU6TqUEpzIe4qi/LmUWzo 09l4NEudRfzMcg76fuE1dROqZwVnWJOmtCtrCstTc2SYeccgZ9spwPryGiZQ5JlYPsAo sJgZJWuMHDCVLWwMDY+rQFVxYu3Wd9fp8r9hnhCG1n22QnTCothyEzF2wJNlme5XTEmQ YfkF/9ZjHcpIq1E3yT3j07l0HlkHVAf9w1RoWtm5u4iUXDN3Cnm4ZVLzJe9SYJA1V5BA XxSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f42umZ4L1MBU02pFMvVCYvy3gksip6eZq2uEh+sCsco=; b=o9EW1ZcQaH5FaQDKtkgivvZCMPqJvgoJyFhWEGxCpYRv/vLH6RWq73/feIgRKGWyol LagVPxMtAE7dxzyPlnNSgt6qOtYQWfiKUJLmHY8Qso+/F4gGUzR9xj3F9iQximT916qy b/qfVjcbsX3g/ZY5CjCa2rJExcW74Rlrgi/oSiyveitN6LSFNcPDP+6u8A2LS0gDORMj Tpv78Br43CLzgwPGh2igrUnheUAkbG5odX/i4qrorczTnVPyD9MW05iGuonA2Ze+lPqG zBXyq2pvmW3Vb3RYQQM5V4PZEnfJvQIs4fitNLBZqW9EiPIHB0n9Ei3LBh6XgVf2vdFE eriQ== X-Gm-Message-State: ANoB5plw7bPmOQOrqlgErzjQfjSteW6sYC49MlDrsW6lX3ZOD0w9rXdp Nr9ykp9B9osIB4cPo40+f9QIKA== X-Google-Smtp-Source: AA0mqf73vZxSZ8Mx1B22rfOWZZEgQz59PIG6IgtVOuOLCtv9WOx8N7a6T2TbPCVbscME/hfUfK4x1g== X-Received: by 2002:a05:651c:158c:b0:26c:90f:f8fe with SMTP id h12-20020a05651c158c00b0026c090ff8femr20750476ljq.2.1669813809445; Wed, 30 Nov 2022 05:10:09 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 6/8] clk: qcom: rpmh: rename VRM clock data Date: Wed, 30 Nov 2022 15:09:59 +0200 Message-Id: <20221130131001.20912-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org RPMH VRM clocks are frequently shared between several platfoms. It makes little sense to encode the SoC name into the clock name, if the same clock is used for other SoCs. Rework the VRM clocks defintions to remove the SoC name. Keep the userspace-visible clock name, but encode the part of cmd resource and the divider into the variable name. This also make it obvious which variant is used, making the code less error-prone. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 258 ++++++++++++++++++------------------ 1 file changed, 129 insertions(+), 129 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index bd6cb07b6154..dcac84614b06 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -115,8 +115,8 @@ static DEFINE_MUTEX(rpmh_clk_lock); __DEFINE_CLK_RPMH(clk_rpmh, _name, _name##_##div##_div, _res_name, \ CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) -#define DEFINE_CLK_RPMH_VRM(_platform, _name, _res_name, _div) \ - __DEFINE_CLK_RPMH(_platform, _name, _name, _res_name, \ +#define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \ + __DEFINE_CLK_RPMH(clk_rpmh, _name, _name##_suffix, _res_name, \ CLK_RPMH_VRM_EN_OFFSET, 1, _div) #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ @@ -345,28 +345,28 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, "lnbclka1", 2); -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, "lnbclka2", 2); -DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, "lnbclka3", 2); +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, "lnbclka1", 4); -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, "lnbclka2", 4); +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4); +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, "lnbclkg2", 4); -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, "lnbclkg3", 4); +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4); +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, "rfclka1", 1); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, "rfclka2", 1); -DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, "rfclka3", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, "rfclka4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, "rfclka5", 1); +DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1); +DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1); +DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1); +DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1); +DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, "rfclkd1", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, "rfclkd2", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, "rfclkd3", 1); -DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1); +DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); +DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); +DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, "divclka1", 2); +DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); DEFINE_CLK_RPMH_BCM(ipa, "IP0"); DEFINE_CLK_RPMH_BCM(ce, "CE0"); @@ -377,16 +377,16 @@ DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_CE_CLK] = &clk_rpmh_ce.hw, }; @@ -399,14 +399,14 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { static struct clk_hw *sdm670_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_CE_CLK] = &clk_rpmh_ce.hw, }; @@ -419,10 +419,10 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { static struct clk_hw *sdx55_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; @@ -435,16 +435,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = { static struct clk_hw *sm8150_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm8150 = { @@ -455,14 +455,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = { static struct clk_hw *sc7180_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; @@ -474,16 +474,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = { static struct clk_hw *sc8180x_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sc8180x = { @@ -494,16 +494,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = { static struct clk_hw *sm8250_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_sm8250 = { @@ -514,20 +514,20 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { static struct clk_hw *sm8350_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw, - [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, - [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw, - [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw, + [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw, + [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, + [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, + [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, @@ -541,8 +541,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { static struct clk_hw *sc8280xp_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, - [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, @@ -556,18 +556,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { static struct clk_hw *sm8450_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, - [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; @@ -579,14 +579,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, @@ -600,10 +600,10 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = { static struct clk_hw *sm6350_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw, - [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw, - [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw, - [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw, [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw, [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw, }; @@ -616,16 +616,16 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { static struct clk_hw *sdx65_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, - [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, - [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, - [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, - [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, - [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, - [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, - [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, - [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, - [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, - [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, }; From patchwork Wed Nov 30 13:10:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4854C352A1 for ; Wed, 30 Nov 2022 13:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230367AbiK3NKP (ORCPT ); Wed, 30 Nov 2022 08:10:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232574AbiK3NKN (ORCPT ); Wed, 30 Nov 2022 08:10:13 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3A726C709 for ; Wed, 30 Nov 2022 05:10:11 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id x6so6636925lji.10 for ; Wed, 30 Nov 2022 05:10:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7yMF4tXA4BGGddk6s4itzrTJFApaXVgAQciV4RpoM9c=; b=VKBp2IRbMGLiDX+aD/PCr+qlP4id1ivvJgHyx7J3vv36r6Y8qIhZZd+dUOrhkcSUsQ lPZuK0z3DTTKS+tdcApCyVLcEFc39QT7OmOu9YciWX3tpCV+HVDlle7gMiy27Aesjwdg xPKwRSoxlja8WDBy1wXLaiMtjJNItQ6AqbtYPgmtedPInywQg9tGnxsOg/ZS2xRGiIdR 3XzAiorAP64gCN++bwWFuG6Q2UtsNRRWn0icLSeNOu75ZA5/MuaZu38IDfHqaxaR0bKR xe3MRtcSpmo6fJOCeedXIX1j1SOSKTwktDMG1o1j9UqBHiBlt54pHY+3wjVnl26v6oRZ XTOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7yMF4tXA4BGGddk6s4itzrTJFApaXVgAQciV4RpoM9c=; b=Td0XApP/52Ui84psMMaa9UP9ToSHWsm+Bvlj51Ukn9YRGOLoXfuKsQRDD8kDMwdtjn 1xXgS9DoiZI3KjdOVyE9q3+DxRjAjpE21GOaTpaB6WfavNX8N7Oc5aT2xMlGd5YKbb7I Wz1+RqGP8X8HB1ieeTxYHByhc9we+qPh5bTtf0KmyqyJW1gupDSCj8Wkp4Ttg48Lhn3a 0Vrlie9QtDUtJcMlXfvFoXMLY9sJQI7jaBLqsw6sPl9JH1kU29MSUV79NkAJW0USsX/8 bDZyn/3qFoacAYA/IppA4mDnrUYnktT++UXqa6Vun11r10UASyBBrCcrblGV9CvKG/4j pCpA== X-Gm-Message-State: ANoB5pnefsjuWO64UztLvLmKKCtvLIxHMNiKY4oc3miuJAiVnmEx57au lNq2egYcquMa0uwedT+V7xq2ug== X-Google-Smtp-Source: AA0mqf63tTdvK++p3YoxsEgvMxGYi8J0irg0ybb6De3RaIJ+YbwMZDnHb/KQPn0hj1x8SupZHPWKvA== X-Received: by 2002:a2e:9806:0:b0:279:97ef:c1ee with SMTP id a6-20020a2e9806000000b0027997efc1eemr7289861ljj.165.1669813810372; Wed, 30 Nov 2022 05:10:10 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:09 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 7/8] clk: qcom: rpmh: remove the last traces of the platform usage Date: Wed, 30 Nov 2022 15:10:00 +0200 Message-Id: <20221130131001.20912-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Simplify __DEFINE_CLK_RPMH macros to use clk_rpmh directly instead of passing it through the `_platform' argument. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index dcac84614b06..2bcf725dd919 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -70,15 +70,15 @@ struct clk_rpmh_desc { static DEFINE_MUTEX(rpmh_clk_lock); -#define __DEFINE_CLK_RPMH(_platform, _name, _cname, _res_name, \ +#define __DEFINE_CLK_RPMH(_name, _cname, _res_name, \ _res_en_offset, _res_on, _div) \ - static struct clk_rpmh _platform##_##_cname##_ao; \ - static struct clk_rpmh _platform##_##_cname = { \ + static struct clk_rpmh clk_rpmh_##_cname##_ao; \ + static struct clk_rpmh clk_rpmh_##_cname = { \ .res_name = _res_name, \ .res_addr = _res_en_offset, \ .res_on_val = _res_on, \ .div = _div, \ - .peer = &_platform##_##_cname##_ao, \ + .peer = &clk_rpmh_##_cname##_ao, \ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT(RPMH_ACTIVE_ONLY_STATE) | \ BIT(RPMH_SLEEP_STATE)), \ @@ -92,12 +92,12 @@ static DEFINE_MUTEX(rpmh_clk_lock); .num_parents = 1, \ }, \ }; \ - static struct clk_rpmh _platform##_##_cname##_ao= { \ + static struct clk_rpmh clk_rpmh_##_cname##_ao= { \ .res_name = _res_name, \ .res_addr = _res_en_offset, \ .res_on_val = _res_on, \ .div = _div, \ - .peer = &_platform##_##_cname, \ + .peer = &clk_rpmh_##_cname, \ .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT(RPMH_ACTIVE_ONLY_STATE)), \ .hw.init = &(struct clk_init_data){ \ @@ -112,11 +112,11 @@ static DEFINE_MUTEX(rpmh_clk_lock); } #define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \ - __DEFINE_CLK_RPMH(clk_rpmh, _name, _name##_##div##_div, _res_name, \ + __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \ CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) #define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \ - __DEFINE_CLK_RPMH(clk_rpmh, _name, _name##_suffix, _res_name, \ + __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \ CLK_RPMH_VRM_EN_OFFSET, 1, _div) #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ From patchwork Wed Nov 30 13:10:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13059800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 921D9C4708C for ; Wed, 30 Nov 2022 13:10:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232574AbiK3NKQ (ORCPT ); Wed, 30 Nov 2022 08:10:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235580AbiK3NKO (ORCPT ); Wed, 30 Nov 2022 08:10:14 -0500 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E83666CA32 for ; Wed, 30 Nov 2022 05:10:12 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id q7so20787098ljp.9 for ; Wed, 30 Nov 2022 05:10:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bo9GFUnaG+OLf3jlfMFp4lSsJHfGSgrFNr0OU6zZytg=; b=HAtVPwnp5lznd8lS4Eq89mFVwSJ5mm3gCirRBwGGIssRmt4NUNmWJw+1/Wgk4ATNIn AkijLV2UECZ8ahJ7qeoES6njBAZEl2+2w479ecbEWN2dJBf4DBI3qqJLcusNjXueL+K0 Y+IOWuGjU7ugaZVfZNf8tOazU1HkAtza/k9swpwNM5Lv4bj2czxGSw9TXoZis0qhznNm Yi4PoS/MPXSj6iCGRnvu3M2cN0yacYvo97hYurEEw0Fy3DyQSZxJuih8OU9J/rMQKqEc x7GIg3JYUuN8j+VE4nYVQzi3UBq4ejbNzIcDdtpFhhcbtd2+mnzM2b3J5OKjF4Xlwadz oxUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bo9GFUnaG+OLf3jlfMFp4lSsJHfGSgrFNr0OU6zZytg=; b=odPXPDejcLnkS1fNFg+1WbVzty+GibeJtxj7s5oZM/piG3AnfyjTJdQAtKEoNFo6uV dcS7Ld1+htoNeeAM3dwIvOjHhsRtZGX8jeQgjvKDmu6TDgUDDIwi1/eBjSM7zvjlYyxV uAL5J3dGoB9USsYtpBsHlvZwu/2/dWE8glhNCsHrxRuwP12GE9NtruHKlSmDWia3rbOs ITEgRUAIAJZOQCWXmRJQpmycnIpS998qIJxj57+YzPhAWbQVVX3DoeKKbchFwkaU3+dt OfATTxOIK1+cf8EWbGAMJN17kx4qlSXxeGzld0LXniMR163cdn0bPEtZytUSF9SL4BQI WM2A== X-Gm-Message-State: ANoB5pl4DO7+De60UfMOUty+EEfk4fG80kEK3pLim/Mx0R6wxm717u/2 mudf7f5nlEv8D/aZE7klCfT11g== X-Google-Smtp-Source: AA0mqf53fk2nLc6KJw0eVVPK+qCjmC1esiOjBZ+4YvDYyuRlp991hFtsRpDvZJa0PGBTH55NSd1X7A== X-Received: by 2002:a2e:b0ef:0:b0:279:be29:cb69 with SMTP id h15-20020a2eb0ef000000b00279be29cb69mr2028667ljl.482.1669813811238; Wed, 30 Nov 2022 05:10:11 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id p9-20020ac246c9000000b004b01305732bsm250083lfo.216.2022.11.30.05.10.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 05:10:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 8/8] clk: qcom: rpm: drop the platform from clock definitions Date: Wed, 30 Nov 2022 15:10:01 +0200 Message-Id: <20221130131001.20912-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> References: <20221130131001.20912-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A single clock definition can be used on different platforms. Thus the platform part of the clock name is not correct (and can be misleading). Remove the platform-specific part of the defined clock. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpm.c | 194 +++++++++++++++++-------------------- 1 file changed, 89 insertions(+), 105 deletions(-) diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index 747c473b0b5e..bcab76776571 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -31,11 +31,11 @@ static const struct clk_parent_data gcc_cxo[] = { { .fw_name = "cxo", .name = "cxo_board" }, }; -#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ - static struct clk_rpm _platform##_##_active; \ - static struct clk_rpm _platform##_##_name = { \ +#define DEFINE_CLK_RPM(_name, _active, r_id) \ + static struct clk_rpm clk_rpm_##_active; \ + static struct clk_rpm clk_rpm_##_name = { \ .rpm_clk_id = (r_id), \ - .peer = &_platform##_##_active, \ + .peer = &clk_rpm_##_active, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_ops, \ @@ -44,9 +44,9 @@ static const struct clk_parent_data gcc_cxo[] = { .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ }; \ - static struct clk_rpm _platform##_##_active = { \ + static struct clk_rpm clk_rpm_##_active = { \ .rpm_clk_id = (r_id), \ - .peer = &_platform##_##_name, \ + .peer = &clk_rpm_##_name, \ .active_only = true, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ @@ -57,20 +57,20 @@ static const struct clk_parent_data gcc_cxo[] = { }, \ } -#define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset) \ - static struct clk_rpm _platform##_##_name = { \ +#define DEFINE_CLK_RPM_XO_BUFFER(_name, _active, offset) \ + static struct clk_rpm clk_rpm_##_name = { \ .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \ .xo_offset = (offset), \ .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_xo_ops, \ + .ops = &clk_rpm_xo_ops, \ .name = #_name, \ .parent_data = gcc_cxo, \ .num_parents = ARRAY_SIZE(gcc_cxo), \ }, \ } -#define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \ - static struct clk_rpm _platform##_##_name = { \ +#define DEFINE_CLK_RPM_FIXED(_name, _active, r_id, r) \ + static struct clk_rpm clk_rpm_##_name = { \ .rpm_clk_id = (r_id), \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ @@ -403,37 +403,47 @@ static const struct clk_ops clk_rpm_ops = { }; /* MSM8660/APQ8060 */ -DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); -DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK); -DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000); +DEFINE_CLK_RPM(afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); +DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); +DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); +DEFINE_CLK_RPM(daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); +DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); +DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); +DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); +DEFINE_CLK_RPM(smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK); +DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); +DEFINE_CLK_RPM(qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK); +DEFINE_CLK_RPM(nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); +DEFINE_CLK_RPM(nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); + +DEFINE_CLK_RPM_FIXED(pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000); + +DEFINE_CLK_RPM_XO_BUFFER(xo_d0_clk, xo_d0_a_clk, 0); +DEFINE_CLK_RPM_XO_BUFFER(xo_d1_clk, xo_d1_a_clk, 8); +DEFINE_CLK_RPM_XO_BUFFER(xo_a0_clk, xo_a0_a_clk, 16); +DEFINE_CLK_RPM_XO_BUFFER(xo_a1_clk, xo_a1_a_clk, 24); +DEFINE_CLK_RPM_XO_BUFFER(xo_a2_clk, xo_a2_a_clk, 28); static struct clk_rpm *msm8660_clks[] = { - [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk, - [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk, - [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk, - [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk, - [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk, - [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk, - [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk, - [RPM_SFPB_CLK] = &msm8660_sfpb_clk, - [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk, - [RPM_CFPB_CLK] = &msm8660_cfpb_clk, - [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk, - [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk, - [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk, - [RPM_SMI_CLK] = &msm8660_smi_clk, - [RPM_SMI_A_CLK] = &msm8660_smi_a_clk, - [RPM_EBI1_CLK] = &msm8660_ebi1_clk, - [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk, - [RPM_PLL4_CLK] = &msm8660_pll4_clk, + [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk, + [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk, + [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk, + [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk, + [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk, + [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk, + [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk, + [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk, + [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk, + [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk, + [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk, + [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk, + [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk, + [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk, + [RPM_SMI_CLK] = &clk_rpm_smi_clk, + [RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk, + [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk, + [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk, + [RPM_PLL4_CLK] = &clk_rpm_pll4_clk, }; static const struct rpm_clk_desc rpm_clk_msm8660 = { @@ -441,46 +451,30 @@ static const struct rpm_clk_desc rpm_clk_msm8660 = { .num_clks = ARRAY_SIZE(msm8660_clks), }; -/* apq8064 */ -DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); -DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28); - static struct clk_rpm *apq8064_clks[] = { - [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk, - [RPM_CFPB_CLK] = &apq8064_cfpb_clk, - [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk, - [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk, - [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk, - [RPM_EBI1_CLK] = &apq8064_ebi1_clk, - [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk, - [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk, - [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk, - [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk, - [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk, - [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk, - [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk, - [RPM_SFPB_CLK] = &apq8064_sfpb_clk, - [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk, - [RPM_QDSS_CLK] = &apq8064_qdss_clk, - [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk, - [RPM_XO_D0] = &apq8064_xo_d0_clk, - [RPM_XO_D1] = &apq8064_xo_d1_clk, - [RPM_XO_A0] = &apq8064_xo_a0_clk, - [RPM_XO_A1] = &apq8064_xo_a1_clk, - [RPM_XO_A2] = &apq8064_xo_a2_clk, + [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk, + [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk, + [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk, + [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk, + [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk, + [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk, + [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk, + [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk, + [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk, + [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk, + [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk, + [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk, + [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk, + [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk, + [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk, + [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk, + [RPM_QDSS_CLK] = &clk_rpm_qdss_clk, + [RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk, + [RPM_XO_D0] = &clk_rpm_xo_d0_clk, + [RPM_XO_D1] = &clk_rpm_xo_d1_clk, + [RPM_XO_A0] = &clk_rpm_xo_a0_clk, + [RPM_XO_A1] = &clk_rpm_xo_a1_clk, + [RPM_XO_A2] = &clk_rpm_xo_a2_clk, }; static const struct rpm_clk_desc rpm_clk_apq8064 = { @@ -488,33 +482,23 @@ static const struct rpm_clk_desc rpm_clk_apq8064 = { .num_clks = ARRAY_SIZE(apq8064_clks), }; -/* ipq806x */ -DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); -DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); - static struct clk_rpm *ipq806x_clks[] = { - [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk, - [RPM_CFPB_CLK] = &ipq806x_cfpb_clk, - [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk, - [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk, - [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk, - [RPM_EBI1_CLK] = &ipq806x_ebi1_clk, - [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk, - [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk, - [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk, - [RPM_SFPB_CLK] = &ipq806x_sfpb_clk, - [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk, - [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk, - [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk, - [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk, - [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk, + [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk, + [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk, + [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk, + [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk, + [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk, + [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk, + [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk, + [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk, + [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk, + [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk, + [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk, + [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk, + [RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk, + [RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk, + [RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk, + [RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk, }; static const struct rpm_clk_desc rpm_clk_ipq806x = {