From patchwork Fri Dec 2 07:08:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13062308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 087CAC4167B for ; Fri, 2 Dec 2022 07:08:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232505AbiLBHIU (ORCPT ); Fri, 2 Dec 2022 02:08:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232465AbiLBHIT (ORCPT ); Fri, 2 Dec 2022 02:08:19 -0500 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 782F881382 for ; Thu, 1 Dec 2022 23:08:18 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id r8so4431609ljn.8 for ; Thu, 01 Dec 2022 23:08:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xkHcQXrYVetwBz0HzmJulrgRpxbGrc7yz8CvYgvdPa8=; b=phIpf7i1xMxt1yI0oapJXupalHP8FBhkyZWs/Xx8cm9VNocoYkbz1VdthewpA8xs7P kXQc3YaAdzakUkwLJqFwZuZBDFB+sjXZGo7gfzdA58lCMUwkyUa3reYusT6F5S2dJWp8 FNFmURAVdoMahc2tn/2+B8ngJpN29AxuAnH+Mq4uTPipm7egGiLlo6OEsBFXxlXSpUlB Rn2M99VyN/8COxZ4npT3/lKg2yZ5UF7zXJ9yPuyyyyMpS+KSfvLc+DoxBcIoBk2Yy59q j8+nG1wKs3XgKc+LlwqXNZvnDbzWk7/7cm5U/6ejoCsFuvLmybaPbo9qU19lLgbPqhrc Fx3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xkHcQXrYVetwBz0HzmJulrgRpxbGrc7yz8CvYgvdPa8=; b=EsR9tyFVlewNUkPWZG0vtTp2dygbg06As1LJ5st828NqifMDta4apF1jBuRoIfenzx R0MJY37kr36m0OCOErnjQa16qL0kkOXTyEJ6jtT6otYNhpa29WA0XAN8SmQtp9KAbLy9 vC4s9ewV/L/7NRqnbRR3MUa1XVsIL+3dRP1Fe7GvfiHYb58odIEkFkhrwhKynlCIFOJ0 qb0Cclz0wNKnX0t4gh61d32aa28XKOBXnqpQfcNhjchuQXWmZJ26qcQZi5+RsDAExg2Z hY8fJyn8oU9GJQY8jnBQEInsVewKNzd42nImuHrY4UOUychFA7aTGh5GKkQq++ni51JA DmVA== X-Gm-Message-State: ANoB5pnFj2AMqoUZuJdK0wTG1X69Tt0DNuhGKt+F4EvYZfLbQj+6UN7S 1/XzF0y2OQXYar9NP1yhUcRKvA== X-Google-Smtp-Source: AA0mqf7btKVtEbOR3Z6N5alYhES9nXg3Pn3oBVg9ZPCZmLF66NT2O8DOC5bbyjvoKs8AZd5gc/rUZQ== X-Received: by 2002:a2e:a5c6:0:b0:277:22c3:afbb with SMTP id n6-20020a2ea5c6000000b0027722c3afbbmr17113632ljp.204.1669964896651; Thu, 01 Dec 2022 23:08:16 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a2-20020a19ca02000000b004946a1e045fsm913097lfg.197.2022.12.01.23.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 23:08:16 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 1/4] clk: qcom: rpm: remove unused active-only clock names Date: Fri, 2 Dec 2022 09:08:11 +0200 Message-Id: <20221202070814.482470-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> References: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The RPM_FIXED and RPM_XO_BUFFER clocks do not have the active-only counterparts. Drop corresponding unused arguments. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index 747c473b0b5e..7fee957bc44f 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -57,19 +57,19 @@ static const struct clk_parent_data gcc_cxo[] = { }, \ } -#define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset) \ +#define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, offset) \ static struct clk_rpm _platform##_##_name = { \ .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \ .xo_offset = (offset), \ .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_xo_ops, \ + .ops = &clk_rpm_xo_ops, \ .name = #_name, \ .parent_data = gcc_cxo, \ .num_parents = ARRAY_SIZE(gcc_cxo), \ }, \ } -#define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \ +#define DEFINE_CLK_RPM_FIXED(_platform, _name, r_id, r) \ static struct clk_rpm _platform##_##_name = { \ .rpm_clk_id = (r_id), \ .rate = (r), \ @@ -412,7 +412,7 @@ DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK); DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000); +DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, QCOM_RPM_PLL_4, 540672000); static struct clk_rpm *msm8660_clks[] = { [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk, @@ -451,11 +451,11 @@ DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, 0); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, 8); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, 16); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, 24); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, 28); static struct clk_rpm *apq8064_clks[] = { [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk, From patchwork Fri Dec 2 07:08:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13062309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73F74C47090 for ; Fri, 2 Dec 2022 07:08:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232152AbiLBHIV (ORCPT ); Fri, 2 Dec 2022 02:08:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232384AbiLBHIU (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a2-20020a19ca02000000b004946a1e045fsm913097lfg.197.2022.12.01.23.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 23:08:16 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 2/4] clk: qcom: rpm: drop separate active-only names Date: Fri, 2 Dec 2022 09:08:12 +0200 Message-Id: <20221202070814.482470-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> References: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To simplify code reviews remove duplication between normal and active-only clock names. Get a single clock name and generate both names internally. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpm.c | 68 +++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index 7fee957bc44f..ca96f4bf7b2d 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -31,27 +31,27 @@ static const struct clk_parent_data gcc_cxo[] = { { .fw_name = "cxo", .name = "cxo_board" }, }; -#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ - static struct clk_rpm _platform##_##_active; \ - static struct clk_rpm _platform##_##_name = { \ +#define DEFINE_CLK_RPM(_platform, _name, r_id) \ + static struct clk_rpm _platform##_##_name##_a_clk; \ + static struct clk_rpm _platform##_##_name##_clk = { \ .rpm_clk_id = (r_id), \ - .peer = &_platform##_##_active, \ + .peer = &_platform##_##_name##_a_clk, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_ops, \ - .name = #_name, \ + .name = #_name "_clk", \ .parent_data = gcc_pxo, \ .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ }; \ - static struct clk_rpm _platform##_##_active = { \ + static struct clk_rpm _platform##_##_name##_a_clk = { \ .rpm_clk_id = (r_id), \ - .peer = &_platform##_##_name, \ + .peer = &_platform##_##_name##_clk, \ .active_only = true, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_ops, \ - .name = #_active, \ + .name = #_name "_a_clk", \ .parent_data = gcc_pxo, \ .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ @@ -403,15 +403,15 @@ static const struct clk_ops clk_rpm_ops = { }; /* MSM8660/APQ8060 */ -DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); -DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK); -DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); +DEFINE_CLK_RPM(msm8660, afab, QCOM_RPM_APPS_FABRIC_CLK); +DEFINE_CLK_RPM(msm8660, sfab, QCOM_RPM_SYS_FABRIC_CLK); +DEFINE_CLK_RPM(msm8660, mmfab, QCOM_RPM_MM_FABRIC_CLK); +DEFINE_CLK_RPM(msm8660, daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); +DEFINE_CLK_RPM(msm8660, sfpb, QCOM_RPM_SFPB_CLK); +DEFINE_CLK_RPM(msm8660, cfpb, QCOM_RPM_CFPB_CLK); +DEFINE_CLK_RPM(msm8660, mmfpb, QCOM_RPM_MMFPB_CLK); +DEFINE_CLK_RPM(msm8660, smi, QCOM_RPM_SMI_CLK); +DEFINE_CLK_RPM(msm8660, ebi1, QCOM_RPM_EBI1_CLK); DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, QCOM_RPM_PLL_4, 540672000); static struct clk_rpm *msm8660_clks[] = { @@ -442,15 +442,15 @@ static const struct rpm_clk_desc rpm_clk_msm8660 = { }; /* apq8064 */ -DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); -DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK); +DEFINE_CLK_RPM(apq8064, afab, QCOM_RPM_APPS_FABRIC_CLK); +DEFINE_CLK_RPM(apq8064, cfpb, QCOM_RPM_CFPB_CLK); +DEFINE_CLK_RPM(apq8064, daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); +DEFINE_CLK_RPM(apq8064, ebi1, QCOM_RPM_EBI1_CLK); +DEFINE_CLK_RPM(apq8064, mmfab, QCOM_RPM_MM_FABRIC_CLK); +DEFINE_CLK_RPM(apq8064, mmfpb, QCOM_RPM_MMFPB_CLK); +DEFINE_CLK_RPM(apq8064, sfab, QCOM_RPM_SYS_FABRIC_CLK); +DEFINE_CLK_RPM(apq8064, sfpb, QCOM_RPM_SFPB_CLK); +DEFINE_CLK_RPM(apq8064, qdss, QCOM_RPM_QDSS_CLK); DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, 0); DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, 8); DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, 16); @@ -489,14 +489,14 @@ static const struct rpm_clk_desc rpm_clk_apq8064 = { }; /* ipq806x */ -DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); -DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); +DEFINE_CLK_RPM(ipq806x, afab, QCOM_RPM_APPS_FABRIC_CLK); +DEFINE_CLK_RPM(ipq806x, cfpb, QCOM_RPM_CFPB_CLK); +DEFINE_CLK_RPM(ipq806x, daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); +DEFINE_CLK_RPM(ipq806x, ebi1, QCOM_RPM_EBI1_CLK); +DEFINE_CLK_RPM(ipq806x, sfab, QCOM_RPM_SYS_FABRIC_CLK); +DEFINE_CLK_RPM(ipq806x, sfpb, QCOM_RPM_SFPB_CLK); +DEFINE_CLK_RPM(ipq806x, nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK); +DEFINE_CLK_RPM(ipq806x, nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK); static struct clk_rpm *ipq806x_clks[] = { [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, From patchwork Fri Dec 2 07:08:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13062310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18B09C4708E for ; Fri, 2 Dec 2022 07:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232383AbiLBHIW (ORCPT ); Fri, 2 Dec 2022 02:08:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230094AbiLBHIU (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a2-20020a19ca02000000b004946a1e045fsm913097lfg.197.2022.12.01.23.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 23:08:17 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 3/4] clk: qcom: rpm: drop the _clk suffix completely Date: Fri, 2 Dec 2022 09:08:13 +0200 Message-Id: <20221202070814.482470-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> References: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Drop the _clk suffix from other clocks too. This does not produce any user-visible changes, just syntax sugar. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpm.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index ca96f4bf7b2d..74a94e858920 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -58,24 +58,24 @@ static const struct clk_parent_data gcc_cxo[] = { } #define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, offset) \ - static struct clk_rpm _platform##_##_name = { \ + static struct clk_rpm _platform##_##_name##_clk = { \ .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \ .xo_offset = (offset), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_xo_ops, \ - .name = #_name, \ + .name = #_name "_clk", \ .parent_data = gcc_cxo, \ .num_parents = ARRAY_SIZE(gcc_cxo), \ }, \ } #define DEFINE_CLK_RPM_FIXED(_platform, _name, r_id, r) \ - static struct clk_rpm _platform##_##_name = { \ + static struct clk_rpm _platform##_##_name##_clk = { \ .rpm_clk_id = (r_id), \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_fixed_ops, \ - .name = #_name, \ + .name = #_name "_clk", \ .parent_data = gcc_pxo, \ .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ @@ -412,7 +412,7 @@ DEFINE_CLK_RPM(msm8660, cfpb, QCOM_RPM_CFPB_CLK); DEFINE_CLK_RPM(msm8660, mmfpb, QCOM_RPM_MMFPB_CLK); DEFINE_CLK_RPM(msm8660, smi, QCOM_RPM_SMI_CLK); DEFINE_CLK_RPM(msm8660, ebi1, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, QCOM_RPM_PLL_4, 540672000); +DEFINE_CLK_RPM_FIXED(msm8660, pll4, QCOM_RPM_PLL_4, 540672000); static struct clk_rpm *msm8660_clks[] = { [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk, @@ -451,11 +451,11 @@ DEFINE_CLK_RPM(apq8064, mmfpb, QCOM_RPM_MMFPB_CLK); DEFINE_CLK_RPM(apq8064, sfab, QCOM_RPM_SYS_FABRIC_CLK); DEFINE_CLK_RPM(apq8064, sfpb, QCOM_RPM_SFPB_CLK); DEFINE_CLK_RPM(apq8064, qdss, QCOM_RPM_QDSS_CLK); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, 0); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, 8); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, 16); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, 24); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, 28); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0, 0); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1, 8); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0, 16); +DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1, 24); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a2-20020a19ca02000000b004946a1e045fsm913097lfg.197.2022.12.01.23.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 23:08:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/4] clk: qcom: rpm: drop the platform from clock definitions Date: Fri, 2 Dec 2022 09:08:14 +0200 Message-Id: <20221202070814.482470-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> References: <20221202070814.482470-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org A single clock definition can be used on different platforms. Thus the platform part of the clock name is not correct (and can be misleading). Remove the platform-specific part of the defined clock. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpm.c | 194 +++++++++++++++++-------------------- 1 file changed, 89 insertions(+), 105 deletions(-) diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index 74a94e858920..b1be5b664bf3 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -31,11 +31,11 @@ static const struct clk_parent_data gcc_cxo[] = { { .fw_name = "cxo", .name = "cxo_board" }, }; -#define DEFINE_CLK_RPM(_platform, _name, r_id) \ - static struct clk_rpm _platform##_##_name##_a_clk; \ - static struct clk_rpm _platform##_##_name##_clk = { \ +#define DEFINE_CLK_RPM(_name, r_id) \ + static struct clk_rpm clk_rpm_##_name##_a_clk; \ + static struct clk_rpm clk_rpm_##_name##_clk = { \ .rpm_clk_id = (r_id), \ - .peer = &_platform##_##_name##_a_clk, \ + .peer = &clk_rpm_##_name##_a_clk, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_ops, \ @@ -44,9 +44,9 @@ static const struct clk_parent_data gcc_cxo[] = { .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ }; \ - static struct clk_rpm _platform##_##_name##_a_clk = { \ + static struct clk_rpm clk_rpm_##_name##_a_clk = { \ .rpm_clk_id = (r_id), \ - .peer = &_platform##_##_name##_clk, \ + .peer = &clk_rpm_##_name##_clk, \ .active_only = true, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ @@ -57,8 +57,8 @@ static const struct clk_parent_data gcc_cxo[] = { }, \ } -#define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, offset) \ - static struct clk_rpm _platform##_##_name##_clk = { \ +#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \ + static struct clk_rpm clk_rpm_##_name##_clk = { \ .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \ .xo_offset = (offset), \ .hw.init = &(struct clk_init_data){ \ @@ -69,8 +69,8 @@ static const struct clk_parent_data gcc_cxo[] = { }, \ } -#define DEFINE_CLK_RPM_FIXED(_platform, _name, r_id, r) \ - static struct clk_rpm _platform##_##_name##_clk = { \ +#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \ + static struct clk_rpm clk_rpm_##_name##_clk = { \ .rpm_clk_id = (r_id), \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ @@ -402,38 +402,48 @@ static const struct clk_ops clk_rpm_ops = { .recalc_rate = clk_rpm_recalc_rate, }; -/* MSM8660/APQ8060 */ -DEFINE_CLK_RPM(msm8660, afab, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, sfab, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, mmfab, QCOM_RPM_MM_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(msm8660, sfpb, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(msm8660, cfpb, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(msm8660, mmfpb, QCOM_RPM_MMFPB_CLK); -DEFINE_CLK_RPM(msm8660, smi, QCOM_RPM_SMI_CLK); -DEFINE_CLK_RPM(msm8660, ebi1, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM_FIXED(msm8660, pll4, QCOM_RPM_PLL_4, 540672000); +DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK); +DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK); +DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK); +DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); +DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK); +DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK); +DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK); +DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK); +DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK); + +DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK); +DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK); +DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK); + +DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000); + +DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0); +DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8); +DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16); +DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24); +DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28); static struct clk_rpm *msm8660_clks[] = { - [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk, - [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk, - [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk, - [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk, - [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk, - [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk, - [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk, - [RPM_SFPB_CLK] = &msm8660_sfpb_clk, - [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk, - [RPM_CFPB_CLK] = &msm8660_cfpb_clk, - [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk, - [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk, - [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk, - [RPM_SMI_CLK] = &msm8660_smi_clk, - [RPM_SMI_A_CLK] = &msm8660_smi_a_clk, - [RPM_EBI1_CLK] = &msm8660_ebi1_clk, - [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk, - [RPM_PLL4_CLK] = &msm8660_pll4_clk, + [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk, + [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk, + [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk, + [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk, + [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk, + [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk, + [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk, + [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk, + [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk, + [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk, + [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk, + [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk, + [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk, + [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk, + [RPM_SMI_CLK] = &clk_rpm_smi_clk, + [RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk, + [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk, + [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk, + [RPM_PLL4_CLK] = &clk_rpm_pll4_clk, }; static const struct rpm_clk_desc rpm_clk_msm8660 = { @@ -441,46 +451,30 @@ static const struct rpm_clk_desc rpm_clk_msm8660 = { .num_clks = ARRAY_SIZE(msm8660_clks), }; -/* apq8064 */ -DEFINE_CLK_RPM(apq8064, afab, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, cfpb, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(apq8064, daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, ebi1, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM(apq8064, mmfab, QCOM_RPM_MM_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, mmfpb, QCOM_RPM_MMFPB_CLK); -DEFINE_CLK_RPM(apq8064, sfab, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(apq8064, sfpb, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(apq8064, qdss, QCOM_RPM_QDSS_CLK); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0, 0); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1, 8); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0, 16); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1, 24); -DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2, 28); - static struct clk_rpm *apq8064_clks[] = { - [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk, - [RPM_CFPB_CLK] = &apq8064_cfpb_clk, - [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk, - [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk, - [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk, - [RPM_EBI1_CLK] = &apq8064_ebi1_clk, - [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk, - [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk, - [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk, - [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk, - [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk, - [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk, - [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk, - [RPM_SFPB_CLK] = &apq8064_sfpb_clk, - [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk, - [RPM_QDSS_CLK] = &apq8064_qdss_clk, - [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk, - [RPM_XO_D0] = &apq8064_xo_d0_clk, - [RPM_XO_D1] = &apq8064_xo_d1_clk, - [RPM_XO_A0] = &apq8064_xo_a0_clk, - [RPM_XO_A1] = &apq8064_xo_a1_clk, - [RPM_XO_A2] = &apq8064_xo_a2_clk, + [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk, + [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk, + [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk, + [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk, + [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk, + [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk, + [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk, + [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk, + [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk, + [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk, + [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk, + [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk, + [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk, + [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk, + [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk, + [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk, + [RPM_QDSS_CLK] = &clk_rpm_qdss_clk, + [RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk, + [RPM_XO_D0] = &clk_rpm_xo_d0_clk, + [RPM_XO_D1] = &clk_rpm_xo_d1_clk, + [RPM_XO_A0] = &clk_rpm_xo_a0_clk, + [RPM_XO_A1] = &clk_rpm_xo_a1_clk, + [RPM_XO_A2] = &clk_rpm_xo_a2_clk, }; static const struct rpm_clk_desc rpm_clk_apq8064 = { @@ -488,33 +482,23 @@ static const struct rpm_clk_desc rpm_clk_apq8064 = { .num_clks = ARRAY_SIZE(apq8064_clks), }; -/* ipq806x */ -DEFINE_CLK_RPM(ipq806x, afab, QCOM_RPM_APPS_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, cfpb, QCOM_RPM_CFPB_CLK); -DEFINE_CLK_RPM(ipq806x, daytona, QCOM_RPM_DAYTONA_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, ebi1, QCOM_RPM_EBI1_CLK); -DEFINE_CLK_RPM(ipq806x, sfab, QCOM_RPM_SYS_FABRIC_CLK); -DEFINE_CLK_RPM(ipq806x, sfpb, QCOM_RPM_SFPB_CLK); -DEFINE_CLK_RPM(ipq806x, nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK); -DEFINE_CLK_RPM(ipq806x, nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK); - static struct clk_rpm *ipq806x_clks[] = { - [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk, - [RPM_CFPB_CLK] = &ipq806x_cfpb_clk, - [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk, - [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk, - [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk, - [RPM_EBI1_CLK] = &ipq806x_ebi1_clk, - [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk, - [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk, - [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk, - [RPM_SFPB_CLK] = &ipq806x_sfpb_clk, - [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk, - [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk, - [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk, - [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk, - [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk, + [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk, + [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk, + [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk, + [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk, + [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk, + [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk, + [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk, + [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk, + [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk, + [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk, + [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk, + [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk, + [RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk, + [RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk, + [RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk, + [RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk, }; static const struct rpm_clk_desc rpm_clk_ipq806x = {