From patchwork Fri Dec 2 09:48:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edmund Berenson X-Patchwork-Id: 13062529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F1A4C4332F for ; Fri, 2 Dec 2022 09:57:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232734AbiLBJ5M (ORCPT ); Fri, 2 Dec 2022 04:57:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232214AbiLBJ5L (ORCPT ); Fri, 2 Dec 2022 04:57:11 -0500 Received: from mx1.emlix.com (mx1.emlix.com [136.243.223.33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53C64CB20C for ; Fri, 2 Dec 2022 01:57:11 -0800 (PST) Received: from mailer.emlix.com (p5098be52.dip0.t-ipconnect.de [80.152.190.82]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.emlix.com (Postfix) with ESMTPS id C25FD5FCDC; Fri, 2 Dec 2022 10:49:20 +0100 (CET) From: Edmund Berenson Cc: Edmund Berenson , Lukasz Zemla , Serge Semin , Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] spi: dw: select SS0 when gpio cs is used Date: Fri, 2 Dec 2022 10:48:59 +0100 Message-Id: <20221202094859.7869-1-edmund.berenson@emlix.com> X-Mailer: git-send-email 2.37.4 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SER register contains only 4-bit bit-field for enabling 4 SPI chip selects. If gpio cs are used the cs number may be >= 4. To ensure we do not write outside of the valid area, we choose SS0 in case of gpio cs to start spi transfer. Co-developed-by: Lukasz Zemla Signed-off-by: Lukasz Zemla Signed-off-by: Edmund Berenson --- drivers/spi/spi-dw-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 99edddf9958b..57c9e384d6d4 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -94,6 +94,10 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) { struct dw_spi *dws = spi_controller_get_devdata(spi->controller); bool cs_high = !!(spi->mode & SPI_CS_HIGH); + u8 enable_cs = 0; + + if (!spi->cs_gpiod) + enable_cs = spi->chip_select; /* * DW SPI controller demands any native CS being set in order to @@ -103,7 +107,7 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) * support active-high or active-low CS level. */ if (cs_high == enable) - dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); + dw_writel(dws, DW_SPI_SER, BIT(enable_cs)); else dw_writel(dws, DW_SPI_SER, 0); } From patchwork Fri Dec 2 09:49:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edmund Berenson X-Patchwork-Id: 13062527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62D7FC4332F for ; Fri, 2 Dec 2022 09:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233161AbiLBJ46 (ORCPT ); Fri, 2 Dec 2022 04:56:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233188AbiLBJ46 (ORCPT ); Fri, 2 Dec 2022 04:56:58 -0500 X-Greylist: delayed 454 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 02 Dec 2022 01:56:56 PST Received: from mx1.emlix.com (mx1.emlix.com [136.243.223.33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3B70CA7A9 for ; Fri, 2 Dec 2022 01:56:56 -0800 (PST) Received: from mailer.emlix.com (p5098be52.dip0.t-ipconnect.de [80.152.190.82]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.emlix.com (Postfix) with ESMTPS id 0E82C5FEEB; Fri, 2 Dec 2022 10:49:28 +0100 (CET) From: Edmund Berenson Cc: Edmund Berenson , Lukasz Zemla , Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] spi: execute set_cs function before gpio cs is activated Date: Fri, 2 Dec 2022 10:49:26 +0100 Message-Id: <20221202094926.9113-1-edmund.berenson@emlix.com> X-Mailer: git-send-email 2.37.4 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In some cases it is necessary to adjust the spi controller configuration before gpio cs is set. For example if spi devices requiring different cpol are used from the same controller the adjustment to cpol has to be made before gpio is activated. To achieve this set_cs should be executed before gpio cs and necessary adjustments can be made inside of controller driver. Suggested-by: Lukasz Zemla Signed-off-by: Edmund Berenson --- drivers/spi/spi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 5f9aedd1f0b6..bf2a67184969 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -976,6 +976,11 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) enable = !enable; if (spi->cs_gpiod) { + /* Some SPI masters need both GPIO CS & slave_select */ + if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && + spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + if (!(spi->mode & SPI_NO_CS)) { /* * Historically ACPI has no means of the GPIO polarity and @@ -993,10 +998,6 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) /* Polarity handled by GPIO library */ gpiod_set_value_cansleep(spi->cs_gpiod, activate); } - /* Some SPI masters need both GPIO CS & slave_select */ - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && - spi->controller->set_cs) - spi->controller->set_cs(spi, !enable); } else if (spi->controller->set_cs) { spi->controller->set_cs(spi, !enable); } From patchwork Fri Dec 2 09:49:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edmund Berenson X-Patchwork-Id: 13062528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F3B6C4332F for ; Fri, 2 Dec 2022 09:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232312AbiLBJ5G (ORCPT ); Fri, 2 Dec 2022 04:57:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232734AbiLBJ5F (ORCPT ); Fri, 2 Dec 2022 04:57:05 -0500 Received: from mx1.emlix.com (mx1.emlix.com [136.243.223.33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BA4FCB223 for ; Fri, 2 Dec 2022 01:57:04 -0800 (PST) Received: from mailer.emlix.com (p5098be52.dip0.t-ipconnect.de [80.152.190.82]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.emlix.com (Postfix) with ESMTPS id C60E05FF10; Fri, 2 Dec 2022 10:49:35 +0100 (CET) From: Edmund Berenson Cc: Edmund Berenson , Lukasz Zemla , Serge Semin , Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] spi: dw: Write chip configuration before cs is set Date: Fri, 2 Dec 2022 10:49:34 +0100 Message-Id: <20221202094934.9420-1-edmund.berenson@emlix.com> X-Mailer: git-send-email 2.37.4 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Using chips with different cpol, causes first communication to fail on cpol change. To avoid this issue write cr0 register before cs is set. Suggested-by: Lukasz Zemla Signed-off-by: Edmund Berenson --- drivers/spi/spi-dw-core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 57c9e384d6d4..c3da4fe3e510 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -93,6 +93,7 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws) void dw_spi_set_cs(struct spi_device *spi, bool enable) { struct dw_spi *dws = spi_controller_get_devdata(spi->controller); + struct dw_spi_chip_data *chip = spi_get_ctldata(spi); bool cs_high = !!(spi->mode & SPI_CS_HIGH); u8 enable_cs = 0; @@ -106,8 +107,13 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) * Enable register no matter whether the SPI core is configured to * support active-high or active-low CS level. */ - if (cs_high == enable) + if (cs_high == enable) { + dw_spi_enable_chip(dws, 0); + dw_writel(dws, DW_SPI_CTRLR0, chip->cr0); + dw_spi_enable_chip(dws, 1); + dw_writel(dws, DW_SPI_SER, BIT(enable_cs)); + } else dw_writel(dws, DW_SPI_SER, 0); }