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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:19 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang Subject: [PATCH 01/32] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Date: Sun, 4 Dec 2022 20:05:22 +0100 Message-Id: <20221204190553.3274-2-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-2-philmd@linaro.org> Reviewed-by: Igor Mammedov --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c0a2e0ab04..9bffa1b128 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -71,6 +71,8 @@ #define FLASH_SIZE 0x400000 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1401,7 +1403,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, + piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true, TYPE_PIIX4_PCI_DEVICE); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); From patchwork Sun Dec 4 19:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BB82C47089 for ; Sun, 4 Dec 2022 19:18:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKl-0001jc-LF; Sun, 04 Dec 2022 14:07:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKk-0001in-76; Sun, 04 Dec 2022 14:07:26 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKi-0001a5-JC; Sun, 04 Dec 2022 14:07:25 -0500 Received: by mail-ej1-x62f.google.com with SMTP id qk9so5324864ejc.3; Sun, 04 Dec 2022 11:07:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lMFMoTtlMr7+uTcURApX//gZTvt+E84r/Dv7wPElE8g=; b=e5l0A+4tHEoqO9ceF5Br/exmaFFAsQSeXYpYsjnzikV1GFy9bz7l84LsUJewnO3r+v VCdNldpu05Py4g/hHD+FPi861amrZknmM6P+2Z2LofSGu1pAXHaxNPb/SWLA9VTZP1eq kN+o4y+jTuRlgOt1N7g+NL9krGo01GH2tZnNamcX/zxhTEJ0Pr81eJdi4+YfxCqYNxvP 70Jmva4KFc8iokesWIjMrETHP81hVmmk/PF4BbQ5aHSInctY2FHCAiBA2fP9WP98JSNF ht7mEqYECv4eLj+7CC/O6dlJKQCpq2jRV9VPEjs6opVBYsFsUdMAJAiPufayCBdQOWpJ RcWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lMFMoTtlMr7+uTcURApX//gZTvt+E84r/Dv7wPElE8g=; b=SekcJU1oOAGCzWO/8UKq/dmXqBH/NiqwoQim+DuMBppua8OobYcEnJUmrR48Z7XY+T qUvMPzC+3AbWPP7ygosH5ef1OBy8CocKWlXYmUr4O6F0TFGn2FaSwg/xvLHJluaDRC7w 2WamPB/AlKiWTIxB0yBgb1GDIhaomwWTuWyjePwKEzPNEUcWyHClmqS4y4IL6Wc21lRo LAJaKeDuPbcO9VjqnSXXN3K+vW57WlQEkPHGTYQPSoSzXDQ6fcozHlL4uJsXHy6TVOzW 6nJ7I220LIuVArk5GOGVRQK5dO9toG+B3N4lbGdkdC/C+Vl3U/AxYSsZhzUgkItvf/yu iPpA== X-Gm-Message-State: ANoB5plxxqeVoEsyflSMD7XyDHUY8xjOu1XRf8aNw+KnWvpSkytK17ig WiaJDhSNRKz2Gve/MQOGM87mPR2f/g8= X-Google-Smtp-Source: AA0mqf7H1myBkC6yIQim18+SOKXBEikch5X9ZUhlg+tiLJumQcS6s6UPkCUUXQ1O3hG28d14qAUOxw== X-Received: by 2002:a17:906:6a8e:b0:78d:a136:7332 with SMTP id p14-20020a1709066a8e00b0078da1367332mr66002516ejr.355.1670180841734; Sun, 04 Dec 2022 11:07:21 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:21 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang Subject: [PATCH 02/32] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Sun, 4 Dec 2022 20:05:23 +0100 Message-Id: <20221204190553.3274-3-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-3-philmd@linaro.org> --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9bffa1b128..c3dcd43f37 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -803,6 +803,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); @@ -840,6 +842,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; /* Small bootloader */ @@ -914,6 +919,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* From patchwork Sun Dec 4 19:05:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36595C47089 for ; Sun, 4 Dec 2022 19:18:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKn-0001kv-6o; Sun, 04 Dec 2022 14:07:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKl-0001jU-9x; Sun, 04 Dec 2022 14:07:27 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKj-0001aW-TB; Sun, 04 Dec 2022 14:07:27 -0500 Received: by mail-ed1-x531.google.com with SMTP id m19so13032970edj.8; Sun, 04 Dec 2022 11:07:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UICViTJnHcQeaPYE3gN3Gm3w5DqlM81wlE2s7yBTyiA=; b=LLJLigkdA/HS2uZKgchUv31zw7VCEVYbolRx2Pr9Wns9YcYRn3nnqGo2IRatvDfCPq mxrGhlxmT81/xrFM78nO2UhNUK6owZKrzm7WII659nh4/B+TsvJCom0ulTjz+/kLSGlU 82W+fLOSaWSOjQ4ZBnHcDyfbr09TYRph7TSir7MUvRl8n+a0QcXXO7Wo/oy6PlJM4bm8 QwKGl0CiH3No7PZhfyigOm54lvSWZ0CLxDrUU+53A2q0fohpaxDu+DGbVAvNcimbo5Tn LJQ1i/5yhQ8QuDWXcbR9hOVrhG/YzWuCIj1A3oAyk2111O8X149N94Qh47GwC/O4nize PRag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UICViTJnHcQeaPYE3gN3Gm3w5DqlM81wlE2s7yBTyiA=; b=xNa/6r6ol1ZMqPKaaO9sgw6w87IW8cf9hHgYegt3gwQu3jkmMyT6wMF+VStw445Kms csMark9n3jzQzHA1erWXMGKDaJQmcfOkjQ8C6+85U5wWRtc0tia2fQKF+ahXw6UdyQWq 6DNOznJoaOtIVp2sBUNDeuhFlan/ofVSJcBZVPhSbkian4EZs5GCXf9YUPdsY0x3wQ0n EppwIn3DEg/699THDa2HhDnjdBMuXbeWIh6FpD3jMAYMtDBynAkE0MfMvlK4BRtzD4HU CThOK5L2JJp3iUyp7h8YC/BlrbvIId6hgoxDNQiLL6URsyhaauqUjaNe8a9GF/pntBLv 3z7A== X-Gm-Message-State: ANoB5pn3QYPl4HxBHm9scSVL1QrPkOwbMTHyhhCZiJFmxfvNQFLZ4QK5 alsk6OhHT+7a7J3qrugOGTbzEjFB4I8= X-Google-Smtp-Source: AA0mqf5lpmEafSc5J5puKhkpUJFggHIIAdjVWGGBwF54i3b8eaPxQsbqdAUaqGAo/0SRglPhTCrzvA== X-Received: by 2002:a05:6402:d6:b0:458:b42e:46e6 with SMTP id i22-20020a05640200d600b00458b42e46e6mr71724753edu.375.1670180843449; Sun, 04 Dec 2022 11:07:23 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:23 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang Subject: [PATCH 03/32] hw/isa/piix4: Correct IRQRC[A:D] reset values Date: Sun, 4 Dec 2022 20:05:24 +0100 Message-Id: <20221204190553.3274-4-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-4-philmd@linaro.org> --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8fc1db6dc9..0d23e11a39 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -116,10 +116,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] = 0x80; + pci_conf[0x61] = 0x80; + pci_conf[0x62] = 0x80; + pci_conf[0x63] = 0x80; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; From patchwork Sun Dec 4 19:05:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CB38C4321E for ; Sun, 4 Dec 2022 19:19:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKn-0001kz-IH; Sun, 04 Dec 2022 14:07:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKm-0001kI-M7; Sun, 04 Dec 2022 14:07:28 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKl-0001bf-72; Sun, 04 Dec 2022 14:07:28 -0500 Received: by mail-ej1-x62f.google.com with SMTP id ml11so23088232ejb.6; Sun, 04 Dec 2022 11:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CmkH8CbbCM2o782sBEukQ8ETWoFsxaO7vlWTDApTAUc=; b=TRzYrq1B48Ga5KU02Eh97MTjX0uBN/OQx3eMXN+jlEoo/PN0CB6cX/vJ0hlObmXkUR x1MqZnYLe1hBLAjOAmTUMagtffly0/CqfKCpDc0OVBwN7MO5AUX4SPdUkhlNiN9QqPqI I0BiVPppG2HwhHy62gco7XJ6CG0IAeSONOxj6EMm55yrNr483DghGvUboOHhtpXGx0aw Ns0anl/MrDzpHhHU/+HGzU9gIMgWOkXb4MLQZtpcIVqiapJ/BQEE4qUbpJGInSkFOdf0 MsDFN0BZOorspmFWueO2aTkBSYlVD/nW3gmio/5peg5LE4LLa6rFy/ODFYbqD4npV0Pu glag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CmkH8CbbCM2o782sBEukQ8ETWoFsxaO7vlWTDApTAUc=; b=vP/Ifu5xjazBIxbcigXzMLnGgLgYygAvrgzMmw4LaEOKfW1PctJ5YvOcAK1CqoMjkW eQ6XcgOBOmkHb+LwoO/mKHd/XXV8t6GN4PDEGsPDt7moohKAizl3x2fAwFiLVdO+umFu qJUcYM8bBERK686O69ihhTqcGzwlwMifb2IdmhxBX6VY51hhpc1TIcP3hC8mLvSSkiYY TtFeCCWy7189qGepAwzNW9Ai7AZwFLIcgDnKJnOg+TeM/K0afTRbaI5l/zakXJ2LEnHz uAOV1cRG4TXb/iCGDsg5U4dVm01PY/HeYhh34akcQM7SnHqEwq9CGbfLUzGo4s5GQNfD gqrA== X-Gm-Message-State: ANoB5pmyNNFXnIz9OXVtKDVHMMLLRx9G0mE45Hor4wvAQKM2u4gu4kgY LXOBSajz5H/bd2jfFoVhFrkSX2C5ASs= X-Google-Smtp-Source: AA0mqf400dXTwpmfT69Qwkfdd7yNwz4vW8q6cRa5Ff5nTjNTAprJAzPGfq+fohf6pIBGn/a71nR/cA== X-Received: by 2002:a17:906:6703:b0:7ae:5dd6:e62d with SMTP id a3-20020a170906670300b007ae5dd6e62dmr56697204ejp.518.1670180845029; Sun, 04 Dec 2022 11:07:25 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:24 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 04/32] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig Date: Sun, 4 Dec 2022 20:05:25 +0100 Message-Id: <20221204190553.3274-5-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- configs/devices/mips-softmmu/common.mak | 2 -- hw/mips/Kconfig | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index 416161f833..7813fd1b41 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -18,10 +18,8 @@ CONFIG_PCSPK=y CONFIG_PCKBD=y CONFIG_FDC=y CONFIG_ACPI=y -CONFIG_ACPI_PIIX4=y CONFIG_APM=y CONFIG_I8257=y -CONFIG_PIIX4=y CONFIG_IDE_ISA=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 725525358d..4e7042f03d 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,6 +1,7 @@ config MALTA bool select ISA_SUPERIO + select PIIX4 config MIPSSIM bool From patchwork Sun Dec 4 19:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E0FAC4321E for ; Sun, 4 Dec 2022 19:13:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKq-0001ln-6i; Sun, 04 Dec 2022 14:07:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKo-0001lG-KL; Sun, 04 Dec 2022 14:07:30 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKn-0001c1-3w; Sun, 04 Dec 2022 14:07:30 -0500 Received: by mail-ej1-x62e.google.com with SMTP id fc4so16119554ejc.12; Sun, 04 Dec 2022 11:07:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oKpijhmAXOPvV4zJYeFTakq7e6VfIrSbYOidvRCdJEA=; b=f4Ls+kTcvPkReg3UHW194yTX95PQP/+d3eOMPDweIKBblnW+irQpO90FprVO4z/Lko LOfT8E66Rqq0m9wQ93t2htUFgbfkWWmLRJYk49N5V3IPmubgH+MtAFOxSsGEI/UOaD7B fiwv1cduclHRqSzNTUEBEz/LcC+5jUgkX0IGuBI7l1W2FrvqQtamvRR/wUa2OtzXuaeX V4Nbh3lLrOKLtIhIYfYDcanZNebwl/JhPG8lHWnVyvi5m3cemo3qraLLgRiKKcUReB+9 HfZqVvcYyUlUGrwPNEieFHW/gbZ6Hrn6PDXnWphCWHwPAbjQrSzZApED1kYBPRVJwmet DWEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oKpijhmAXOPvV4zJYeFTakq7e6VfIrSbYOidvRCdJEA=; b=0vvRKoEfUegIrWUryeC/H9E9fPgkacFxsORU5sO36OGnS2+wa2Q47KYkevRb5sImx9 6xnt2dn357n+hsLo2kQ80Cedu189Z9sdKbokWpH5Tb1O1Exao7RJC823/AUK1Oo6iKqh 6PEmpJcokypxfN5jsND+1nhFAIxFBUI0pugxvaL1isu9g8lB+/DQIvwm7cc59CZwqFsf VRiBSrUgx2JNfwPa42+0+a7wTuSyL1VuoyzoNTwYsfEdh6sOU9cYad4vJ4MWjdzpiLNP uBzQ04AOXhoaM+TYyFtmg5A5NHZd9Kp96zPWSpv9CwfTDEUqiDICb57NR1RFCau0MI2f zk/Q== X-Gm-Message-State: ANoB5pnYVKlgAtMyZU9j5Euh+VkUUlbMorQ/JMsb610pgg9hNDOnDqU6 g9EB0D5hBHu0wqqmH5xZ8LAaYXqQutE= X-Google-Smtp-Source: AA0mqf4+WHuRtMGrZQ++ylJps/mjUoVNK4eib7uAt8NH4m0xjTMWbmhL3XnRf7c05Cjt5SMMcUTlUA== X-Received: by 2002:a17:907:1b0a:b0:7c0:fa5f:a032 with SMTP id mp10-20020a1709071b0a00b007c0fa5fa032mr128893ejc.112.1670180847022; Sun, 04 Dec 2022 11:07:27 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:26 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow , Peter Maydell Subject: [PATCH 05/32] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Date: Sun, 4 Dec 2022 20:05:26 +0100 Message-Id: <20221204190553.3274-6-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Message-Id: <20221022150508.26830-3-shentey@gmail.com> --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0ad0ed1603..e26509a935 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -218,7 +218,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + pci_dev = pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; From patchwork Sun Dec 4 19:05:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30B21C4321E for ; Sun, 4 Dec 2022 19:16:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKr-0001mY-Bo; Sun, 04 Dec 2022 14:07:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKq-0001mD-Lz; Sun, 04 Dec 2022 14:07:32 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKo-0001cG-JT; Sun, 04 Dec 2022 14:07:32 -0500 Received: by mail-ej1-x632.google.com with SMTP id n20so23134038ejh.0; Sun, 04 Dec 2022 11:07:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJq1Ucn+VVeqqpkB9YPt71C5Kv2BL3f3dT/zXJbfztA=; b=jOrsPvNNs+N3jml49k5FhH6urggBqYyLn+vfXCo/3qzSSNT2krNuspCIIlEIZEfgKR l7kr4EVXj4vu0rhOjfZScjmFWcjc9AMt83ekC1pYdW1nAe+X4wljzjXHrsMA8JRGwLxJ wdTJrfHdF2N7kz/SEt3AMB4NzR2ZJ4fGH1FnMm+98nVm9b85p8UdpjCsyAWIuGqFJr76 T2NGaAJNDhqDnQOEzzBeTkSWIh7Kn0+dSEGNgxm0jgZ19A5K/esedyOo4VNk/gzvkVcB 5oGvGwFzYDqymxTS9WP6gY0csHvODAZIeixICda6WyoikoPNJrQ65e3R/hknqswTW6WX 3nVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJq1Ucn+VVeqqpkB9YPt71C5Kv2BL3f3dT/zXJbfztA=; b=RegCwsFPRLN7Ezf6HDaIEOBKcRZdYFa5uHb2Kzl5bAoj9x0zOMsx1LO1DxaDSdi5+m h7vPraJUYyS+iJt2E59c8hPR/X5geOAbr9BL3MRGgfOvtcHh/Uv9mnDt2kFJbjZ2L5XY NEwNYFaB186Bx2qrdr2IGxg4Jzw65ntPIAMYg+2mnbAMmlxkQrK8xULb6BLTH+S7dprn wgnT1/bub0ZCE4jTHs3qDHk+17kVxUMU6SDYz50VpYCMxolIDCfjB95PGsU+AMvBOyPW NiWPy8FR5GGc/UTFrpnJqQaoshE0U2bSWLh8X389Xa/FLJm3QMrySoRy+kxBX7ScS2P7 69Xw== X-Gm-Message-State: ANoB5pmIz/ImWl3RzzX8PG97+twrTzWQUtl9J29gebTReay6ZoYQp0VS dWQQvOK15PRO7NtoqxZ0QQjnrU6umsg= X-Google-Smtp-Source: AA0mqf4ECkIsmGaNXwEe3nxnrLjEh06euKbWBout3QHLgdOt8j0jTsxs42Jqkv9oqWgqQ0/kripjHg== X-Received: by 2002:a17:907:8749:b0:7c0:7c6c:d484 with SMTP id qo9-20020a170907874900b007c07c6cd484mr1300399ejc.752.1670180848703; Sun, 04 Dec 2022 11:07:28 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:28 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH 06/32] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Date: Sun, 4 Dec 2022 20:05:27 +0100 Message-Id: <20221204190553.3274-7-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=shentey@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-10-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 3 ++- hw/i386/pc_q35.c | 13 +++++++------ hw/isa/piix4.c | 2 +- hw/usb/hcd-uhci.c | 16 ++++++++-------- hw/usb/hcd-uhci.h | 4 ++++ 5 files changed, 22 insertions(+), 16 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index e26509a935..caa983d76e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -50,6 +50,7 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -291,7 +292,7 @@ static void pc_init1(MachineState *machine, #endif if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); + pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); } if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a496bd6e74..1da6d34339 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -48,6 +48,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -65,15 +66,15 @@ struct ehci_companions { }; static const struct ehci_companions ich9_1d[] = { - { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, - { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, - { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, + { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, + { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, + { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, }; static const struct ehci_companions ich9_1a[] = { - { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, - { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, - { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, + { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, + { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, + { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, }; static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 0d23e11a39..aceb21ee3e 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -280,7 +280,7 @@ static void piix4_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci"); + object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index d1b5657d72..30ae0104bb 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1292,56 +1292,56 @@ void uhci_data_class_init(ObjectClass *klass, void *data) static UHCIInfo uhci_info[] = { { - .name = "piix3-usb-uhci", + .name = TYPE_PIIX3_USB_UHCI, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, .revision = 0x01, .irq_pin = 3, .unplug = true, },{ - .name = "piix4-usb-uhci", + .name = TYPE_PIIX4_USB_UHCI, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, .revision = 0x01, .irq_pin = 3, .unplug = true, },{ - .name = "ich9-usb-uhci1", /* 00:1d.0 */ + .name = TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, .revision = 0x03, .irq_pin = 0, .unplug = false, },{ - .name = "ich9-usb-uhci2", /* 00:1d.1 */ + .name = TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, .revision = 0x03, .irq_pin = 1, .unplug = false, },{ - .name = "ich9-usb-uhci3", /* 00:1d.2 */ + .name = TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, .revision = 0x03, .irq_pin = 2, .unplug = false, },{ - .name = "ich9-usb-uhci4", /* 00:1a.0 */ + .name = TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, .revision = 0x03, .irq_pin = 0, .unplug = false, },{ - .name = "ich9-usb-uhci5", /* 00:1a.1 */ + .name = TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, .revision = 0x03, .irq_pin = 1, .unplug = false, },{ - .name = "ich9-usb-uhci6", /* 00:1a.2 */ + .name = TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, .revision = 0x03, diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index c85ab7868e..83e6f548b1 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -91,4 +91,8 @@ typedef struct UHCIInfo { void uhci_data_class_init(ObjectClass *klass, void *data); void usb_uhci_common_realize(PCIDevice *dev, Error **errp); +#define TYPE_PIIX3_USB_UHCI "piix3-usb-uhci" +#define TYPE_PIIX4_USB_UHCI "piix4-usb-uhci" +#define TYPE_ICH9_USB_UHCI(fn) "ich9-usb-uhci" #fn + #endif From patchwork Sun Dec 4 19:05:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06125C47089 for ; Sun, 4 Dec 2022 19:17:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKt-0001nk-Qa; Sun, 04 Dec 2022 14:07:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKs-0001n5-IV; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:29 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 07/32] hw/i386/pc: Create RTC controllers in south bridges Date: Sun, 4 Dec 2022 20:05:28 +0100 Message-Id: <20221204190553.3274-8-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Just like in the real hardware (and in PIIX4), create the RTC controllers in the south bridges. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-11-shentey@gmail.com> --- hw/i386/pc.c | 12 +++++++++++- hw/i386/pc_piix.c | 8 ++++++++ hw/i386/pc_q35.c | 1 + hw/isa/Kconfig | 2 ++ hw/isa/lpc_ich9.c | 8 ++++++++ hw/isa/piix3.c | 15 +++++++++++++++ include/hw/i386/ich9.h | 2 ++ include/hw/southbridge/piix.h | 3 +++ 8 files changed, 50 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 546b703cb4..9379cf4374 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1299,7 +1299,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + if (rtc_irq) { + qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + } else { + uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + "irq", + &error_fatal); + isa_connect_gpio_out(*rtc_state, 0, irq); + } + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + "date"); qemu_register_boot_set(pc_boot_set, *rtc_state); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index caa983d76e..7de2f1092b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -32,6 +32,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" @@ -225,10 +226,17 @@ static void pc_init1(MachineState *machine, piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), + "rtc")); } else { pci_bus = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + + rtc_state = isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); + isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 1da6d34339..b5cd876dc2 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -239,6 +239,7 @@ static void pc_q35_init(MachineState *machine) lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 18b5c6bf3f..af5ec9cd61 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select I8257 select ISA_BUS + select MC146818RTC config PIIX4 bool @@ -79,3 +80,4 @@ config LPC_ICH9 select ISA_BUS select ACPI_SMBUS select ACPI_X86_ICH + select MC146818RTC diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 6c44cc9767..eb230a1a23 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -660,6 +660,8 @@ static void ich9_lpc_initfn(Object *obj) static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; + object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); + object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, @@ -725,6 +727,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, lpc->gsi); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { + return; + } } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index eabad7ba58..c68e51ddad 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -28,6 +28,7 @@ #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" @@ -312,6 +313,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { + return; + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -338,6 +345,13 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } +static void pci_piix3_init(Object *obj) +{ + PIIX3State *d = PIIX3_PCI_DEVICE(obj); + + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); +} + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -364,6 +378,7 @@ static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIX3State), + .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 23ee8e371b..672efc6bce 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -11,6 +11,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/rtc/mc146818rtc.h" #include "qom/object.h" void ich9_lpc_set_irq(void *opaque, int irq_num, int level); @@ -39,6 +40,7 @@ struct ICH9LPCState { */ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; + RTCState rtc; APMState apm; ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 2693778b23..b1fa08dd2b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/rtc/mc146818rtc.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -52,6 +53,8 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + RTCState rtc; + /* Reset Control Register contents */ uint8_t rcr; From patchwork Sun Dec 4 19:05:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EFB6C4321E for ; Sun, 4 Dec 2022 19:14:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uKv-0001oI-4H; Sun, 04 Dec 2022 14:07:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uKt-0001nl-RQ; Sun, 04 Dec 2022 14:07:35 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKs-0001cz-9B; Sun, 04 Dec 2022 14:07:35 -0500 Received: by mail-ej1-x62d.google.com with SMTP id x22so705455ejs.11; Sun, 04 Dec 2022 11:07:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kts3SFClrINDqhVllIjfmvy1KSDpg0aYdMA7IUaZF3E=; b=OS+iyM/N/NVmS8YF5WUNOtTO/qpAZkgA9J5kyf+qlCn0uDYmsZkHLOsr/tGqGo9+y+ ctMyVtKjh+QeVg/Bit3PCqO7lLjeNAFDahjyj8C0/UeeYsIiokC1mIX0WyrrW0tVCt5i 5rvtkXTQZZvkCGpuCOe1D3FvMC68JU85l3BJNkQjjXjMaUqy17XLZYaBd0QxWLBqugEt wR0KRLICpJaicjE3riAKZj3lum29MfSqKC9QAZo+O0DKPfjvNzPzo+N17bfb+sKFf/vO mb5r/ll0m8k6bcgF+ihPzvZ+MN9o3yTaBBfZpbkAd/CllqHZHe8sLfiFddYhS4Dxeu2o bnkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kts3SFClrINDqhVllIjfmvy1KSDpg0aYdMA7IUaZF3E=; b=QokfRgv9SOmcPt7biSEbeIEztswNXrUlWivB9V3oA9/9zWOkuECuYN7SvK+UQRVVRz FKDP9ndfNuT1yARfKu7YuX+KsMTfHKWK2oXSb+AE6ynNNELJfF919RQtxCUVt6Od16oR b4HM4VCHGxK2FqRaOGZmi9JtA76wBWb6tjfqeIhPZJ8d7cuVBQDjsxXZ7dMamaz0MSSd Vfzhe1lcPH8yQz/lcAVXFz31QYWk5XnpuXNdqquLDhcU2BqMe0gZ2+dgd+sNPRjUaGFN 9cDSPr4BQn7gMl6DGX3KoKQ5WgTuHn8m8Dj+SIvFS+4YXKsb9KNtS747t9AmZb4vhWCR wQXQ== X-Gm-Message-State: ANoB5pn/5aJU/2D3K44a+kahSA0Om7ZD5TFpcb9YvbBrAV9hO5QWAu/7 pvzYWLAdt8pS0TR1g6rTFSBjnJSP0xY= X-Google-Smtp-Source: AA0mqf5L9ViAK0x+Md99bVnn2IhWjkDsW5cKY2VbDCtbXk+tpQARodSyYHQ+0enuLLjG2mBiLbq+0w== X-Received: by 2002:a17:906:6dc9:b0:7bc:5700:490 with SMTP id j9-20020a1709066dc900b007bc57000490mr36085116ejt.592.1670180852356; Sun, 04 Dec 2022 11:07:32 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:31 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow , Peter Maydell Subject: [PATCH 08/32] hw/i386/pc: No need for rtc_state to be an out-parameter Date: Sun, 4 Dec 2022 20:05:29 +0100 Message-Id: <20221204190553.3274-9-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that the RTC is created as part of the southbridges it doesn't need to be an out-parameter any longer. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Message-Id: <20221022150508.26830-12-shentey@gmail.com> --- hw/i386/pc.c | 12 ++++++------ hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- include/hw/i386/pc.h | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9379cf4374..beb5f4d313 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1246,7 +1246,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs) { @@ -1301,17 +1301,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, } if (rtc_irq) { - qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); } else { - uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + uint32_t irq = object_property_get_uint(OBJECT(rtc_state), "irq", &error_fatal); - isa_connect_gpio_out(*rtc_state, 0, irq); + isa_connect_gpio_out(rtc_state, 0, irq); } - object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), "date"); - qemu_register_boot_set(pc_boot_set, *rtc_state); + qemu_register_boot_set(pc_boot_set, rtc_state); if (!xen_enabled() && (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7de2f1092b..b97bff5674 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -262,7 +262,7 @@ static void pc_init1(MachineState *machine, } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, true, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, 0x4); pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index b5cd876dc2..c88f4448d9 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -293,7 +293,7 @@ static void pc_q35_init(MachineState *machine) } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 0xff0104); /* connect pm stuff to lpc */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c95333514e..0cf3ccdf0d 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -169,7 +169,7 @@ uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs); void pc_cmos_init(PCMachineState *pcms, From patchwork Sun Dec 4 19:05:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1565C47089 for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:34 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 09/32] hw/isa/piix3: Create USB controller in host device Date: Sun, 4 Dec 2022 20:05:30 +0100 Message-Id: <20221204190553.3274-10-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-13-shentey@gmail.com> --- hw/i386/pc_piix.c | 7 ++----- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 17 +++++++++++++++++ include/hw/southbridge/piix.h | 4 ++++ 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b97bff5674..22c1c5404c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -51,7 +51,6 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -221,6 +220,8 @@ static void pc_init1(MachineState *machine, pcms->bus = pci_bus; pci_dev = pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -299,10 +300,6 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { PCIDevice *piix4_pm; diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index af5ec9cd61..97b8ea7c06 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select USB_UHCI config PIIX4 bool diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index c68e51ddad..af1c5b9859 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -299,6 +299,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev), @@ -319,6 +320,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { return; } + + /* USB */ + if (d->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, + TYPE_PIIX3_USB_UHCI); + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -352,6 +363,11 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } +static Property pci_piix3_props[] = { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -371,6 +387,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml = build_pci_isa_aml; } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b1fa08dd2b..5367917182 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:36 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 10/32] hw/isa/piix3: Create power management controller in host device Date: Sun, 4 Dec 2022 20:05:31 +0100 Message-Id: <20221204190553.3274-11-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The power management controller is an integral part of PIIX3 (function 3). So create it as part of the south bridge. Note that the ACPI function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-14-shentey@gmail.com> --- hw/i386/pc_piix.c | 23 +++++++++++++---------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 14 ++++++++++++++ include/hw/southbridge/piix.h | 6 ++++++ 4 files changed, 34 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 22c1c5404c..c96d989636 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -46,11 +46,11 @@ #include "sysemu/kvm.h" #include "hw/kvm/clock.h" #include "hw/sysbus.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -85,6 +85,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *system_io = get_system_io(); PCIBus *pci_bus; ISABus *isa_bus; + Object *piix4_pm; int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; @@ -222,6 +223,13 @@ static void pc_init1(MachineState *machine, pci_dev = pci_new_multifunction(-1, true, type); object_property_set_bool(OBJECT(pci_dev), "has-usb", machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -229,8 +237,10 @@ static void pc_init1(MachineState *machine, isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); + piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus = NULL; + piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); @@ -300,15 +310,8 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { - PCIDevice *piix4_pm; - + if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); - qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); @@ -322,7 +325,7 @@ static void pc_init1(MachineState *machine, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, - OBJECT(piix4_pm), &error_abort); + piix4_pm, &error_abort); } if (machine->nvdimms_state->is_enabled) { diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 97b8ea7c06..6c154d88c7 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 config PIIX3 bool + select ACPI_PIIX4 select I8257 select ISA_BUS select MC146818RTC diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index af1c5b9859..cb2d9285ae 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -330,6 +330,17 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } } + + /* Power Management */ + if (d->has_acpi) { + object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base); + qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled); + if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -364,7 +375,10 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix3_props[] = { + DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 5367917182..1c291cc954 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,9 @@ struct PIIXState { RTCState rtc; UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; /* Reset Control Register contents */ uint8_t rcr; @@ -63,7 +67,9 @@ struct PIIXState { /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + bool has_acpi; bool has_usb; + bool smm_enabled; }; typedef struct PIIXState PIIX3State; From patchwork Sun Dec 4 19:05:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 721C5C4321E for ; Sun, 4 Dec 2022 19:10:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uL2-0001uu-Dm; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:37 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 11/32] hw/core: Introduce proxy-pic Date: Sun, 4 Dec 2022 20:05:32 +0100 Message-Id: <20221204190553.3274-12-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Having a proxy PIC allows for ISA PICs to be created and wired up in southbridges. This is especially useful for PIIX3 for two reasons: First, the southbridge doesn't need to care about the virtualization technology used (KVM, TCG, Xen) due to in-IRQs (where devices get attached) and out-IRQs (which will trigger the IRQs of the respective virtzalization technology) are separated. Second, since the in-IRQs are populated with fully initialized qemu_irq's, they can already be wired up inside PIIX3. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-15-shentey@gmail.com> --- MAINTAINERS | 2 ++ hw/core/Kconfig | 3 ++ hw/core/meson.build | 1 + hw/core/proxy-pic.c | 70 +++++++++++++++++++++++++++++++++++++ include/hw/core/proxy-pic.h | 54 ++++++++++++++++++++++++++++ 5 files changed, 130 insertions(+) create mode 100644 hw/core/proxy-pic.c create mode 100644 include/hw/core/proxy-pic.h diff --git a/MAINTAINERS b/MAINTAINERS index 6966490c94..b33fc7e091 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1660,6 +1660,7 @@ S: Supported F: hw/char/debugcon.c F: hw/char/parallel* F: hw/char/serial* +F: hw/core/proxy-pic.c F: hw/dma/i8257* F: hw/i2c/pm_smbus.c F: hw/input/pckbd.c @@ -1676,6 +1677,7 @@ F: hw/watchdog/wdt_ib700.c F: hw/watchdog/wdt_i6300esb.c F: include/hw/display/vga.h F: include/hw/char/parallel.h +F: include/hw/core/proxy-pic.h F: include/hw/dma/i8257.h F: include/hw/i2c/pm_smbus.h F: include/hw/input/i8042.h diff --git a/hw/core/Kconfig b/hw/core/Kconfig index 9397503656..a7224f4ca0 100644 --- a/hw/core/Kconfig +++ b/hw/core/Kconfig @@ -22,6 +22,9 @@ config OR_IRQ config PLATFORM_BUS bool +config PROXY_PIC + bool + config REGISTER bool diff --git a/hw/core/meson.build b/hw/core/meson.build index 7a4d02b6c0..e86aef6ec3 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -30,6 +30,7 @@ softmmu_ss.add(when: ['CONFIG_GUEST_LOADER', fdt], if_true: files('guest-loader. softmmu_ss.add(when: 'CONFIG_OR_IRQ', if_true: files('or-irq.c')) softmmu_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('platform-bus.c')) softmmu_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c')) +softmmu_ss.add(when: 'CONFIG_PROXY_PIC', if_true: files('proxy-pic.c')) softmmu_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c')) softmmu_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c')) softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c')) diff --git a/hw/core/proxy-pic.c b/hw/core/proxy-pic.c new file mode 100644 index 0000000000..3251727d19 --- /dev/null +++ b/hw/core/proxy-pic.c @@ -0,0 +1,70 @@ +/* + * Proxy interrupt controller device. + * + * Copyright (c) 2022 Bernhard Beschow + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/core/proxy-pic.h" + +static void proxy_pic_set_irq(void *opaque, int irq, int level) +{ + ProxyPICState *s = opaque; + + qemu_set_irq(s->out_irqs[irq], level); +} + +static void proxy_pic_realize(DeviceState *dev, Error **errp) +{ + ProxyPICState *s = PROXY_PIC(dev); + + qdev_init_gpio_in(DEVICE(s), proxy_pic_set_irq, MAX_PROXY_PIC_LINES); + qdev_init_gpio_out(DEVICE(s), s->out_irqs, MAX_PROXY_PIC_LINES); + + for (int i = 0; i < MAX_PROXY_PIC_LINES; ++i) { + s->in_irqs[i] = qdev_get_gpio_in(DEVICE(s), i); + } +} + +static void proxy_pic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + /* No state to reset or migrate */ + dc->realize = proxy_pic_realize; + + /* Reason: Needs to be wired up to work */ + dc->user_creatable = false; +} + +static const TypeInfo proxy_pic_info = { + .name = TYPE_PROXY_PIC, + .parent = TYPE_DEVICE, + .instance_size = sizeof(ProxyPICState), + .class_init = proxy_pic_class_init, +}; + +static void split_irq_register_types(void) +{ + type_register_static(&proxy_pic_info); +} + +type_init(split_irq_register_types) diff --git a/include/hw/core/proxy-pic.h b/include/hw/core/proxy-pic.h new file mode 100644 index 0000000000..0eb40c478a --- /dev/null +++ b/include/hw/core/proxy-pic.h @@ -0,0 +1,54 @@ +/* + * Proxy interrupt controller device. + * + * Copyright (c) 2022 Bernhard Beschow + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_PROXY_PIC_H +#define HW_PROXY_PIC_H + +#include "hw/qdev-core.h" +#include "qom/object.h" +#include "hw/irq.h" + +#define TYPE_PROXY_PIC "proxy-pic" +OBJECT_DECLARE_SIMPLE_TYPE(ProxyPICState, PROXY_PIC) + +#define MAX_PROXY_PIC_LINES 16 + +/** + * This is a simple device which has 16 pairs of GPIO input and output lines. + * Any change on an input line is forwarded to the respective output. + * + * QEMU interface: + * + 16 unnamed GPIO inputs: the input lines + * + 16 unnamed GPIO outputs: the output lines + */ +struct ProxyPICState { + /*< private >*/ + struct DeviceState parent_obj; + /*< public >*/ + + qemu_irq in_irqs[MAX_PROXY_PIC_LINES]; + qemu_irq out_irqs[MAX_PROXY_PIC_LINES]; +}; + +#endif /* HW_PROXY_PIC_H */ From patchwork Sun Dec 4 19:05:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13063998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C945BC47089 for ; Sun, 4 Dec 2022 19:09:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLF-00024e-OO; Sun, 04 Dec 2022 14:07:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLC-000233-Dx; Sun, 04 Dec 2022 14:07:54 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uKz-0001bf-Af; Sun, 04 Dec 2022 14:07:54 -0500 Received: by mail-ej1-x62f.google.com with SMTP id ml11so23089060ejb.6; Sun, 04 Dec 2022 11:07:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f3T47yIEIUMDvXF7x3Vl6rwvnsSBRqCjaJ2oEC6lUes=; b=AZH4Rax+tSQ2cPSzsoxliAQrTytzAg3YZrPpoHKOfBDt+pqpC5JWPJ4P6mc1G0mpOn P6OUP040bLaLsoAe+mMoR/rwccd8KMxctETVg5TdZcSVzTp02eAVW9C0cB4trFtDzbQc BpQ/glsx+WamVcEEd7ih3nLJEWQCe0bneX9a7MRXf1yXtsFhkEMZKiKwJMflfz4rGKyQ xoL/WK78Gxw/q7kxkLcE/G0paF7H56AEf2nt++z1gWo3yifjAk0a+L5+PZU2TVhO0BNc ClqUuMaUrDZixlaPAkuKtn8Lluqg/jpwSJLBuHcNBf87B1PBer9NeaxkmwOcZI7H+OuD lY7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f3T47yIEIUMDvXF7x3Vl6rwvnsSBRqCjaJ2oEC6lUes=; b=Reoc0MzcIPduxCuSm3pUSj3Ht6TH5cC11QYbPebOIsOAxHr2197rOlUf/ezLssJJoz tzWePB3It5q9UdNEQndCqwAkpZivD/JZvEHcUN54777BKM5xiWNJAEvUW+w3YTEWVkIm rFXiSAw/jA90r4VNrmSGqGD6ltW/CU47gAfWv753LZEWSLqqjwb0NLYCtk/NN1e9dKjK ucUv0wZdVaZurLC/XjUbpseUdNUC+WHHGBIe6HEGw75+r8O5NuGFoB9gXbMHFkMgZzd5 xoGZfp/LVJD1905AFYGjj83AWrO0iU87GY6bAmTmL5bhenfQpyYhbcEhYzBBrVsgsrVq DIzA== X-Gm-Message-State: ANoB5pl6XLrbVRton5UoYIY5JB7gyrk4IFnW0JdilHZZamckx+m0vCsy Ja6a2W7t33Wy4DXHhN30/0lwxZr/vpU= X-Google-Smtp-Source: AA0mqf4Qn0j8GFcoQBb5a2dSGsnl9vzjPKexvX9eJN3kzrpwNXITr4vx4krIr/voQp/dDkkhWMSydQ== X-Received: by 2002:a17:907:a50a:b0:7c0:7902:885f with SMTP id vr10-20020a170907a50a00b007c07902885fmr8248190ejc.233.1670180859804; Sun, 04 Dec 2022 11:07:39 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:39 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 12/32] hw/isa/piix3: Create Proxy PIC in host device Date: Sun, 4 Dec 2022 20:05:33 +0100 Message-Id: <20221204190553.3274-13-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use the newly introduced TYPE_PROXY_PIC which allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-16-shentey@gmail.com> --- hw/i386/Kconfig | 1 + hw/i386/pc_piix.c | 15 +++++++++------ hw/isa/Kconfig | 1 + hw/isa/piix3.c | 10 +++++++++- include/hw/southbridge/piix.h | 4 ++-- 5 files changed, 22 insertions(+), 9 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d22ac4a4b9..79f5925dbe 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -72,6 +72,7 @@ config I440FX select PC_PCI select PC_ACPI select ACPI_SMBUS + select I8259 select PCI_I440FX select PIIX3 select IDE_PIIX diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c96d989636..f81e91220f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -207,10 +207,11 @@ static void pc_init1(MachineState *machine, gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); if (pcmc->pci_enabled) { - PIIX3State *piix3; + DeviceState *dev; PCIDevice *pci_dev; const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; + int i; pci_bus = i440fx_init(pci_type, i440fx_host, @@ -231,10 +232,12 @@ static void pc_init1(MachineState *machine, x86_machine_is_smm_enabled(x86ms), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - piix3->pic = x86ms->gsi; - piix3_devfn = piix3->dev.devfn; - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic")); + for (i = 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); + } + piix3_devfn = pci_dev->devfn; + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); @@ -243,6 +246,7 @@ static void pc_init1(MachineState *machine, piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); rtc_state = isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -251,7 +255,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } - isa_bus_irqs(isa_bus, x86ms->gsi); if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 6c154d88c7..b4ad1fb66e 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -37,6 +37,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select PROXY_PIC select USB_UHCI config PIIX4 diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index cb2d9285ae..199cbf1e14 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -39,7 +39,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { - qemu_set_irq(piix3->pic[pic_irq], + qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); @@ -308,6 +308,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* PIC */ + if (!qdev_realize(DEVICE(&d->pic), NULL, errp)) { + return; + } + + isa_bus_irqs(isa_bus, d->pic.in_irqs); + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), @@ -371,6 +378,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d = PIIX3_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &d->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1c291cc954..7b1b4625a3 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/core/proxy-pic.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -50,11 +51,10 @@ struct PIIXState { #endif uint64_t pic_levels; - qemu_irq *pic; - /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + ProxyPICState pic; RTCState rtc; UHCIState uhci; PIIX4PMState pm; From patchwork Sun Dec 4 19:05:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4F00C4321E for ; Sun, 4 Dec 2022 19:16:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uL5-0001wy-1M; Sun, 04 Dec 2022 14:07:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uL3-0001vu-A0; Sun, 04 Dec 2022 14:07:45 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uL1-0001c1-GZ; Sun, 04 Dec 2022 14:07:45 -0500 Received: by mail-ej1-x62e.google.com with SMTP id fc4so16120399ejc.12; Sun, 04 Dec 2022 11:07:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7GB+odbQ95eIC6uph3zslGGTIRRkoNM8DhwqfiI1Vb0=; b=hPtWwgVhiL3Pls+gKB9DMmsFI23/HdC6LtUbDJdSr7YlRQFdXLjN88c6hTIpk8kz3R SShM9XWzibvU9Hc9EK5J48JCC1P+bX+uoc2Y0/FPzfGi6kQyr8F3dCoopL88GmV/cFl6 S0bVAks/LHwbk+189W5C15Lm4FPcOLkIv9CUc4klOIKlK4xKEjgI1gNwytxYEdd0XuU4 5AuaOZRiJkbridEnVcGff/3jYu6qv7ZYsdb2zMBouUbD+Lqf/u3Pg4nAUqTd/2uRvqxw UFM91bafAmxc1UNIAgH6QCDXBcKpygfSnav6RWA3L6Xd8P3pUJdSS2E8PJUGw62vRvo6 JxFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7GB+odbQ95eIC6uph3zslGGTIRRkoNM8DhwqfiI1Vb0=; b=Qh39avYNGRAF+Pj3Wzk6Y+uyLQk0yK7CtZOBXOM0267afVHBPdNOsq5CzztvkAXH95 g+XQWNfJAmLvdVsgoM5lSfe8S/fVENa/gMPwrCjFvlPJcAtifb7I6T/8pFETgoBJo3GD RNZE0vMG+K7mMx2YcAA9hBcyrUr2FiDdItHvo/n5NJ8UewUbhLf5dFJ/OVjD7WE7Zgqh CIVVv/Q2Fpve/v944YKJdTeZYjId5mNFUZsMXit2MUfaiYXCpKKknptJgEdOHkJ1BnDT LeYpdCz0vq0ntRguQLd43z3f//201Luz5o9lFn+tYNe6mX+DOJBZ5wjlBnJFIbsv41D0 mn7w== X-Gm-Message-State: ANoB5pk6NqUfB0gLTSLNAxmGbOKC7YI3ZFBp0/lyn+UPARlEl1F1dRtF TRmranLKH+uSefvowziiY/fPGQ7MujQ= X-Google-Smtp-Source: AA0mqf4ps5aRc4gqxCLGRJOckswKwBZSmCHKaFcNHt1XE53nL4W3nDzrTtQX52mRaOiQEhlvg8HMSw== X-Received: by 2002:a17:906:9615:b0:7c0:f459:a0e4 with SMTP id s21-20020a170906961500b007c0f459a0e4mr1481634ejx.155.1670180862380; Sun, 04 Dec 2022 11:07:42 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:42 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 13/32] hw/isa/piix3: Create IDE controller in host device Date: Sun, 4 Dec 2022 20:05:34 +0100 Message-Id: <20221204190553.3274-14-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that PIIX3 contains the new isa-pic, it is possible to instantiate PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to the ISA bus in its realize method which requires the interrupt controller to provide fully populated qemu_irqs. This is the case for isa-pic even though the virtualization technology not known yet. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-17-shentey@gmail.com> --- hw/i386/Kconfig | 1 - hw/i386/pc_piix.c | 15 ++++++--------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 8 ++++++++ include/hw/southbridge/piix.h | 2 ++ 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 79f5925dbe..39a35467ca 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -75,7 +75,6 @@ config I440FX select I8259 select PCI_I440FX select PIIX3 - select IDE_PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f81e91220f..19fe07a13b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -41,7 +41,6 @@ #include "hw/usb.h" #include "net/net.h" #include "hw/ide/pci.h" -#include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" @@ -86,7 +85,6 @@ static void pc_init1(MachineState *machine, PCIBus *pci_bus; ISABus *isa_bus; Object *piix4_pm; - int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; BusState *idebus[MAX_IDE_BUS]; @@ -236,11 +234,14 @@ static void pc_init1(MachineState *machine, for (i = 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); } - piix3_devfn = pci_dev->devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); + idebus[0] = qdev_get_child_bus(dev, "ide.0"); + idebus[1] = qdev_get_child_bus(dev, "ide.1"); } else { pci_bus = NULL; piix4_pm = NULL; @@ -254,6 +255,8 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; + idebus[0] = NULL; + idebus[1] = NULL; } if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { @@ -282,12 +285,6 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); if (pcmc->pci_enabled) { - PCIDevice *dev; - - dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE); - pci_ide_create_devs(dev); - idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0"); - idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1"); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); } #ifdef CONFIG_IDE_ISA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index b4ad1fb66e..8bf6462798 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select ACPI_PIIX4 select I8257 + select IDE_PIIX select ISA_BUS select MC146818RTC select PROXY_PIC diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 199cbf1e14..3504ad16ca 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -29,6 +29,7 @@ #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/ide/piix.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" @@ -328,6 +329,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* IDE */ + qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { + return; + } + /* USB */ if (d->has_usb) { object_initialize_child(OBJECT(dev), "uhci", &d->uhci, @@ -380,6 +387,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "pic", &d->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } static Property pci_piix3_props[] = { diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 7b1b4625a3..c4e6e9f827 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -16,6 +16,7 @@ #include "qom/object.h" #include "hw/acpi/piix4.h" #include "hw/core/proxy-pic.h" +#include "hw/ide/pci.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,7 @@ struct PIIXState { ProxyPICState pic; RTCState rtc; + PCIIDEState ide; UHCIState uhci; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:43 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 14/32] hw/isa/piix3: Wire up ACPI interrupt internally Date: Sun, 4 Dec 2022 20:05:35 +0100 Message-Id: <20221204190553.3274-15-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that PIIX3 has the PIC integrated, the ACPI controller can be wired up internally. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-18-shentey@gmail.com> --- hw/i386/pc_piix.c | 1 - hw/isa/piix3.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 19fe07a13b..dd4e89acf9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -313,7 +313,6 @@ static void pc_init1(MachineState *machine, if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 3504ad16ca..0341284199 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -354,6 +354,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { return; } + qdev_connect_gpio_out(DEVICE(&d->pm), 0, + qdev_get_gpio_in(DEVICE(&d->pic), 9)); } } From patchwork Sun Dec 4 19:05:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D083C4321E for ; Sun, 4 Dec 2022 19:11:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uL8-00020Z-NS; Sun, 04 Dec 2022 14:07:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uL7-0001zs-GQ; Sun, 04 Dec 2022 14:07:49 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uL5-0001ey-Ul; Sun, 04 Dec 2022 14:07:49 -0500 Received: by mail-ed1-x52f.google.com with SMTP id z92so13113585ede.1; Sun, 04 Dec 2022 11:07:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c8grMbME18Qpbp0IUFjkcz55as3asZan9rfItqTASvQ=; b=cwK35B56DokNxXbHnhc4ffWGBR8pyg9qtPEmfO16CgswT4i+jDgqzkMip4IZipc/+W GQpOlCS2BJhIfa7wZ+0h1nsQo/DpsEVErVJKsT5SnU3mM8rsMW0CYxIo8Wc4cq3tgkEW pM2nmIlAhzpt3tLeiUks0DdLxqbFN9rwhL2kXi/giUdGKhMo2P4YSXTkFrPLhHWhuved kEc8IzZjcb0uywcnbMXxEGqxXgcjLdXYxjMlROijFI73luOEff0B4b6j/809SX0vaqsi Wap5st/r31uzcTlmIyAfmFUOwVHTa8BVv2xXmg37m7JpT0WKwPUaeAV0qumNZKW5BUYO LATg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c8grMbME18Qpbp0IUFjkcz55as3asZan9rfItqTASvQ=; b=gdqOXAbRC1CYbTg4Z1x3MDrMU0S7M6blky+leYfjA+UK7y48uyo5xQ5lsix8diEHkK E7/qx5nH3E1sNO+2Fqk4+vuNIFiYktmPK3IMEAxewQ5XfOsfldxCIfhKd5R4bxV/me6c ksSDdD0iS8qym9XDOYZP6EeXEbWTI8Kfjy3y9rRGr8+iALhglICPji0QuBlX2DQx91Cp GLWDSweYgkfI1MX7F7LGno6YmYO4XICUVXJzNkarz9xhrb9dEVGJoGLCOqtLkKnVSBhA bhoAiZurDhgUD9rN5Bfyb6sOorrcyV46zgpl2nfVUp8hC4InL8LPToTqZgNBvZCLW2Fx QfUQ== X-Gm-Message-State: ANoB5pmej6WTCIoVFzUvxxbwhLh3H+hEisdbdIWtp3BtUi6HmcP32akt TbPfAJc7FzXtUbjb7tzpbb+ksgRyTug= X-Google-Smtp-Source: AA0mqf7sqpXHmMhPa0tAHWib3+OSOC3rVSKHeoMxV63HK7v2XGPip2LKkR2XhntPlAU9trUlcxZD6w== X-Received: by 2002:aa7:c719:0:b0:46a:bfd0:f816 with SMTP id i25-20020aa7c719000000b0046abfd0f816mr8765398edq.277.1670180865980; Sun, 04 Dec 2022 11:07:45 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:45 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 15/32] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Date: Sun, 4 Dec 2022 20:05:36 +0100 Message-Id: <20221204190553.3274-16-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-21-shentey@gmail.com> --- hw/isa/piix3.c | 8 ++++---- include/hw/southbridge/piix.h | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 0341284199..7ee706243a 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) uint64_t mask; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { + if (pic_irq >= ISA_NUM_IRQS) { return; } @@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) int pic_irq; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { + if (pic_irq >= ISA_NUM_IRQS) { return; } @@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; - if (irq < PIIX_NUM_PIC_IRQS) { + if (irq < ISA_NUM_IRQS) { route.mode = PCI_INTX_ENABLED; route.irq = irq; } else { @@ -130,7 +130,7 @@ static void piix3_write_config(PCIDevice *dev, pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); piix3_update_irq_levels(piix3); - for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { piix3_set_irq_pic(piix3, pic_irq); } } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index c4e6e9f827..39c31da9ad 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -32,7 +32,6 @@ */ #define PIIX_RCR_IOPORT 0xcf9 -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ struct PIIXState { @@ -44,10 +43,10 @@ struct PIIXState { * So one PIC level is tracked by PIIX_NUM_PIRQS bits. * * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with + * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with * pic_irq * PIIX_NUM_PIRQS + pirq */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 #error "unable to encode pic state in 64bit in pic_levels." #endif uint64_t pic_levels; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:47 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 16/32] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Date: Sun, 4 Dec 2022 20:05:37 +0100 Message-Id: <20221204190553.3274-17-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-22-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7ee706243a..a811a9bdab 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -392,7 +392,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } -static Property pci_piix3_props[] = { +static Property pci_piix_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), @@ -419,7 +419,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; - device_class_set_props(dc, pci_piix3_props); + device_class_set_props(dc, pci_piix_props); adevc->build_dev_aml = build_pci_isa_aml; } From patchwork Sun Dec 4 19:05:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31F2FC4321E for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:48 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 17/32] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 Date: Sun, 4 Dec 2022 20:05:38 +0100 Message-Id: <20221204190553.3274-18-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-23-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index a811a9bdab..e99622699a 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -156,7 +156,7 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } -static void piix3_reset(DeviceState *dev) +static void piix_reset(DeviceState *dev) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; @@ -406,7 +406,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); - dc->reset = piix3_reset; + dc->reset = piix_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; From patchwork Sun Dec 4 19:05:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99800C4321E for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:50 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 18/32] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" Date: Sun, 4 Dec 2022 20:05:39 +0100 Message-Id: <20221204190553.3274-19-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The additional prefix aligns the function name with both other piix3-internal functions as well as QEMU conventions. Furthermore, it will help to distinguish the function from its PIIX4 counterpart once merged. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-24-shentey@gmail.com> --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e99622699a..7faa699a3d 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -85,7 +85,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level) * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; slot_addend = PCI_SLOT(pci_dev->devfn) - 1; @@ -448,7 +448,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } From patchwork Sun Dec 4 19:05:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13063999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76BFFC3A5A7 for ; Sun, 4 Dec 2022 19:09:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLP-0002Ba-TD; Sun, 04 Dec 2022 14:08:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLN-00029U-Hd; Sun, 04 Dec 2022 14:08:05 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uLC-0001g4-Lb; Sun, 04 Dec 2022 14:08:03 -0500 Received: by mail-ej1-x630.google.com with SMTP id td2so23048405ejc.5; Sun, 04 Dec 2022 11:07:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rupUs35jEN5Y59bxwbRFxpiIUltwCjX9j3izbINqU7w=; b=SaSQRSLm4K/kR/GNDdDXEjZPTVCRKHNX/nKwnDf27GRDochNIep9cidYZhQBgHTb/N VLECDCPiIWlliqfjIJaUJLSk8PWPYEdcvKSJn0n8Jy78816fJURQY9+GP8WMcSW44Ray M6qhWmKC+tN9YUgyfGA+2J3NqFj14gYv9jA8j5OlF/JcwxYxLm8fZXdu0KHbNm5g4jeG VPIgp7q7X1X7BYI/DQShsioNqmmz+wkYyyMwb5NwVGhBMPOFWB+frs9MqE1k/mDVyBZl S92q2l0MVBD+zNINjkd3TMsg4vLDmCrJPRX4XrVcA8W3RMsSwDQEl+GU58/vw6vMmhAW Y2kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rupUs35jEN5Y59bxwbRFxpiIUltwCjX9j3izbINqU7w=; b=i7GxnmnTpBtuDoIyFE+cItSIkHBj2oRuupTTfge39IMch8MqCh1FgBpAXpzGWA7PGl GlZK7jxCL9ukYQE85daoLALDei4pEtdXgWHa/gTv+tZzh/LhRwIWR8+p7yY1GY7gfEB1 XzUc0c/kowqgCpOnsagAvxijqw4nAfWOCRAxEhBbNC+nr4Wes8jXfGCw4h972JP88bFh S4wHkNeL60lOUgFnTZuPWHj0sJZB2hgmUk4xpIG4WelZMYj+rik8d8BfVyMwPrHyO8r7 mTOibouMb+bgx4pnNUTE1nZ2AQldgo/1ZXGFnnQh9ZFGGIfiJbyHGEqeKcNKtshtfkyA VciA== X-Gm-Message-State: ANoB5pkjSl0StccltWH+8MexIzU7fqxx1Yaf0V59rqwHDv14GdkieZbA ti5EzCuhofcSZzBCO2CZ8SiLgMuQYII= X-Google-Smtp-Source: AA0mqf4kO6dQya3S4EJGNr0PJTblg4O59XT160/PLLFBBZTK2QfdjaEtLLLch6Dh04q0La9yAa2ycw== X-Received: by 2002:a17:907:2904:b0:78d:b598:bb6a with SMTP id eq4-20020a170907290400b0078db598bb6amr53225455ejc.258.1670180872473; Sun, 04 Dec 2022 11:07:52 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:52 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 19/32] hw/isa/piix3: Rename typedef PIIX3State to PIIXState Date: Sun, 4 Dec 2022 20:05:40 +0100 Message-Id: <20221204190553.3274-20-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-25-shentey@gmail.com> --- hw/isa/piix3.c | 50 +++++++++++++++++------------------ include/hw/southbridge/piix.h | 4 +-- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7faa699a3d..ff349c99ad 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -38,7 +38,7 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & @@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) piix3->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; @@ -77,7 +77,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } @@ -94,7 +94,7 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; @@ -109,7 +109,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus = pci_get_bus(&piix3->dev); int pirq; @@ -125,7 +125,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); int pic_irq; pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -158,7 +158,7 @@ static void piix3_write_config_xen(PCIDevice *dev, static void piix_reset(DeviceState *dev) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; /* master, memory and I/O */ @@ -199,7 +199,7 @@ static void piix_reset(DeviceState *dev) static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int pirq; /* @@ -222,7 +222,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] = @@ -234,7 +234,7 @@ static int piix3_pre_save(void *opaque) static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; return (piix3->rcr != 0); } @@ -245,7 +245,7 @@ static const VMStateDescription vmstate_piix3_rcr = { .minimum_version_id = 1, .needed = piix3_rcr_needed, .fields = (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -257,8 +257,8 @@ static const VMStateDescription vmstate_piix3 = { .post_load = piix3_post_load, .pre_save = piix3_pre_save, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -271,7 +271,7 @@ static const VMStateDescription vmstate_piix3 = { static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -282,7 +282,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; return d->rcr; } @@ -299,7 +299,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -385,7 +385,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) static void pci_piix3_init(Object *obj) { - PIIX3State *d = PIIX3_PCI_DEVICE(obj); + PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); @@ -393,10 +393,10 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -426,7 +426,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX3State), + .instance_size = sizeof(PIIXState), .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, @@ -440,7 +440,7 @@ static const TypeInfo piix3_pci_type_info = { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); @@ -470,7 +470,7 @@ static const TypeInfo piix3_info = { static void piix3_xen_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 39c31da9ad..a489f52d1b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -72,10 +72,10 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; +typedef struct PIIXState PIIXState; #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, +DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) #define TYPE_PIIX3_DEVICE "PIIX3" From patchwork Sun Dec 4 19:05:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92CB2C4321E for ; Sun, 4 Dec 2022 19:09:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLM-000299-64; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:53 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 20/32] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Date: Sun, 4 Dec 2022 20:05:41 +0100 Message-Id: <20221204190553.3274-21-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This aligns PIIX4 with PIIX3. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-30-shentey@gmail.com> --- hw/isa/piix4.c | 44 ++++++++++++++++++++++++++++++++------------ hw/mips/malta.c | 6 ++++-- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index aceb21ee3e..24d943c609 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -51,9 +51,16 @@ struct PIIX4State { PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; + + uint32_t smb_io_base; + /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; + + bool has_acpi; + bool has_usb; + bool smm_enabled; }; OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) @@ -259,17 +266,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } /* USB */ - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } } /* ACPI controller */ - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -280,13 +296,16 @@ static void piix4_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); - - object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0); } +static Property piix4_props[] = { + DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -305,6 +324,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) */ dc->user_creatable = false; dc->hotpluggable = false; + device_class_set_props(dc, piix4_props); } static const TypeInfo piix4_info = { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c3dcd43f37..4d0251ee12 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1422,8 +1422,10 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true, - TYPE_PIIX4_PCI_DEVICE); + piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, true, + TYPE_PIIX4_PCI_DEVICE); + qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); From patchwork Sun Dec 4 19:05:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7E20C4321E for ; Sun, 4 Dec 2022 19:18:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLI-00027f-HV; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:55 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 21/32] hw/isa/piix4: Remove unused code Date: Sun, 4 Dec 2022 20:05:42 +0100 Message-Id: <20221204190553.3274-22-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Malta board, which is the only user of PIIX4, doesn't connect to the exported interrupt lines. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-32-shentey@gmail.com> --- hw/isa/piix4.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 24d943c609..dbefcb3ff4 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -180,12 +180,6 @@ static void piix4_request_i8259_irq(void *opaque, int irq, int level) qemu_set_irq(s->cpu_intr, level); } -static void piix4_set_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s = opaque; - qemu_set_irq(s->isa[irq], level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -229,8 +223,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, - "isa", ISA_NUM_IRQS); qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, "intr", 1); From patchwork Sun Dec 4 19:05:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC4B1C4321E for ; Sun, 4 Dec 2022 19:17:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLO-00029x-Tx; Sun, 04 Dec 2022 14:08:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLN-00029T-Gs; Sun, 04 Dec 2022 14:08:05 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uLG-0001di-JU; Sun, 04 Dec 2022 14:08:03 -0500 Received: by mail-ed1-x52f.google.com with SMTP id a16so13030717edb.9; Sun, 04 Dec 2022 11:07:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AJe/x/f5psHysCR+cTfpOkxzfZdgwmNuxZEnGlBuf0E=; b=GU2wuIGIAUDJFHGnpIWAGudyspaTIOZWLFZLHgtvq8TtNtSZ4Dm5MB/sJqfCh/yjJF jvuCC6uQ/kuTJU8WqiBfOOTtQUdxGwQr4MoAMeVOHDS19IrZvM+mq1nAA5CLaHGwJF1B J44hFT5IHBSXJdDHSIkjl5FSfWZzjJihXK2gzHHfNbcykY+ZBzHWtfnnmNBW3GX4VPVT cRRuSYdoVlj9TodIk2gUz5tUw0kyLbAGVGcxSrReJUj/p/2iw6+8m/hV7ZusQxW/8Cp4 Zvl+kRZVADTOZVaxj77Lg9ECyPxPezFKTi8rM0Vt/EWYOuSVXEAS8kk1dzkI3gHw+DJX nv3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AJe/x/f5psHysCR+cTfpOkxzfZdgwmNuxZEnGlBuf0E=; b=yqEGUAAdei1sKSLA7gxeT/vU0zseWdqx97QZ1its/qaAlzZCNydnHAa9Ho6OjPWwib dG1fO9dG335oJPrks0xzGklLpvN6gj0nN4bIEh4NzCbBFRvV/z4NTSO7iFznVtNyeQQc 1H8hnrtX8H90OWUg7sN2gx9YfE+zir/hG1L2Vs+CCtqDo4JWlab4Kmtigj+L2yEqLX6W AILa3ulYHd5oEtOVP1HKixX0+RkLOmTkS4V3VgPXPyeM4aJVE3vuSC3LwMKI35pddIW0 zRHAJWMsJn/WOU7zYXJuoGkfH5bM3pI0Bz4i/RtgQRoVz8zNzjcGvjCVn7N/gMVxeSlq FjXw== X-Gm-Message-State: ANoB5pmOSDIKAdBnINTMBmLjAcjMXBtBh8zPPgwIH3iDY7eM9f/hXJD3 kUlkPIdzkgy8CyCkFJO+04x2oGpHxLE= X-Google-Smtp-Source: AA0mqf7atwCDKaBzkYcvVpTh/NZfmrmR/9KgKJqmwGli/lTMJguMvXWOde3DhepROu3cPX2u5QJbTQ== X-Received: by 2002:aa7:de05:0:b0:46b:7706:9a38 with SMTP id h5-20020aa7de05000000b0046b77069a38mr22907910edv.321.1670180877418; Sun, 04 Dec 2022 11:07:57 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:57 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 22/32] hw/isa/piix4: Use Proxy PIC device Date: Sun, 4 Dec 2022 20:05:43 +0100 Message-Id: <20221204190553.3274-23-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-33-shentey@gmail.com> --- hw/isa/Kconfig | 2 +- hw/isa/piix4.c | 30 +++++++++++------------------- hw/mips/Kconfig | 1 + hw/mips/malta.c | 11 +++++++++-- 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 8bf6462798..4dfa3310d9 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -48,10 +48,10 @@ config PIIX4 select ACPI_PIIX4 select I8254 select I8257 - select I8259 select IDE_PIIX select ISA_BUS select MC146818RTC + select PROXY_PIC select USB_UHCI config VT82C686 diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index dbefcb3ff4..0c34e3717c 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -30,7 +30,7 @@ #include "hw/pci/pci.h" #include "hw/ide/piix.h" #include "hw/isa/isa.h" -#include "hw/intc/i8259.h" +#include "hw/core/proxy-pic.h" #include "hw/dma/i8257.h" #include "hw/timer/i8254.h" #include "hw/rtc/mc146818rtc.h" @@ -44,9 +44,8 @@ struct PIIX4State { PCIDevice dev; - qemu_irq cpu_intr; - qemu_irq *isa; + ProxyPICState pic; RTCState rtc; PCIIDEState ide; UHCIState uhci; @@ -82,7 +81,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) pic_level |= pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(s->isa[pic_irq], pic_level); + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); } } @@ -174,12 +173,6 @@ static const VMStateDescription vmstate_piix4 = { } }; -static void piix4_request_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s = opaque; - qemu_set_irq(s->cpu_intr, level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -215,7 +208,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s = PIIX4_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - qemu_irq *i8259_out_irq; isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -223,20 +215,18 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, - "intr", 1); - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); /* initialize i8259 pic */ - i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); - s->isa = i8259_init(isa_bus, *i8259_out_irq); + if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + return; + } /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->isa); + isa_bus_irqs(isa_bus, s->pic.in_irqs); /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); @@ -249,7 +239,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { return; } - s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); /* IDE */ qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); @@ -276,7 +266,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { return; } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); } pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); @@ -286,6 +277,7 @@ static void piix4_init(Object *obj) { PIIX4State *s = PIIX4_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &s->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 4e7042f03d..d156de812c 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,5 +1,6 @@ config MALTA bool + select I8259 select ISA_SUPERIO select PIIX4 diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4d0251ee12..36bdc184f6 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -29,6 +29,7 @@ #include "qemu/guest-random.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" +#include "hw/intc/i8259.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -1254,10 +1255,11 @@ void mips_malta_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; + qemu_irq *i8259; I2CBus *smbus; DriveInfo *dinfo; int fl_idx = 0; - int be; + int be, i; MaltaState *s; PCIDevice *piix4; DeviceState *dev; @@ -1432,7 +1434,12 @@ void mips_malta_init(MachineState *machine) pci_ide_create_devs(PCI_DEVICE(dev)); /* Interrupt controller */ - qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pic")); + i8259 = i8259_init(isa_bus, i8259_irq); + for (i = 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, i8259[i]); + } + g_free(i8259); /* generate SPD EEPROM data */ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); From patchwork Sun Dec 4 19:05:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 438F1C4321E for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:58 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 23/32] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Date: Sun, 4 Dec 2022 20:05:44 +0100 Message-Id: <20221204190553.3274-24-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that PIIX4 also uses the "proxy-pic", both implementations can share the same struct. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-34-shentey@gmail.com> --- hw/isa/piix4.c | 51 +++++++++++++++----------------------------------- 1 file changed, 15 insertions(+), 36 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 0c34e3717c..c12388ddac 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -42,32 +42,10 @@ #include "sysemu/runstate.h" #include "qom/object.h" -struct PIIX4State { - PCIDevice dev; - - ProxyPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register */ - MemoryRegion rcr_mem; - uint8_t rcr; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) - static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX4State *s = opaque; + PIIXState *s = opaque; PCIBus *bus = pci_get_bus(&s->dev); /* now we change the pic irq level according to the piix irq mappings */ @@ -112,7 +90,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d = PIIX4_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; // master, memory and I/O @@ -147,12 +125,13 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; + d->pic_levels = 0; /* not used in PIIX4 */ d->rcr = 0; } static int piix4_post_load(void *opaque, int version_id) { - PIIX4State *s = opaque; + PIIXState *s = opaque; if (version_id == 2) { s->rcr = 0; @@ -167,8 +146,8 @@ static const VMStateDescription vmstate_piix4 = { .minimum_version_id = 2, .post_load = piix4_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_UINT8_V(rcr, PIIX4State, 3), + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), VMSTATE_END_OF_LIST() } }; @@ -176,7 +155,7 @@ static const VMStateDescription vmstate_piix4 = { static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { - PIIX4State *s = opaque; + PIIXState *s = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -188,7 +167,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) { - PIIX4State *s = opaque; + PIIXState *s = opaque; return s->rcr; } @@ -205,7 +184,7 @@ static const MemoryRegionOps piix4_rcr_ops = { static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *s = PIIX4_PCI_DEVICE(dev); + PIIXState *s = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -275,7 +254,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) static void piix4_init(Object *obj) { - PIIX4State *s = PIIX4_PCI_DEVICE(obj); + PIIXState *s = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &s->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); @@ -283,10 +262,10 @@ static void piix4_init(Object *obj) } static Property piix4_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -314,7 +293,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX4State), + .instance_size = sizeof(PIIXState), .instance_init = piix4_init, .class_init = piix4_class_init, .interfaces = (InterfaceInfo[]) { From patchwork Sun Dec 4 19:05:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13063996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E5ACC4321E for ; Sun, 4 Dec 2022 19:09:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLS-0002Ee-Pp; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:00 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 24/32] hw/isa/piix4: Rename reset control operations to match PIIX3 Date: Sun, 4 Dec 2022 20:05:45 +0100 Message-Id: <20221204190553.3274-25-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-35-shentey@gmail.com> --- hw/isa/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index c12388ddac..13ec2503d0 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -152,7 +152,7 @@ static const VMStateDescription vmstate_piix4 = { } }; -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { PIIXState *s = opaque; @@ -165,16 +165,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, s->rcr = val & 2; /* keep System Reset type only */ } -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIXState *s = opaque; return s->rcr; } -static const MemoryRegionOps piix4_rcr_ops = { - .read = piix4_rcr_read, - .write = piix4_rcr_write, +static const MemoryRegionOps rcr_ops = { + .read = rcr_read, + .write = rcr_write, .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 1, @@ -194,7 +194,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); From patchwork Sun Dec 4 19:05:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E160BC4708D for ; Sun, 4 Dec 2022 19:14:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLT-0002Es-6h; Sun, 04 Dec 2022 14:08:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLP-0002Aa-3F; Sun, 04 Dec 2022 14:08:07 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uLN-0001cz-JK; Sun, 04 Dec 2022 14:08:06 -0500 Received: by mail-ej1-x62d.google.com with SMTP id x22so707016ejs.11; Sun, 04 Dec 2022 11:08:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O21mvhv0jXquAoUuO39uCEwvUB1QlIRX94aQwEjiL8g=; b=HCznjU4P5UeVcFhR9GpboExF8vtWCS1f6TbzCLG5ZeObY16p2FElbIDqVo/oXzObmF 0F/zMLvBnACHhdMOf54V3FMii/pua7z5GRQ8lwJY1+hLyNlxI+Jr6XbJs/UGBHVGYJd0 /WjFRVzQFR545xdICK2DIffZfTYS5hG6yfw8WU6lxy/I79yZVNK/xFRazuNeZvoKobM0 3hmgilWyZco2/Cv4LDjpKK23drHWTdtl33vMKUjcu0tH2x5Awcr7hWW6GyTOVMMJba46 fgrw9EN5Xfgc4b4JIhJFO4bsmQzRlIg/S0KghjjibzwUdcfOcyhwXSfH264aTDzGbSjy +Suw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O21mvhv0jXquAoUuO39uCEwvUB1QlIRX94aQwEjiL8g=; b=0XitCyVYgec0zwgOYlWMlRUm6fvuNt1tK/o6y0XepsAbYc1cPbgtKwa2lDLP9F+vDz d+10D/ofgooBWFARQMdfDE11AxZbVnAAq990fPeDHF8yuZnwU2mfjwGJ6Fk7o83qAqLx rFiuDzUx2crRP0CFBwq1HivfxSvWV222TVYuSgEPHrnf2+ZUZn2UH5GQtogwt8kbqvCp h3NCN2DjhDSQ8bzZnh10kvIStYuJe+7aiK1ega3aYFGPmBb9mMFo3GCnRQh0EkvaC1AX j25kJngi7thO6ZZ1HXaCxVaQlNz+V4UPR/qzv7IPEI08fMESusWSCEOo/0yzJ69OmTdf kInQ== X-Gm-Message-State: ANoB5pnDbrQmjORF4FIoO9kwcNzVq32xizczvh5CYC0hShnmEtl0gmY6 SDQGPvOR/rivMaZ9hmn+88sruyhfong= X-Google-Smtp-Source: AA0mqf7zM1mm6qYInAB60oktzD5cy+Gj3CzzPHqOfgs23JqPtnIZPM7vlUSfjxt8kSn3hYyb4qrQ1A== X-Received: by 2002:a17:906:52cd:b0:7c0:f212:46fc with SMTP id w13-20020a17090652cd00b007c0f21246fcmr1864091ejn.214.1670180882415; Sun, 04 Dec 2022 11:08:02 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:02 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 25/32] hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" Date: Sun, 4 Dec 2022 20:05:46 +0100 Message-Id: <20221204190553.3274-26-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Prefixing with "piix4_" makes the method distinguishable from its PIIX3 counterpart upon merging and also complies more with QEMU conventions. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-36-shentey@gmail.com> --- hw/isa/piix4.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 13ec2503d0..e01d6ae00c 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -63,7 +63,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) } } -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) { int slot; @@ -249,7 +249,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->pic), 9)); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + PIIX_NUM_PIRQS); } static void piix4_init(Object *obj) From patchwork Sun Dec 4 19:05:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F615C4321E for ; Sun, 4 Dec 2022 19:19:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLV-0002HU-9g; Sun, 04 Dec 2022 14:08:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLS-0002EI-BV; Sun, 04 Dec 2022 14:08:10 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uLO-0001hf-2O; Sun, 04 Dec 2022 14:08:10 -0500 Received: by mail-ed1-x534.google.com with SMTP id s5so13013083edc.12; Sun, 04 Dec 2022 11:08:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xLe6LulDawoV6ei0ZDpf/o85NplTaL5h+gY0BCTroSw=; b=SXdE0zP7Xv3JMe2AMsz7gJUCtoaZpjCmZuAr+6N3E5Lf7ANb7ZMgEAmbX93H+QBQKa 9s0+yazyHfUfl5GQYEN5ZRIB840TU97oRS+Zd8Ns52K+sCgQXw5zdaNAyJU9V5/Qrog0 LjeFbGcFY6822b+71oi9mtvnkmyMumBsKtNq+gkSwNy4N05m/JY4DjW4X6LcPKubtNBI H2ee/wMoZtTUFSX04F05EY8K3f/HzJMKltP2v6U34XYvKmvQTqe4RFy5ChO3gWnomjLv FA4tn8yOnLhWL0xOZbUpid5zMWRU5sVs2DaLdYY25id3af5SxGDohCqP5PzPHN+48xEF +FKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xLe6LulDawoV6ei0ZDpf/o85NplTaL5h+gY0BCTroSw=; b=U92VOl2hOeVMl+e6WBMAF1iipHIZWujrY0EseOfPZVG7esGup8OqYAxiWDtk4USYLk hjTsqQAQeW0UXBXW4+LzrKUoPOcs7bWIKocTlwwlR2Hf2F7R3NCYpkJqHHvYKx/4aBHN Tg/bE6U9ZtzNqhZKKnBK4z9XPWGeLSiUllC/EBT6twu70DsitarrHF03Vs+r46EUeDyT FoZS6lkx49Bd2bY086g5yKZzcjuaX8LERIq2AfYaEB20+GdVhzaQZ/IhQSXj1EsxS2SB +ZJS++AhBgSd0jBjRFK0mBv4yW13HtRbqZMbx5o12SmqlDwuYrMJYhbd08wcv4GrE3B8 9uAA== X-Gm-Message-State: ANoB5pm+vG/Q86zdjqctmGEQ0Yu6k9o7ecC3xW2AiXqioxUCv6w5gSaO Q6x0/+o1SOWt3y7kZZQXvrXUizOb5HI= X-Google-Smtp-Source: AA0mqf6aP6FqoyI3HwJDzJWBCGUjJwSDEpYDRGuNfNmMWwSqmuvkU4bziGVa9vRAa6FR6hhi5Olo8A== X-Received: by 2002:aa7:dada:0:b0:46b:c59b:d10d with SMTP id x26-20020aa7dada000000b0046bc59bd10dmr16334481eds.403.1670180884010; Sun, 04 Dec 2022 11:08:04 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:03 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 26/32] hw/isa/piix3: Merge hw/isa/piix4.c Date: Sun, 4 Dec 2022 20:05:47 +0100 Message-Id: <20221204190553.3274-27-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that the PIIX3 and PIIX4 device models are sufficiently consolidated, their implementations can be merged into one file for further consolidation. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-37-shentey@gmail.com> --- MAINTAINERS | 6 +- hw/i386/Kconfig | 2 +- hw/isa/Kconfig | 12 +- hw/isa/meson.build | 3 +- hw/isa/{piix3.c => piix.c} | 184 ++++++++++++++++++++++ hw/isa/piix4.c | 311 ------------------------------------- hw/mips/Kconfig | 2 +- 7 files changed, 191 insertions(+), 329 deletions(-) rename hw/isa/{piix3.c => piix.c} (73%) delete mode 100644 hw/isa/piix4.c diff --git a/MAINTAINERS b/MAINTAINERS index b33fc7e091..ca0444dd15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1223,7 +1223,7 @@ Malta M: Philippe Mathieu-Daudé R: Aurelien Jarno S: Odd Fixes -F: hw/isa/piix4.c +F: hw/isa/piix.c F: hw/acpi/piix4.c F: hw/mips/malta.c F: hw/mips/gt64xxx_pci.c @@ -1640,7 +1640,7 @@ F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h -F: hw/isa/piix3.c +F: hw/isa/piix.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c @@ -2330,7 +2330,7 @@ PIIX4 South Bridge (i82371AB) M: Hervé Poussineau M: Philippe Mathieu-Daudé S: Maintained -F: hw/isa/piix4.c +F: hw/isa/piix.c F: include/hw/southbridge/piix.h Firmware configuration (fw_cfg) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 39a35467ca..15442ddbdf 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -74,7 +74,7 @@ config I440FX select ACPI_SMBUS select I8259 select PCI_I440FX - select PIIX3 + select PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 4dfa3310d9..0f3284220b 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -31,17 +31,7 @@ config PC87312 select FDC_ISA select IDE_ISA -config PIIX3 - bool - select ACPI_PIIX4 - select I8257 - select IDE_PIIX - select ISA_BUS - select MC146818RTC - select PROXY_PIC - select USB_UHCI - -config PIIX4 +config PIIX bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 8bf678ca0a..314bbd0860 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -3,8 +3,7 @@ softmmu_ss.add(when: 'CONFIG_I82378', if_true: files('i82378.c')) softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) -softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c')) -softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c')) +softmmu_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c')) softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) diff --git a/hw/isa/piix3.c b/hw/isa/piix.c similarity index 73% rename from hw/isa/piix3.c rename to hw/isa/piix.c index ff349c99ad..75001ce528 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix.c @@ -2,6 +2,7 @@ * QEMU PIIX PCI ISA Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +28,7 @@ #include "qapi/error.h" #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" +#include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ide/piix.h" @@ -81,6 +83,27 @@ static void piix3_set_irq(void *opaque, int pirq, int level) piix3_set_irq_level(piix3, pirq, level); } +static void piix4_set_irq(void *opaque, int irq_num, int level) +{ + int i, pic_irq, pic_level; + PIIXState *s = opaque; + PCIBus *bus = pci_get_bus(&s->dev); + + /* now we change the pic irq level according to the piix irq mappings */ + /* XXX: optimize */ + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; + if (pic_irq < ISA_NUM_IRQS) { + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level = 0; + for (i = 0; i < PIIX_NUM_PIRQS; i++) { + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { + pic_level |= pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); + } +} + /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -92,6 +115,31 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) return (pci_intx + slot_addend) & 3; } +static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +{ + int slot; + + slot = PCI_SLOT(pci_dev->devfn); + + switch (slot) { + /* PIIX4 USB */ + case 10: + return 3; + /* AMD 79C973 Ethernet */ + case 11: + return 1; + /* Crystal 4281 Sound */ + case 12: + return 2; + /* PCI slot 1 to 4 */ + case 18 ... 21: + return ((slot - 18) + irq_num) & 0x03; + /* Unknown device, don't do any translation */ + default: + return irq_num; + } +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 = opaque; @@ -219,6 +267,17 @@ static int piix3_post_load(void *opaque, int version_id) return 0; } +static int piix4_post_load(void *opaque, int version_id) +{ + PIIXState *s = opaque; + + if (version_id == 2) { + s->rcr = 0; + } + + return 0; +} + static int piix3_pre_save(void *opaque) { int i; @@ -268,6 +327,17 @@ static const VMStateDescription vmstate_piix3 = { } }; +static const VMStateDescription vmstate_piix4 = { + .name = "PIIX4", + .version_id = 3, + .minimum_version_id = 2, + .post_load = piix4_post_load, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), + VMSTATE_END_OF_LIST() + } +}; static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -502,11 +572,125 @@ static const TypeInfo piix3_xen_info = { .class_init = piix3_xen_class_init, }; +static void piix4_realize(PCIDevice *dev, Error **errp) +{ + PIIXState *s = PIIX_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); + ISABus *isa_bus; + + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), + pci_address_space_io(dev), errp); + if (!isa_bus) { + return; + } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &s->rcr_mem, 1); + + /* initialize i8259 pic */ + if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + return; + } + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->pic.in_irqs); + + /* initialize pit */ + i8254_pit_init(isa_bus, 0x40, 0, NULL); + + /* DMA */ + i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { + return; + } + s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); + + /* IDE */ + qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { + return; + } + + /* USB */ + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } + } + + /* ACPI controller */ + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); + } + + pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + PIIX_NUM_PIRQS); +} + +static void piix4_init(Object *obj) +{ + PIIXState *s = PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "pic", &s->pic, TYPE_PROXY_PIC); + object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); +} + +static void piix4_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = piix4_realize; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; + k->class_id = PCI_CLASS_BRIDGE_ISA; + dc->reset = piix_reset; + dc->desc = "ISA bridge"; + dc->vmsd = &vmstate_piix4; + /* + * Reason: part of PIIX4 southbridge, needs to be wired up, + * e.g. by mips_malta_init() + */ + dc->user_creatable = false; + dc->hotpluggable = false; + device_class_set_props(dc, pci_piix_props); +} + +static const TypeInfo piix4_info = { + .name = TYPE_PIIX4_PCI_DEVICE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PIIXState), + .instance_init = piix4_init, + .class_init = piix4_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + static void piix3_register_types(void) { type_register_static(&piix3_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); + type_register_static(&piix4_info); } type_init(piix3_register_types) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c deleted file mode 100644 index e01d6ae00c..0000000000 --- a/hw/isa/piix4.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * QEMU PIIX4 PCI Bridge Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2018 Hervé Poussineau - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/irq.h" -#include "hw/southbridge/piix.h" -#include "hw/pci/pci.h" -#include "hw/ide/piix.h" -#include "hw/isa/isa.h" -#include "hw/core/proxy-pic.h" -#include "hw/dma/i8257.h" -#include "hw/timer/i8254.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/ide/pci.h" -#include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" -#include "migration/vmstate.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "qom/object.h" - -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - -static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) -{ - int slot; - - slot = PCI_SLOT(pci_dev->devfn); - - switch (slot) { - /* PIIX4 USB */ - case 10: - return 3; - /* AMD 79C973 Ethernet */ - case 11: - return 1; - /* Crystal 4281 Sound */ - case 12: - return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: - return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: - return irq_num; - } -} - -static void piix4_isa_reset(DeviceState *dev) -{ - PIIXState *d = PIIX_PCI_DEVICE(dev); - uint8_t *pci_conf = d->dev.config; - - pci_conf[0x04] = 0x07; // master, memory and I/O - pci_conf[0x05] = 0x00; - pci_conf[0x06] = 0x00; - pci_conf[0x07] = 0x02; // PCI_status_devsel_medium - pci_conf[0x4c] = 0x4d; - pci_conf[0x4e] = 0x03; - pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x80; - pci_conf[0x61] = 0x80; - pci_conf[0x62] = 0x80; - pci_conf[0x63] = 0x80; - pci_conf[0x69] = 0x02; - pci_conf[0x70] = 0x80; - pci_conf[0x76] = 0x0c; - pci_conf[0x77] = 0x0c; - pci_conf[0x78] = 0x02; - pci_conf[0x79] = 0x00; - pci_conf[0x80] = 0x00; - pci_conf[0x82] = 0x00; - pci_conf[0xa0] = 0x08; - pci_conf[0xa2] = 0x00; - pci_conf[0xa3] = 0x00; - pci_conf[0xa4] = 0x00; - pci_conf[0xa5] = 0x00; - pci_conf[0xa6] = 0x00; - pci_conf[0xa7] = 0x00; - pci_conf[0xa8] = 0x0f; - pci_conf[0xaa] = 0x00; - pci_conf[0xab] = 0x00; - pci_conf[0xac] = 0x00; - pci_conf[0xae] = 0x00; - - d->pic_levels = 0; /* not used in PIIX4 */ - d->rcr = 0; -} - -static int piix4_post_load(void *opaque, int version_id) -{ - PIIXState *s = opaque; - - if (version_id == 2) { - s->rcr = 0; - } - - return 0; -} - -static const VMStateDescription vmstate_piix4 = { - .name = "PIIX4", - .version_id = 3, - .minimum_version_id = 2, - .post_load = piix4_post_load, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIXState), - VMSTATE_UINT8_V(rcr, PIIXState, 3), - VMSTATE_END_OF_LIST() - } -}; - -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int len) -{ - PIIXState *s = opaque; - - if (val & 4) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - } - - s->rcr = val & 2; /* keep System Reset type only */ -} - -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) -{ - PIIXState *s = opaque; - - return s->rcr; -} - -static const MemoryRegionOps rcr_ops = { - .read = rcr_read, - .write = rcr_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .impl = { - .min_access_size = 1, - .max_access_size = 1, - }, -}; - -static void piix4_realize(PCIDevice *dev, Error **errp) -{ - PIIXState *s = PIIX_PCI_DEVICE(dev); - PCIBus *pci_bus = pci_get_bus(dev); - ISABus *isa_bus; - - isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { - return; - } - - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); - - /* initialize pit */ - i8254_pit_init(isa_bus, 0x40, 0, NULL); - - /* DMA */ - i8257_dma_init(isa_bus, 0); - - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } - s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, - PIIX_NUM_PIRQS); -} - -static void piix4_init(Object *obj) -{ - PIIXState *s = PIIX_PCI_DEVICE(obj); - - object_initialize_child(obj, "pic", &s->pic, TYPE_PROXY_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); -} - -static Property piix4_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), - DEFINE_PROP_END_OF_LIST(), -}; - -static void piix4_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->reset = piix4_isa_reset; - dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable = false; - dc->hotpluggable = false; - device_class_set_props(dc, piix4_props); -} - -static const TypeInfo piix4_info = { - .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIXState), - .instance_init = piix4_init, - .class_init = piix4_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - -static void piix4_register_types(void) -{ - type_register_static(&piix4_info); -} - -type_init(piix4_register_types) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index d156de812c..5b16ff4ed2 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -2,7 +2,7 @@ config MALTA bool select I8259 select ISA_SUPERIO - select PIIX4 + select PIIX config MIPSSIM bool From patchwork Sun Dec 4 19:05:48 2022 Content-Type: text/plain; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:05 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 27/32] hw/isa/piix: Harmonize names of reset control memory regions Date: Sun, 4 Dec 2022 20:05:48 +0100 Message-Id: <20221204190553.3274-28-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221022150508.26830-38-shentey@gmail.com> --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 75001ce528..035f64b928 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -387,7 +387,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) isa_bus_irqs(isa_bus, d->pic.in_irqs); memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, - "piix3-reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); @@ -585,7 +585,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); From patchwork Sun Dec 4 19:05:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A083C4321E for ; Sun, 4 Dec 2022 19:15:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLU-0002H3-Pi; Sun, 04 Dec 2022 14:08:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLS-0002EF-99; Sun, 04 Dec 2022 14:08:10 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uLQ-0001gV-G4; Sun, 04 Dec 2022 14:08:10 -0500 Received: by mail-ej1-x62d.google.com with SMTP id vp12so23072216ejc.8; Sun, 04 Dec 2022 11:08:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p0Qdh80kbynSl9LCH3naFlq0wvbCk+tgsZdaOsanR1U=; b=Q616y+Ad8a3Dbtiyyemufvy/djuwm4QnrSQYmVDJ6J9QCLSnn0iYZAbxtKUdjQM06p aihPANZVKPF1g7CUjS3bqByNCWCDCLGfTEkK+1IFdkUq5EId5AM4x3hM69PcYyZ82zPz AwUozwIUW7Fn7+t/OTHATxvM7w8RB35doJL2gWqAV1vtW9+J0e0eHmW2Klm5u/z2PZcF 2aOFUf0C8mXQHVx7WiPlBCJ/qK+U7EGLZUd+JVx6UcFnflv0ASzI+96uxMsfkQWYzLoQ aH7uICAHoUxIvycA3gEX5pJt0OnaL1sab7uEA1G4HWefMLVG+5qpUtg3I+0u16YGvAgw 2eeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p0Qdh80kbynSl9LCH3naFlq0wvbCk+tgsZdaOsanR1U=; b=Mn7NqCG+B9bm9Avg7TTT0eUZnGLiDdSOYhH+ZH0xskn2GggRAF/Bl6O4yy/i+dav4g jPw2DOlOYg2AcX8A8aCL7+9Y2hSfPF41xxlCvlacKVLZCE3NSVfPguaW/DrYEVlZPky7 kOhldkflsJe3gjFYEQmb950TWFsOcJtikCaGiVC8YKGRa4jKz03i0hT1J+oA4aUa0pMw 9hs60OCjzuK2QOuPUnOMzcZ5pgQzlFEvFvWmJxTk1QCX/1XqIwSeCTWRMyEQKBSGuDqH 5ZEpie6dZo4lKAMoPhloiq+mil3F/iWAZSNZ2pAhsPdDFvJvAYnTby8SUcrofGMiy7r/ TaPw== X-Gm-Message-State: ANoB5plpWJGVeOS346cMj2bl9z7snGXkDQwG0Jv33TXPzKwDTtUbntK2 kYgwiRtt0OJRBIVsGh5CSSwQHVQ7O/U= X-Google-Smtp-Source: AA0mqf58dngLAXAjUAqDkB9ysIbLABNsEz0PFufNlKe9Vml4I8HCrcq+peS/3HSV/Y3iY07FZ8zr2Q== X-Received: by 2002:a17:906:8282:b0:7c0:aa3b:9bd6 with SMTP id h2-20020a170906828200b007c0aa3b9bd6mr15096737ejx.454.1670180887212; Sun, 04 Dec 2022 11:08:07 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:06 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 28/32] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Date: Sun, 4 Dec 2022 20:05:49 +0100 Message-Id: <20221204190553.3274-29-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Resolves duplicate code. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-39-shentey@gmail.com> --- hw/isa/piix.c | 65 +++++++-------------------------------------------- 1 file changed, 9 insertions(+), 56 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 035f64b928..f37851c5f4 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -367,7 +367,8 @@ static const MemoryRegionOps rcr_ops = { }, }; -static void pci_piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, + Error **errp) { PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); @@ -407,8 +408,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) /* USB */ if (d->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &d->uhci, - TYPE_PIIX3_USB_UHCI); + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type); qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { return; @@ -513,7 +513,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -543,7 +543,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -574,71 +574,24 @@ static const TypeInfo piix3_xen_info = { static void piix4_realize(PCIDevice *dev, Error **errp) { + ERRP_GUARD(); PIIXState *s = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "piix-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), NULL, errp)) { + pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp); + if (*errp) { return; } - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); - /* DMA */ - i8257_dma_init(isa_bus, 0); - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } From patchwork Sun Dec 4 19:05:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70E69C4321E for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:08 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 29/32] hw/isa/piix: Rename functions to be shared for interrupt triggering Date: Sun, 4 Dec 2022 20:05:50 +0100 Message-Id: <20221204190553.3274-30-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-40-shentey@gmail.com> --- hw/isa/piix.c | 56 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index f37851c5f4..3d1659e5fd 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -40,47 +40,47 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) +static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { - qemu_set_irq(piix3->pic.in_irqs[pic_irq], - !!(piix3->pic_levels & + qemu_set_irq(piix->pic.in_irqs[pic_irq], + !!(piix->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int level) { int pic_irq; uint64_t mask; - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq = piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= ISA_NUM_IRQS) { return; } mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); - piix3->pic_levels &= ~mask; - piix3->pic_levels |= mask * !!level; + piix->pic_levels &= ~mask; + piix->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level(PIIXState *piix, int pirq, int level) { int pic_irq; - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq = piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= ISA_NUM_IRQS) { return; } - piix3_set_irq_level_internal(piix3, pirq, level); + piix_set_irq_level_internal(piix, pirq, level); - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } -static void piix3_set_irq(void *opaque, int pirq, int level) +static void piix_set_irq(void *opaque, int pirq, int level) { - PIIXState *piix3 = opaque; - piix3_set_irq_level(piix3, pirq, level); + PIIXState *piix = opaque; + piix_set_irq_level(piix, pirq, level); } static void piix4_set_irq(void *opaque, int irq_num, int level) @@ -157,29 +157,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIXState *piix3) +static void piix_update_irq_levels(PIIXState *piix) { - PCIBus *bus = pci_get_bus(&piix3->dev); + PCIBus *bus = pci_get_bus(&piix->dev); int pirq; - piix3->pic_levels = 0; + piix->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); + piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq)); } } -static void piix3_write_config(PCIDevice *dev, - uint32_t address, uint32_t val, int len) +static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, + int len) { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIXState *piix3 = PIIX_PCI_DEVICE(dev); + PIIXState *piix = PIIX_PCI_DEVICE(dev); int pic_irq; - pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); - piix3_update_irq_levels(piix3); + pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix->dev)); + piix_update_irq_levels(piix); for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } } } @@ -201,7 +201,7 @@ static void piix3_write_config_xen(PCIDevice *dev, } } - piix3_write_config(dev, address, val, len); + piix_write_config(dev, address, val, len); } static void piix_reset(DeviceState *dev) @@ -261,7 +261,7 @@ static int piix3_post_load(void *opaque, int version_id) */ piix3->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level_internal(piix3, pirq, + piix_set_irq_level_internal(piix3, pirq, pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); } return 0; @@ -518,7 +518,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } - pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq, + pci_bus_irqs(pci_bus, piix_set_irq, piix3_pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } @@ -527,7 +527,7 @@ static void piix3_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->config_write = piix3_write_config; + k->config_write = piix_write_config; k->realize = piix3_realize; } From patchwork Sun Dec 4 19:05:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFF56C4321E for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:10 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 30/32] hw/isa/piix: Consolidate IRQ triggering Date: Sun, 4 Dec 2022 20:05:51 +0100 Message-Id: <20221204190553.3274-31-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Speeds up PIIX4 which resolves an old TODO. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-41-shentey@gmail.com> --- hw/isa/piix.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 3d1659e5fd..d05f1aa4ff 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -83,27 +83,6 @@ static void piix_set_irq(void *opaque, int pirq, int level) piix_set_irq_level(piix, pirq, level); } -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -275,7 +254,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr = 0; } - return 0; + return piix3_post_load(opaque, version_id); } static int piix3_pre_save(void *opaque) @@ -592,7 +571,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* RTC */ s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + pci_bus_irqs(pci_bus, piix_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -610,6 +589,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + k->config_write = piix_write_config; k->realize = piix4_realize; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; From patchwork Sun Dec 4 19:05:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC87EC3A5A7 for ; Sun, 4 Dec 2022 19:12:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1uLd-0002Lg-DE; Sun, 04 Dec 2022 14:08:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1uLZ-0002JF-24; Sun, 04 Dec 2022 14:08:17 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1uLW-0001jn-UD; Sun, 04 Dec 2022 14:08:16 -0500 Received: by mail-ej1-x633.google.com with SMTP id qk9so5327492ejc.3; Sun, 04 Dec 2022 11:08:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xPBJYaNb5t8JLFccVseFLIPVe5ir62CAXXTwo5Sx7Qs=; b=Q3ukOjQwopTt527Vytz7WFZt53fm/aBhoK5rhy5YZ/noEUKNuygtsGquKLlcZmCVeG V8OuZciHTKicMiY1wCSotYkxwRgX/fGCC+IB5avc1L6/sOXXxpdLIIy+RUXFN/yHA7tk Byy09W7FKjWUq9k8K2FupYQCQsB5zVMu8oeY6/i8tnk8Sol1Tkzxt66E052+2ongIm0u YAjsswTb4lRHC7O09gTUY+fHw1oXQJeCgIiznL7lQX8ENRPCvAPDDaCKAh9qgMNGM28a eCj+jh7MBcXoy+3tPAGCu9cG7is5V5iQNYjx2DjQSTBTGMuEKWp5CD5kN6g3a3AkHU+k 0APg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xPBJYaNb5t8JLFccVseFLIPVe5ir62CAXXTwo5Sx7Qs=; b=10mZMbj2fo1mgusYrNY53QbbHxXyvkymb8tSKTARNvs7FP9ZhplbYJE1/BlLY05JWk xADKdI69xvF83sUX90SEghzKhe3fNek9yIaCSOInAudCVoWvjYt88cicA0MDTvfDoYpg qaMjCmKbQSD28zSUaOrC27uWd8CDug9Ijv+GI1GBMxJvD5cST2hdb8OV+Imsj7vDuQzJ Rvs6NCHwfoCi0oN76O2bHLnLmq4ux1EB4Y/N33rNt4ssz6VeXZ8/rd+e9jVE4vorrh/m JJgck1xJTGLIsn47PH5UwENU8I+KB8abJOnn7j9hWOSG8631JfMtxP4H8k61dyjbG0UF Ipgg== X-Gm-Message-State: ANoB5pkh0DGPGAcC/ixmRWuBphGwSfiRNs+v8th8ZLQGjsnTW6W63/Tt nBzaqvp/aRI8bm7zkJsANaqhgsHhTeU= X-Google-Smtp-Source: AA0mqf53KPRJc1dTz1DouQM6GeflLVy4d4K53vsVm2pUfdKsClIK+ud9Sgw+2wrVeoaIIdpyaUisQA== X-Received: by 2002:a17:906:f2c8:b0:7c0:eeae:242d with SMTP id gz8-20020a170906f2c800b007c0eeae242dmr2443772ejb.672.1670180891986; Sun, 04 Dec 2022 11:08:11 -0800 (PST) Received: from localhost.localdomain (dynamic-089-012-182-051.89.12.pool.telefonica.de. [89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:11 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 31/32] hw/isa/piix: Share PIIX3 base class with PIIX4 Date: Sun, 4 Dec 2022 20:05:52 +0100 Message-Id: <20221204190553.3274-32-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Having a common base class allows for substituting PIIX3 with PIIX4 and vice versa. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-42-shentey@gmail.com> --- hw/isa/piix.c | 53 +++++++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index d05f1aa4ff..70fe1166c1 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -432,13 +432,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } -static void pci_piix3_init(Object *obj) +static void pci_piix_init(Object *obj) { PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_PROXY_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } static Property pci_piix_props[] = { @@ -449,7 +448,7 @@ static Property pci_piix_props[] = { DEFINE_PROP_END_OF_LIST(), }; -static void pci_piix3_class_init(ObjectClass *klass, void *data) +static void pci_piix_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); @@ -457,11 +456,8 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) dc->reset = piix_reset; dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; k->vendor_id = PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; k->class_id = PCI_CLASS_BRIDGE_ISA; /* * Reason: part of PIIX3 southbridge, needs to be wired up by @@ -472,13 +468,13 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) adevc->build_dev_aml = build_pci_isa_aml; } -static const TypeInfo piix3_pci_type_info = { +static const TypeInfo piix_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIXState), - .instance_init = pci_piix3_init, + .instance_init = pci_piix_init, .abstract = true, - .class_init = pci_piix3_class_init, + .class_init = pci_piix_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { TYPE_ACPI_DEV_AML_IF }, @@ -502,17 +498,29 @@ static void piix3_realize(PCIDevice *dev, Error **errp) pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } +static void piix3_init(Object *obj) +{ + PIIXState *d = PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); +} + static void piix3_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix_write_config; k->realize = piix3_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd = &vmstate_piix3; } static const TypeInfo piix3_info = { .name = TYPE_PIIX3_DEVICE, .parent = TYPE_PIIX3_PCI_DEVICE, + .instance_init = piix3_init, .class_init = piix3_class_init, }; @@ -539,15 +547,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) static void piix3_xen_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix3_write_config_xen; k->realize = piix3_xen_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd = &vmstate_piix3; } static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, .parent = TYPE_PIIX3_PCI_DEVICE, + .instance_init = piix3_init, .class_init = piix3_xen_class_init, }; @@ -579,8 +592,6 @@ static void piix4_init(Object *obj) { PIIXState *s = PIIX_PCI_DEVICE(obj); - object_initialize_child(obj, "pic", &s->pic, TYPE_PROXY_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } @@ -591,36 +602,20 @@ static void piix4_class_init(ObjectClass *klass, void *data) k->config_write = piix_write_config; k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->reset = piix_reset; - dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable = false; - dc->hotpluggable = false; - device_class_set_props(dc, pci_piix_props); } static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIXState), + .parent = TYPE_PIIX3_PCI_DEVICE, .instance_init = piix4_init, .class_init = piix4_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, }; static void piix3_register_types(void) { - type_register_static(&piix3_pci_type_info); + type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); type_register_static(&piix4_info); From patchwork Sun Dec 4 19:05:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13064007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29401C4321E for ; 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:08:13 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 32/32] hw/isa/piix: Drop the "3" from the PIIX base class Date: Sun, 4 Dec 2022 20:05:53 +0100 Message-Id: <20221204190553.3274-33-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that the base class is used for both PIIX3 and PIIX4, the "3" became misleading. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-43-shentey@gmail.com> --- hw/isa/piix.c | 8 ++++---- include/hw/southbridge/piix.h | 6 ++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 70fe1166c1..84b27b36ea 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -469,7 +469,7 @@ static void pci_piix_class_init(ObjectClass *klass, void *data) } static const TypeInfo piix_pci_type_info = { - .name = TYPE_PIIX3_PCI_DEVICE, + .name = TYPE_PIIX_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIXState), .instance_init = pci_piix_init, @@ -519,7 +519,7 @@ static void piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_info = { .name = TYPE_PIIX3_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix3_init, .class_init = piix3_class_init, }; @@ -559,7 +559,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix3_init, .class_init = piix3_xen_class_init, }; @@ -608,7 +608,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix4_init, .class_init = piix4_class_init, }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index a489f52d1b..65ad8569da 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -72,11 +72,9 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIXState; -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) +#define TYPE_PIIX_PCI_DEVICE "pci-piix" +OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE) #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"