From patchwork Mon Dec 5 13:26:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91911C4708D for ; Mon, 5 Dec 2022 13:27:21 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453612.711190 (Exim 4.92) (envelope-from ) id 1p2BUm-0004AA-OV; Mon, 05 Dec 2022 13:26:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453612.711190; Mon, 05 Dec 2022 13:26:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BUm-0004A3-LN; Mon, 05 Dec 2022 13:26:56 +0000 Received: by outflank-mailman (input) for mailman id 453612; Mon, 05 Dec 2022 13:26:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BUk-00049F-Fz for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 13:26:54 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20600.outbound.protection.outlook.com [2a01:111:f400:fe5a::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 74e7f7da-74a0-11ed-8fd2-01056ac49cbb; Mon, 05 Dec 2022 14:26:43 +0100 (CET) Received: from DM6PR10CA0012.namprd10.prod.outlook.com (2603:10b6:5:60::25) by PH8PR12MB6721.namprd12.prod.outlook.com (2603:10b6:510:1cc::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14; Mon, 5 Dec 2022 13:26:46 +0000 Received: from DS1PEPF0000E641.namprd02.prod.outlook.com (2603:10b6:5:60:cafe::a0) by DM6PR10CA0012.outlook.office365.com (2603:10b6:5:60::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 13:26:46 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by DS1PEPF0000E641.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.8 via Frontend Transport; Mon, 5 Dec 2022 13:26:45 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:26:45 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:26:45 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:26:43 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 74e7f7da-74a0-11ed-8fd2-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cFyJLuYHDAIn48Sy2YpkbkjA4jezam42kxGxPe73uLF5ebb88lLvbg+3boSSvEPrMT7QOZDe0yLwsKknpBqfdwmHhinYiXwdJLxqpu4C5lxQ7kmOM1KsZgjH7puWNUWPmygSWqIfrwl0of3M6KTuk53K5PF7b0bHLwo+wVW1kaCQThm2J76AXPFLtsDuqi8T8EP5iByDrt8D86g29FjZiFowTCi8qd2crKUHhTviEbJnQkZlWvraCCRm5q63a4Lc5rxjwXUh2vIw5vUiWkrCkHhSEqlsGmUHaMM3Xxg+uXDMTLYFnLuKXVUzHPurX8SLF6PcRzoHJ9oe7s4XhlZKaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IfUXAZQrIKkiNagnHJ7wx2BrbdiMgcEKOEdkkFLHNBg=; b=ZCe0oI5AYCFt/kZpqYoCOOo7BBnSn7jzVwq8tEMfPH1PF+Prlr8pfZBA/RJR9WEIBGvKF0yowcXeVv0G3VzxIx1S7xsd6HXwfzu8qOiRC3ZXHC4duGpPMELOF/Ua8SuR7O9hf8mF1vZ9IkkuawSorSDl1UyOVL+Xe+IJv0qqyrNiswXG254bQ7dYQgCKIcc4QSvyDANmNfvLhSH5cPu5w6o4G/l8non5ubVoZ6fIUWqRbzWclr6tcfU7NR8LSsMDKoLJNPl+1IdJortOvKO0sqQ8ASmGxGunIH5StzSRQl06957X++SJ0/SHNfggu/Tt6cn0845tT73d92PCZlNtag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IfUXAZQrIKkiNagnHJ7wx2BrbdiMgcEKOEdkkFLHNBg=; b=FlapATERC5NBLJkpZI2R/5GB3J/OBJYsN4+KCK+P2W4MYMXW+Jmxd4NtojaIApmwbh7wp8kEMeBCW+i+RqoYimSRL53bIWgZYwnLUMknhJzzMkJwOg/9Ra3FLB747QQ9YYYIpLbXNw6xDi9NYrmyLwrJBg8ZQmGfpuItL3Yv4S0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 01/11] xen/Arm: vGICv3: Sysreg emulation is applicable for AArch64 only Date: Mon, 5 Dec 2022 13:26:27 +0000 Message-ID: <20221205132637.26775-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E641:EE_|PH8PR12MB6721:EE_ X-MS-Office365-Filtering-Correlation-Id: cb7d4285-0378-4cef-0ee6-08dad6c45b1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DtUG7Y2TKr+hHyLe/vUG95Qg5lghnfDgXdOLlHNWCyf2cBoAFvAQNRkLnfwLVJ9yanGO+CPB5OCh8bDoGN5MjLQqI3/yFbrTNtu280CQp9+fmwQezcQZX/7t583t7y8V7AwvRAIxZfx5i53MEK4oA62M6S5xqtRwYqpqqI/URTItI8j3TwWWHcCw1VO3LOaaxifp7BtAU60mkXuKSb+2TCvgnKAyHLkNkPrNZ415U2JIYMocttJ2GDQRwb9GLRIgXynCkyXKU+leW6MghafdG+qNjNe4S2Q8LdrIrqS4q6Zlp9dL4Jy/3cRAQxJz9KYIbgQm6Kvrb6FXeOD9mAUxIASvmAUskqQSnCLUtmzGCj+LV2YkxkOETmJOTi5y694ScjqcQRY+EmAgIA5ZMIRkQN7IIT9a2r87WuW2IALZ9WYP/wSMj44PQKtZEvU6bI2sJzIkMgh9euUy6eAVSdNWlHPCpjCLRH3ZqZrAAoDOUD5aTxrqp6ba5V0EbBpJmnhpXe6C1sQS/lz44u/tpUA2DsKmHsuwSu5pJj5GPqw9Qjsjui1nL8kCUjQ72VWWO3N8USXfTdAdIDQqM7hEDKU3A/5fZQ3feHTiVvIeAqLgme7bKdQf9E5RUfXs7N9ge94G7FncdghJ8GLMXGdcARCbIksF84wNGxmDtR/sAZ/PL3XGsh+wuCQ1mfE2sNQJqZZZPCzKJWQs6jfTUMg0uVu6iJqM7HRl3TtAW0HGx1esrNs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199015)(40470700004)(46966006)(36840700001)(4326008)(8676002)(336012)(82740400003)(81166007)(356005)(54906003)(6916009)(83380400001)(316002)(103116003)(40460700003)(26005)(186003)(426003)(5660300002)(47076005)(40480700001)(82310400005)(70206006)(70586007)(36756003)(2906002)(8936002)(36860700001)(41300700001)(1076003)(2616005)(6666004)(86362001)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 13:26:45.6130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb7d4285-0378-4cef-0ee6-08dad6c45b1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E641.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6721 Sysreg emulation is 64-bit specific, so guard the calls to vgic_v3_emulate_sysreg() as well as the function itself with "#ifdef CONFIG_ARM_64". Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from - v1 - 1. Updated the commit message. v2 - 1. Updated the commit message (removed the reference to Arm ARM as it is not required). v3 - No changes. Added Rb and Ack. v4 - No changes. xen/arch/arm/vgic-v3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 015446be17..3f4509dcd3 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1519,6 +1519,7 @@ static bool vgic_v3_emulate_sgi1r(struct cpu_user_regs *regs, uint64_t *r, } } +#ifdef CONFIG_ARM_64 static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_sysreg sysreg = hsr.sysreg; @@ -1539,6 +1540,7 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) return false; } } +#endif static bool vgic_v3_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) { @@ -1562,8 +1564,10 @@ static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr) { switch (hsr.ec) { +#ifdef CONFIG_ARM_64 case HSR_EC_SYSREG: return vgic_v3_emulate_sysreg(regs, hsr); +#endif case HSR_EC_CP15_64: return vgic_v3_emulate_cp64(regs, hsr); default: From patchwork Mon Dec 5 13:26:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2AF8C47089 for ; Mon, 5 Dec 2022 13:27:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453613.711197 (Exim 4.92) (envelope-from ) id 1p2BUn-0004Dm-6n; Mon, 05 Dec 2022 13:26:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453613.711197; Mon, 05 Dec 2022 13:26:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BUm-0004DF-Uk; Mon, 05 Dec 2022 13:26:56 +0000 Received: by outflank-mailman (input) for mailman id 453613; Mon, 05 Dec 2022 13:26:56 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BUm-0003tw-15 for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 13:26:56 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20605.outbound.protection.outlook.com [2a01:111:f400:fe5a::605]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7b894013-74a0-11ed-91b6-6bf2151ebd3b; Mon, 05 Dec 2022 14:26:55 +0100 (CET) Received: from CY5PR22CA0096.namprd22.prod.outlook.com (2603:10b6:930:65::18) by SA0PR12MB4350.namprd12.prod.outlook.com (2603:10b6:806:92::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14; Mon, 5 Dec 2022 13:26:50 +0000 Received: from CY4PEPF0000C96B.namprd02.prod.outlook.com (2603:10b6:930:65:cafe::9d) by CY5PR22CA0096.outlook.office365.com (2603:10b6:930:65::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.8 via Frontend Transport; Mon, 5 Dec 2022 13:26:50 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000C96B.mail.protection.outlook.com (10.167.241.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.8 via Frontend Transport; Mon, 5 Dec 2022 13:26:49 +0000 Received: from SATLEXMB07.amd.com (10.181.41.45) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:26:49 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 05:26:49 -0800 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:26:47 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7b894013-74a0-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CjbTYsUjb+nLHquy43Grsrz+CI1ubK8odms74Dv3qf5Wg/FzvlmSNTHyDfxpt6fWTraTK0kGNoK9o7sRDN09xCXChpeivmhMB8wecJ1muVvM50xoewgde7sitPvkjVp0eRyG5oPa59lGNuM/2Z6Ru9uppTkTa7FZu7mTdtLzNtgpDHnD+88TfpbaH3uFxOKuWOz6G34TlYFfhLM9B9IBBH6AsSxho8YYyVIBexcgt1IGZLAqa9AYu+0ecQG9LmVGp2NKUrI4mm58/07O0k/TWJlrQJPFweO6ajEQZKxTqOKzQFTHFF+YOwO7W056CHelapWjNOuN7sblKJHYWpNhcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GvCRxtMbB9wFwtRZRm0PuriMjLF60alBSHXkTWtslew=; b=d9W72t9cYlWX4ZiH/ly7QA1h9GeERjJfVH5shiA9mwvK72JvxzZCCbFPtbw1V2X0aCe1oMTgD7zxDW3Rg8bs4MusXy7tZU3SlqMdeL+jRSvkmvEpq5pbv4idze+sTU/LcD6UWZ/8ub7nfY/D4xg3JrDI5EcPPNz4HiVxhuK5GNG23OlZZ7ncd7+VrbagiN5iFkrg38wCWUrQWTtM8Zq6ZRW1h2qpYT/0LFW7H7NJiM/9TficvrahewNF/JDY++5qtalEuEzel1OVbgFVn1r0RwH2tvJlEqpvUwEdj3bnCANNCOCBcMOdiLD2wcixyx3tL1H25CF2t7hf7J8EYpzwig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GvCRxtMbB9wFwtRZRm0PuriMjLF60alBSHXkTWtslew=; b=C79XHFX6ld8jInchh+n9qG147LRf7oBhvi7rjzp2VNDf5FDdE6j+yODScl0vqX+dOgHUjSCZ4gocEJ1gaCDC77OlBb0Zb3HimoGmF2gYD2mu9niKnX0sIGYIY5AFvLjkMJpZ6bZEPpUJmPer23b43W5gLqqDkPM5v6ZGrGkucic= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 02/11] xen/Arm: GICv3: Do not calculate affinity level 3 for AArch32 Date: Mon, 5 Dec 2022 13:26:28 +0000 Message-ID: <20221205132637.26775-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C96B:EE_|SA0PR12MB4350:EE_ X-MS-Office365-Filtering-Correlation-Id: 3025d731-b757-47ab-cc91-08dad6c45dae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Lahkle87zdiX0/Kcna0OxU0OfyiSiADg/Dxg7IScQnzRtjcSHZewdh6WQcR6WGKOar0LhgCexQoH5JT412o1MSbcYksyERNB6kw0nv3QG9vfDyuIP99hTid04AnS2ny9+Tf5K+oxIxDSKBgeng5jdDOHXuPzOjuY/CrH/OJxXgvyx1K3yVbY7Nl+P74wAqOGuVy7Q1XXGea2Z3BNvX3kDWiOK3w+lNAj2SW5Mw/Zb5qGuqiF6uExdyU0QLZBpn/upVSWLtRmMZWkF2MtbdRb4Ozp9dWjUNu/bQI7VcxHTgKOanIJCnMHkxzHB7AeqE/M+DyKvPcZ/H7kpsMMRGejRMz6ZnK9pwRoh+BU3jHv/aWMybFiD9/k5o0g1EIE2j0Ohdtk7qx0eKm4cp5VZEjO/kWgm1HtNphEfVK2Ipkw1eIYhzfAHXTAqUmGZy4cCCLLjf7w4L7rHt5g3IP6nZp7tOnGdjzParT8ykmLjMuYkg7c//5leQSDMcoMT30aNXh1Zkw88fmlXXM8eUBFXBWajeZUtpaTFSMtXpnUjhuF5os8TCNd2jlgFfl6RWj/E9WZ2i1j+ZimtUVmushswFveJEmQMIniDLvXNLgbl7VQ+W3QIb/rZSPNfL8dg6/iHr5Z3Vw1v/sGYNYizfd/lU5skTi3rMTZTpuLJPrW35po5fitWmVNHpDO8IiEV4IskqCgh46UzDpXO/aqGdgeKAUwyXIghugVxndvqhCx/+ZMWJM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199015)(40470700004)(36840700001)(46966006)(6916009)(83380400001)(54906003)(70586007)(70206006)(478600001)(2616005)(6666004)(316002)(103116003)(82310400005)(40480700001)(1076003)(40460700003)(36860700001)(86362001)(186003)(36756003)(2906002)(26005)(8676002)(4326008)(41300700001)(356005)(47076005)(5660300002)(81166007)(426003)(8936002)(82740400003)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 13:26:49.8923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3025d731-b757-47ab-cc91-08dad6c45dae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C96B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4350 Refer ARM DDI 0487I.a ID081822, G8-9817, G8.2.169 Affinity level 3 is not present in AArch32. Also, refer ARM DDI 0406C.d ID040418, B4-1644, B4.1.106, Affinity level 3 is not present in Armv7 (ie arm32). Thus, any access to affinity level 3 needs to be guarded within "ifdef CONFIG_ARM_64". Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from - v1 - NA (as it is a new patch) v2 - NA (as it is a new patch) v3 - Modified the title. Added Rb. v4 - Added Ack. xen/arch/arm/gic-v3.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 018fa0dfa0..64a76307dd 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -527,7 +527,10 @@ static void gicv3_set_pending_state(struct irq_desc *irqd, bool pending) static inline uint64_t gicv3_mpidr_to_affinity(int cpu) { uint64_t mpidr = cpu_logical_map(cpu); - return (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | + return ( +#ifdef CONFIG_ARM_64 + MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | +#endif MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); @@ -720,7 +723,10 @@ static int __init gicv3_populate_rdist(void) * Convert affinity to a 32bit value that can be matched to GICR_TYPER * bits [63:32] */ - aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | + aff = ( +#ifdef CONFIG_ARM_64 + MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | +#endif MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); @@ -972,7 +978,10 @@ static void gicv3_send_sgi_list(enum gic_sgi sgi, const cpumask_t *cpumask) * Prepare affinity path of the cluster for which SGI is generated * along with SGI number */ - val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 | + val = ( +#ifdef CONFIG_ARM_64 + MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 | +#endif MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 | sgi << 24 | MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 | From patchwork Mon Dec 5 13:26:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E95BC4321E for ; Mon, 5 Dec 2022 14:47:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453790.711381 (Exim 4.92) (envelope-from ) id 1p2Cky-0000ow-4O; Mon, 05 Dec 2022 14:47:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453790.711381; Mon, 05 Dec 2022 14:47:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cky-0000op-0y; Mon, 05 Dec 2022 14:47:44 +0000 Received: by outflank-mailman (input) for mailman id 453790; Mon, 05 Dec 2022 14:47:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Ckw-0000oh-K1 for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:47:42 +0000 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on20601.outbound.protection.outlook.com [2a01:111:f400:7eae::601]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c4507d18-74ab-11ed-8fd2-01056ac49cbb; Mon, 05 Dec 2022 15:47:41 +0100 (CET) Received: from BN0PR08CA0021.namprd08.prod.outlook.com (2603:10b6:408:142::16) by SA1PR12MB6797.namprd12.prod.outlook.com (2603:10b6:806:259::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13; Mon, 5 Dec 2022 14:47:37 +0000 Received: from BN8NAM11FT086.eop-nam11.prod.protection.outlook.com (2603:10b6:408:142:cafe::ff) by BN0PR08CA0021.outlook.office365.com (2603:10b6:408:142::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:47:37 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT086.mail.protection.outlook.com (10.13.176.220) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.13 via Frontend Transport; Mon, 5 Dec 2022 14:47:37 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:27:02 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:27:00 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c4507d18-74ab-11ed-8fd2-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I8aBEn4sTthDS7VfhuyWdxo/1YCfOTWnj6fG3CcW6qPw/UFlIdGj06Nac/8DMfmwumfk+vU1rmGg9Dk2DclmL23FYymJ4hKN4cVdDPJyyR/6a3mfdLm3mYpUHeTECPbJbCxib0ICANJqSIpltRtluG3UKIV+l1pO1UmVbRYmwBhjHtSQjZjVULO63OOjf1X3xRZ/CoCy1lNjTkpWVHs6gKdZ/631a31EbTYEFZwnjkapJQsGfAqUIr7HwRtFJnA491A4f8eaxYwFtc8ILHDQaHsFbR2V63vu/8Lhq4PtyERrVWAV1v6ruafKmXwfuE7PtZjLm87dHFXoVWypiaBKrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=D7jRyeelaoFeHR1J25tVrU6dQKXjWC8IP5yvkiKz9nw=; b=davqFUNXXFRTngJt3K791MuPfa2vvdeIfP8viV6e9No+w59Gt37UT/pWKTMe6M6+M+lEsIq/Ue5C+xTBp4CwpXkrHyRlZkRTDS8f8Mj9DeK9vAnMBTNA/uPJgASznqkdqEM5nN+6etZrczrwy2izEjYcHxdAxRNurXH/Mr0gbnsuZhz3cSiH6siIcqNb5AiVMOmptfkymGDvXZw1FlKjz3/MrNmuWOwlyVOwb2PS62cVG34J04qh9dEvhr9ndu3J55UGsM4DUJsiBa2bNCExYbi0v55i8LJtRiALLAvsldvOmSslP8p0uJnX4yHXyAbudKJMzDZt1LSPoS8iTd4aGw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=D7jRyeelaoFeHR1J25tVrU6dQKXjWC8IP5yvkiKz9nw=; b=oRuMlW0N0Aa5v1gs/DTlJwPC/DY7+BkP3fdtY4jpRAfxavcd6WMYNeAD4d4amgEXvjuoCQ+41f0hyygVY/H0Moir+Ttq+VcvK5fLk662z4PE53gKzLpieQipgYkAsGr27qso4SAxjQJvF8F+3byiR2T63AZbnaVtSymCYBl0A1k= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 03/11] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32 Date: Mon, 5 Dec 2022 13:26:29 +0000 Message-ID: <20221205132637.26775-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT086:EE_|SA1PR12MB6797:EE_ X-MS-Office365-Filtering-Correlation-Id: 952e0f3f-7674-4d46-a662-08dad6cfa6c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rePy4W4OS3UHnJVU7148FOn6w+2bW+1P4BBDSar2WgE3TUrHK/lIcWeD8UCGIveSzcQn/FQvhSi/mMzmp/dmdT8GMs6l0aDQUtQ85fcUu/+/VXH6Azz9ZEtQtHqXiz2ExbovF2mz9dlhPdqjgfmbuEKJ6Obj4FSO+MqG9JAnFC3b1v13XCx2UPol7FUTpOb+uKyRt6MVu7aPPwSy2cQIcbHiT9oC20pFxn5RLDtjm0ynwPpa9ZiDrx5x9RkRJKFWh8/ia2IVM3gBELu0PhZdVSSIYjk9XvwIAjVW3oj6UlLmlcah10nVNmAp4dgxan2v8aCeDgx3UWGr1YL0X5jEKVHu2+ktrrAMsqxbi05WGc9dsgX1/5Yu9N14Qqdq01LMncRK17mg32EgzxpqfqTZuGAifXe28YQ3h/okHQmtG5wdG5VQOPM2J+29JteTDP77Ns4/k/063+CqzoZM6EqQicM51lD1rPIP+4v6oiYMEDdt6sPfQpA54cAHPdfLFKvEUZHow6obkEBrqQf1b+PW/94g7qdnzEdRkgBs8EB5wZfA/LoDtK2iFuVMF7IdX5zMk/8zTZdmCJyVQuzbc4/20+15zA4Il0dukWQBhM7nWf2fFkFKnqOV4dsiPCHuglM3Dp/AQKJpcc++D10GYiCdEzDAs9kMGfso35ZerhOVKi5Xkcjvkxr5Z6WqY6Vh/baLPVrKD8LRwRb/5tEYQLzJs1VMQwZH9kXJcDV0sOP5jm8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(46966006)(36840700001)(40470700004)(36860700001)(356005)(2906002)(82740400003)(5660300002)(336012)(103116003)(47076005)(86362001)(81166007)(40460700003)(426003)(83380400001)(26005)(1076003)(186003)(478600001)(6666004)(54906003)(6916009)(8676002)(40480700001)(4326008)(316002)(8936002)(41300700001)(70206006)(2616005)(36756003)(70586007)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:47:37.0292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 952e0f3f-7674-4d46-a662-08dad6cfa6c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6797 In some situations (e.g. GICR_TYPER), the hypervior may need to emulate 64bit registers in AArch32 mode. In such situations, the hypervisor may need to read/modify the lower or upper 32 bits of the 64 bit register. In AArch32, 'unsigned long' is 32 bits. Thus, we cannot use it for 64 bit registers. While we could replace 'unsigned long' by 'uint64_t', it is not entirely clear whether a 32-bit compiler would not allocate register for the upper 32-bit. Therefore fold vreg_reg_* helper in the size specific one and use the appropriate type based on the size requested. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from - v1 - 1. Remove vreg_reg_extract(), vreg_reg_update(), vreg_reg_setbits() and vreg_reg_clearbits(). Moved the implementation to vreg_reg##sz##_*. 'mask' and 'val' is now using uint##sz##_t. v2 - 1. Use 'unsigned int' for 'shift' variable. 2. Updated the commit message. v3 - 1. No changes. Added Rb and Ack. v4 - 1. No changes. xen/arch/arm/include/asm/vreg.h | 86 ++++++++------------------------- 1 file changed, 19 insertions(+), 67 deletions(-) diff --git a/xen/arch/arm/include/asm/vreg.h b/xen/arch/arm/include/asm/vreg.h index f26a70d024..d92450017b 100644 --- a/xen/arch/arm/include/asm/vreg.h +++ b/xen/arch/arm/include/asm/vreg.h @@ -89,106 +89,58 @@ static inline bool vreg_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr * The check on the size supported by the register has to be done by * the caller of vreg_regN_*. * - * vreg_reg_* should never be called directly. Instead use the vreg_regN_* - * according to size of the emulated register - * * Note that the alignment fault will always be taken in the guest * (see B3.12.7 DDI0406.b). */ -static inline register_t vreg_reg_extract(unsigned long reg, - unsigned int offset, - enum dabt_size size) -{ - reg >>= 8 * offset; - reg &= VREG_REG_MASK(size); - - return reg; -} - -static inline void vreg_reg_update(unsigned long *reg, register_t val, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VREG_REG_MASK(size); - int shift = offset * 8; - - *reg &= ~(mask << shift); - *reg |= ((unsigned long)val & mask) << shift; -} - -static inline void vreg_reg_setbits(unsigned long *reg, register_t bits, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VREG_REG_MASK(size); - int shift = offset * 8; - - *reg |= ((unsigned long)bits & mask) << shift; -} - -static inline void vreg_reg_clearbits(unsigned long *reg, register_t bits, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VREG_REG_MASK(size); - int shift = offset * 8; - - *reg &= ~(((unsigned long)bits & mask) << shift); -} /* N-bit register helpers */ #define VREG_REG_HELPERS(sz, offmask) \ static inline register_t vreg_reg##sz##_extract(uint##sz##_t reg, \ const mmio_info_t *info)\ { \ - return vreg_reg_extract(reg, info->gpa & (offmask), \ - info->dabt.size); \ + unsigned int offset = info->gpa & (offmask); \ + \ + reg >>= 8 * offset; \ + reg &= VREG_REG_MASK(info->dabt.size); \ + \ + return reg; \ } \ \ static inline void vreg_reg##sz##_update(uint##sz##_t *reg, \ register_t val, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ + unsigned int offset = info->gpa & (offmask); \ + uint##sz##_t mask = VREG_REG_MASK(info->dabt.size); \ + unsigned int shift = offset * 8; \ \ - vreg_reg_update(&tmp, val, info->gpa & (offmask), \ - info->dabt.size); \ - \ - *reg = tmp; \ + *reg &= ~(mask << shift); \ + *reg |= ((uint##sz##_t)val & mask) << shift; \ } \ \ static inline void vreg_reg##sz##_setbits(uint##sz##_t *reg, \ register_t bits, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ - \ - vreg_reg_setbits(&tmp, bits, info->gpa & (offmask), \ - info->dabt.size); \ + unsigned int offset = info->gpa & (offmask); \ + uint##sz##_t mask = VREG_REG_MASK(info->dabt.size); \ + unsigned int shift = offset * 8; \ \ - *reg = tmp; \ + *reg |= ((uint##sz##_t)bits & mask) << shift; \ } \ \ static inline void vreg_reg##sz##_clearbits(uint##sz##_t *reg, \ register_t bits, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ - \ - vreg_reg_clearbits(&tmp, bits, info->gpa & (offmask), \ - info->dabt.size); \ + unsigned int offset = info->gpa & (offmask); \ + uint##sz##_t mask = VREG_REG_MASK(info->dabt.size); \ + unsigned int shift = offset * 8; \ \ - *reg = tmp; \ + *reg &= ~(((uint##sz##_t)bits & mask) << shift); \ } -/* - * 64 bits registers are only supported on platform with 64-bit long. - * This is also allow us to optimize the 32 bit case by using - * unsigned long rather than uint64_t - */ -#if BITS_PER_LONG == 64 VREG_REG_HELPERS(64, 0x7); -#endif VREG_REG_HELPERS(32, 0x3); #undef VREG_REG_HELPERS From patchwork Mon Dec 5 13:26:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F755C4321E for ; Mon, 5 Dec 2022 14:48:08 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453791.711392 (Exim 4.92) (envelope-from ) id 1p2ClC-0001AO-Gb; Mon, 05 Dec 2022 14:47:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453791.711392; Mon, 05 Dec 2022 14:47:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2ClC-0001AH-DQ; Mon, 05 Dec 2022 14:47:58 +0000 Received: by outflank-mailman (input) for mailman id 453791; Mon, 05 Dec 2022 14:47:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2ClB-0000oh-OX for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:47:57 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2062b.outbound.protection.outlook.com [2a01:111:f400:fe59::62b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id cdbd5fcf-74ab-11ed-8fd2-01056ac49cbb; Mon, 05 Dec 2022 15:47:57 +0100 (CET) Received: from BN7PR06CA0042.namprd06.prod.outlook.com (2603:10b6:408:34::19) by DM4PR12MB5280.namprd12.prod.outlook.com (2603:10b6:5:39d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14; Mon, 5 Dec 2022 14:47:53 +0000 Received: from BN8NAM11FT083.eop-nam11.prod.protection.outlook.com (2603:10b6:408:34:cafe::dd) by BN7PR06CA0042.outlook.office365.com (2603:10b6:408:34::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:47:53 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT083.mail.protection.outlook.com (10.13.177.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:47:53 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:27:19 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:27:18 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: cdbd5fcf-74ab-11ed-8fd2-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bS4hSfbrelHttQWuFtSJhpjPEd+6qyph1H0p1ej8t/inKnxeXrUMNkk0vPSjU4xWjknNXHliFvi2o2ajqMFkwjjRCZgO0U+m+tawv0XHtn/ryIzVn8Nbvo+jqmRmiylw/DMkE83li16JG9FI8EFAMrm/qsdBkgaqup3V/JJl7SaUc1g06m463uLJGfvbOPfT8kLeFStVur88M9KybSDIIjUsX1SXnK6k1skVcY7kVDjA4JA8Hw3XAR4Lca2tEZZmXeoGJnIQp1jw3AK2up5D+LwTXypCRyJBCmkq2r8XGqg1Bm8G0cQgey+MA3J8qnL104nfGZfheDrhcBgAOQuUHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZbBy4ttF/x3KcPy08K/eQwu1bbiSIC1Vmw+/9aMnPtA=; b=XfWyw6wnH68IRsxu5i/x4MVWrOk3NQwNh/zrP6tPmKCxyXwwW0bZX9nfyFzDBgTUcnEoCZXrOHNHW+HpFhx/KOzOuGMjT9QW6cx4qHL2BH3qRG4r8hiCCxXFHh9qdxVeZJh4V3pFRMN/La8qKJ9kfMoPKoV0JUA0vpLxJ5Ft0QmP+KMe6oQHuktNAhiJL/xETHxi6ugtI5ffvsCoBjJdDeFacvfUeAXhJD2/hfmogcn9QqOij2vePMRXyjgpRtF7dyrrO8Gp7OCH0K97gJCkjjOEFycSWl0gpKxLg7GUTOU4l+H549TOSbQAHIcNlYgSLEpWAEfpM91ie1w8BjIsvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZbBy4ttF/x3KcPy08K/eQwu1bbiSIC1Vmw+/9aMnPtA=; b=xyAmpNaTzqFfDB8BROW9BgqjSIDo6TenvDeXNSjTukvCGX2PqX9q4FZWRYsWMliOtpVENLnxYthF+imIXZK4taXUNh+/aX0Xl4mUb9awtfiWVIWCkZcZQPfbRS1no+7+Kv8e9+q0N/CvLiJqrzOlqbiMoT+0R/5z9CnSPdCAEiQ= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 04/11] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 Date: Mon, 5 Dec 2022 13:26:30 +0000 Message-ID: <20221205132637.26775-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT083:EE_|DM4PR12MB5280:EE_ X-MS-Office365-Filtering-Correlation-Id: 0568ba9b-2722-4525-152c-08dad6cfb082 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0pYL+xASgdD4C4AzsJe/vYoKy7G6PkqGVu/JZcr2+tnqmcOAelwtEnPzIor4Ea651voxFgFLegnQRviljNNqStG8tlQJHLAYHGoz94b/a/Vj9O1mxXWPjfFxwS5AbZtOiICwf1+1AjfRWujDZ8jAjg0jZcqLNHOaWnFQS1ktDFpTJvPWNFpJ5dwomtob3ch/0imXBZvwkmwxKsc//+QllfUE1nAv3Fb9y2ROI6fP6gzjwLYIfy/ebJWHEB4kSh4LHmBkhDGk+ZDME+Avs2xlgs8ycYll30R1OvZeVR+55N0BXs5944thuMug54C7fIMKAfuXDDozZOzZtygmpVoFuZ7viu7Xtj2JCjmgFhZZ6xB5v4wH2G8CH33bEuWkibfC4VjLSaa3MXcPsGh5z9rrxKRSslWWbkP6Q1Xq5XHGsG0Sh2qJNVj+XoPmEMNOPWV0IXk+lMfnqi/dvFeg+eNqP4EFiSi6B4NkDNRCZv14Bin703uj9Wh/0EnfSTQI6IvU68/lUr4CKXFgCgBtNuWiooGnXS5ygApxoD8MtlNp9Ywc9TcWDB8AZWn0bTElS7Rxf8VHzENQA8zqgGCXp2yHeQYqblsSLfr2aNxymwYl6Dm1EK2dMIG0VTlCKXn78S2Ag/nWwGGjH6fDWyRFMklAJMZ3wuonXY+Tg5Ud4YjZK0JTNeWz36P0Jtn9HkYBvdoZtW9oJtlIHSSVCfbL6uj6VjXOWo15tYKEfx6VyPXfz9k= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(39860400002)(346002)(376002)(451199015)(46966006)(36840700001)(40470700004)(1076003)(336012)(186003)(47076005)(2616005)(426003)(82310400005)(82740400003)(41300700001)(5660300002)(4326008)(70206006)(8676002)(36756003)(70586007)(83380400001)(86362001)(81166007)(356005)(478600001)(40460700003)(40480700001)(103116003)(6666004)(54906003)(26005)(6916009)(316002)(36860700001)(2906002)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:47:53.3923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0568ba9b-2722-4525-152c-08dad6cfb082 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT083.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5280 Refer ARM DDI 0487I.a ID081822, G8-9650, G8.2.113 Aff3 does not exist on AArch32. Also, refer ARM DDI 0406C.d ID040418, B4-1644, B4.1.106 Aff3 does not exist on Armv7 (ie arm32). Thus, access to aff3 has been protected with "#ifdef CONFIG_ARM_64". Also, v->arch.vmpidr is a 32 bit register on AArch32. So, we have assigned it to 'uint64_t vmpidr' to perform the shifts. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - Assigned v->arch.vmpidr to "uint64_t vmpdir". Then, we can use MPIDR_AFFINITY_LEVEL macros to extract the affinity value. v2 - 1. "MPIDR_AFFINITY_LEVEL(vmpidr, 3)" is contained within "#ifdef CONFIG_ARM_64". 2. Updated commit message. v3 - 1. Added an inline comment to explain type widening for v->arch.vmpidr. 2. Updated the commit message. Added Rb. v4 - 1. Added Ack. xen/arch/arm/vgic-v3.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 3f4509dcd3..e0b636b95f 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -191,12 +191,20 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG64(GICR_TYPER): { uint64_t typer, aff; + /* + * This is to enable shifts greater than 32 bits which would have + * otherwise caused overflow (as v->arch.vmpidr is 32 bit on AArch32). + */ + uint64_t vmpidr = v->arch.vmpidr; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; - aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32); + aff = ( +#ifdef CONFIG_ARM_64 + MPIDR_AFFINITY_LEVEL(vmpidr, 3) << 56 | +#endif + MPIDR_AFFINITY_LEVEL(vmpidr, 2) << 48 | + MPIDR_AFFINITY_LEVEL(vmpidr, 1) << 40 | + MPIDR_AFFINITY_LEVEL(vmpidr, 0) << 32); typer = aff; /* We use the VCPU ID as the redistributor ID in bits[23:8] */ typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT; From patchwork Mon Dec 5 13:26:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DE5FC4321E for ; Mon, 5 Dec 2022 14:48:18 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453797.711403 (Exim 4.92) (envelope-from ) id 1p2ClN-0001eU-O6; Mon, 05 Dec 2022 14:48:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453797.711403; Mon, 05 Dec 2022 14:48:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2ClN-0001eL-L3; Mon, 05 Dec 2022 14:48:09 +0000 Received: by outflank-mailman (input) for mailman id 453797; Mon, 05 Dec 2022 14:48:09 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2ClM-0001AR-Ve for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:48:08 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2062e.outbound.protection.outlook.com [2a01:111:f400:fe5a::62e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d36c13e7-74ab-11ed-91b6-6bf2151ebd3b; Mon, 05 Dec 2022 15:48:07 +0100 (CET) Received: from MW4PR04CA0342.namprd04.prod.outlook.com (2603:10b6:303:8a::17) by DM4PR12MB5376.namprd12.prod.outlook.com (2603:10b6:5:39f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14; Mon, 5 Dec 2022 14:47:59 +0000 Received: from CO1NAM11FT091.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8a:cafe::b2) by MW4PR04CA0342.outlook.office365.com (2603:10b6:303:8a::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13 via Frontend Transport; Mon, 5 Dec 2022 14:47:59 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT091.mail.protection.outlook.com (10.13.175.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:47:58 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:27:37 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:27:32 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:27:31 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d36c13e7-74ab-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=C+yllKUEWM4T0u+H0T+7lz/QXJgi++CAmnrDFQUJxMOMgsrh/lo5avv2tJf0G6ZhQDF4GigXGXDjbEG6lK+PklxE3wcpAESoUsdrrrtfzYs3lP+BaOTj1NNkgScEqGHZVV1c19Nuhgv2JdSmxxcpY8LMq9Zfg+hL0jWmuSTk548fCyCe18p5AgQlZ6Tx/fcNho0x5jof4Bp/Bwqx0AT2fb/QGiNUi9PorIAc7SHVhJo+7nVqtn5Grn1TIlxgaWGBQJUc+xWfQXZZD8/AdtG0xC0Xjnb4do0PjjeMUFAWFo+a3RYfx2bFCKhbf607kMSJyu9q7wvt7xudw028aR3Ibg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4KHxmnWmNgQroEJqBI6LTdMkMgVnjuq8fRljQdPYe+4=; b=fRLzH3zv4xcE/2PNy+oAu45PfU29XK4VjErpG+7HFJI0Uy+OS3bZQAjlfy6jixbrpcUKmizCE5TkJrJlIDCSujAHdpWcYXUqRCFdZeksRSiTgRxaRTn/32UmDNEhazl2TntfX9ECO3mbRnFfX+kAotmGcLxRRthYlB3d/peHiXBEXzafJ5IYzmwPQ0n76uG5N9ReukH9jDWPDzo/Nt8jyaFR+XGwUekJ4WTtmhMCp8+cuv1d5S1rzLM9VVtdjDzWiePZT7W44QWYkybAJQNiCsV4k+uXR/UEOlAEUh2CbuH5qB4S2PF4WsOFtj5d+NSSnVxq1KUDeH3i9LEmm1p5+A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4KHxmnWmNgQroEJqBI6LTdMkMgVnjuq8fRljQdPYe+4=; b=SUwniUfv3X3k0NoPVsszxR2BKesK/mQvyFs635j4qRpD4eRepnYZC+F0cFUKIUtSm+gE3Le+BcZ5i7daOgYMa4WbR8BF+LTZzK4FzoYAN2JNFD/S8fJL4pLR0KE9isYlJFqvJuYXnwsOsj4GgHegOGtrSzASO2IydM0yLdNkbbg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 05/11] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host Date: Mon, 5 Dec 2022 13:26:31 +0000 Message-ID: <20221205132637.26775-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT091:EE_|DM4PR12MB5376:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b8cf1d7-4ed6-4bcb-ebea-08dad6cfb386 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: seRSQV338OlO0CSqDLx2X6SBpwp+vpEmZMYPqqGUgodKC95ZDP+eIxW1p7RymlYzmZd9XaHq8btGJHvOSk8kaO/ANMtSkUO8uD3ZdJa6klEQKrjt5AN89VcP5wY4qbnPqbsigDx0pZDbr2hjR88w2H2qNzgtO8Ny505NxjnxG3dIv2rky+wgIR1li2k7nUH75S68E9oTMkGoxhKYYnrljfK4S0ZMozhyF8NNeViCcgW0dje5sPWIMW3ur2mmLjGA9vXcqj+hH6tKEDkR8JptzyY3OBdnqDkzx/L76RYBdC6XiMG3Qs/sJpP+iq/fCCfHETmslHrgHaHfMkyRyymdkGat79dZ7us9vDETBaBAzTl8udchPIIIyq6eXe62E6MXkNbarJQxUYdjM+k2/TPsjGyA5zIXx4RaoAx1K9H+wEjTwM80dukLEnU8cIpR+LrhyRauD9Tg5PABlV1KSjwNtXzjvy8xIRjUILH6A2uVT4OhZAZ7WGHgcqk0tgVyIawjjgseOvYKoVd9AYDiw0qnxcPnzA1tQr0J9zNm+/H7e11GebdvqkhRqZEWg3tT72vzdTi2NK9QQHyR9nF12IsccM0wHV5m7LMHS0mFlyvB3lUHD7QFX1GHgyihu8ACDadUQnO4WHaz/96rZvqHeAsgZr5N1OZN73HRfdndMsEiqV9mwcbzP6cVv1PfbWvPOL8oFq2Qm5+FCpSMnXylHv25tlGwOCf/nIy1BWBuNmWSEyJ49Msd+tQLVmI21KdSGXC1jvFpJf6fMzN7RoT6PB2jnw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(39860400002)(396003)(376002)(451199015)(40470700004)(36840700001)(46966006)(36756003)(82740400003)(86362001)(81166007)(356005)(2906002)(41300700001)(40460700003)(8936002)(4326008)(5660300002)(36860700001)(83380400001)(103116003)(478600001)(70206006)(70586007)(966005)(2616005)(316002)(54906003)(6916009)(40480700001)(8676002)(82310400005)(336012)(47076005)(1076003)(426003)(186003)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:47:58.3322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b8cf1d7-4ed6-4bcb-ebea-08dad6cfb386 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5376 'unsigned long long' is defined as 64 bit across both AArch32 and AArch64. So, use 'ULL' for 64 bit word instead of UL which is 32 bits for AArch32. GICR_PENDBASER and GICR_PROPBASER both are 64 bit registers. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from - v1 - 1. Extract the bug fix for incorrect bit clearing (GICR_PENDBASER_PTZ) into a separate patch fix. https://patchwork.kernel.org/project/xen-devel/patch/20221027185555.46125-1-ayankuma@amd.com/ v2 - No changes. v3 - No changes. v4 - No changes. xen/arch/arm/include/asm/gic_v3_defs.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 728e28d5e5..48a1bc401e 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -134,15 +134,15 @@ #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_SHAREABILITY_SHIFT 10 #define GICR_PROPBASER_SHAREABILITY_MASK \ - (3UL << GICR_PROPBASER_SHAREABILITY_SHIFT) + (3ULL << GICR_PROPBASER_SHAREABILITY_SHIFT) #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT 7 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_RES0_MASK \ - (GENMASK(63, 59) | GENMASK(55, 52) | GENMASK(6, 5)) + (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) #define GICR_PENDBASER_SHAREABILITY_SHIFT 10 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT 7 @@ -152,11 +152,11 @@ #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ (7UL << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) -#define GICR_PENDBASER_PTZ BIT(62, UL) + (7ULL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) +#define GICR_PENDBASER_PTZ BIT(62, ULL) #define GICR_PENDBASER_RES0_MASK \ - (BIT(63, UL) | GENMASK(61, 59) | GENMASK(55, 52) | \ - GENMASK(15, 12) | GENMASK(6, 0)) + (BIT(63, ULL) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ + GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) #define DEFAULT_PMR_VALUE 0xff From patchwork Mon Dec 5 13:26:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59146C4321E for ; Mon, 5 Dec 2022 14:51:53 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453812.711414 (Exim 4.92) (envelope-from ) id 1p2Col-0003zU-8e; Mon, 05 Dec 2022 14:51:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453812.711414; Mon, 05 Dec 2022 14:51:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Col-0003zN-5Q; Mon, 05 Dec 2022 14:51:39 +0000 Received: by outflank-mailman (input) for mailman id 453812; Mon, 05 Dec 2022 14:51:38 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cok-0003zH-5C for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:51:38 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on20609.outbound.protection.outlook.com [2a01:111:f400:fe59::609]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 516628f3-74ac-11ed-8fd2-01056ac49cbb; Mon, 05 Dec 2022 15:51:36 +0100 (CET) Received: from BN9PR03CA0572.namprd03.prod.outlook.com (2603:10b6:408:10d::7) by CH0PR12MB5121.namprd12.prod.outlook.com (2603:10b6:610:bc::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13; Mon, 5 Dec 2022 14:51:33 +0000 Received: from BN8NAM11FT012.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10d:cafe::b5) by BN9PR03CA0572.outlook.office365.com (2603:10b6:408:10d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:51:33 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT012.mail.protection.outlook.com (10.13.177.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:51:32 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:27:57 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:27:57 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:27:56 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 516628f3-74ac-11ed-8fd2-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BJ5WtD8GNHCGS2h68S2Lkl4wfTP+NARAd5Rq132eg0El/avevL/sgy/eL//8TNsEgqJyjX4MKAhmQT7nTpcTmzRjWaHG9fDJenReruDVVCT4kYbrH1ZXWT7y/8e4zLRnYd79TLS4TZTcI8NmW0drIsFbUqr+pmMEtnVzHv1u0sP0HhG6LEt/P5TIYCfZ1J0XElxTHXbS7I/Byzw935xUKLE1QF8MARBa6PVTbPqMX2paXVXjra0i1AdFq3Ro7MMPPPvV2grBrV3GFXnfKBcXLXZ39LGyD7I7geQCwKtmev4KHSwuVzV55Mu/1aSe0MLX0r3hAqyHXwB+3Js6E+PLqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=++4q5HIw11G096d2CZkM4llMeSXkXZxp6mjZ0joYBGE=; b=aXrxyz2hdKqZa1VW2kDTYzLJk9id/GaPXuVmVYGTgnQmgZbj7TTlHT09F0Jv6HsswaQTwLh9vXhGxv/AnwPoAdPawyfLZ3aU0xkTiBxIbGExoRjUpI5Yv1E0pGgWK1CB5X5f8y+Upq1ituAz5NXcmiPU5noOrll4z1T6OHW0kN5wFeFRuz+B004KGDDxFj4BrAEfY3wb5W4f5q4HRKHnqZDg4KZK8kQI9g9Qvtn3hB148rQXCfqyiF/XRM5coG/FnV34k+NCWEzTQ3LbJsJSzoUqZryTm65uRu/KOMw4u8Dh8BeCWSz+NJee+P8YzrHOcc1urwg3LNwme5EcUrVGTw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=++4q5HIw11G096d2CZkM4llMeSXkXZxp6mjZ0joYBGE=; b=PorcKCf8iH11NljbtKjmj55o9FRy756PLib/lX/8osX/seX7M2O/hN6G0hZKdzMuYOq7Rn5gCAjznGzRjE18GQr9t+MGt3zzSyVMvKMsflGdPqaQpBtnoM4IsQV0iVvAXfSCD9FeWXhya0f0i6zfIh9blgMa/+XvkHn46eWI2HY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 06/11] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Date: Mon, 5 Dec 2022 13:26:32 +0000 Message-ID: <20221205132637.26775-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT012:EE_|CH0PR12MB5121:EE_ X-MS-Office365-Filtering-Correlation-Id: eceb8df2-40e2-4297-68ea-08dad6d03338 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eWEViYG6HPTvfVP2mrmBcXJGUsYk8Fre5w2/nqWjY87eGqlybA19XufjNLZ5NhcFdzq9Abcasv76WcBdXmnHey+Q9n5IIyExNF75o/BDBi+8tPF27FqBC6f3/x26q9jDMdYA7elQim+NqZtha8WmScKgB5siKB9Ak9/7tE2ZUCSG6L+oXsttf/3p1oMnmAxQjgqdHDAxTWHcFRDszpNdgCVs2Ttn0AouTj71dlO479zPZZ0a1jcOvY3OPAw568VrYnJBf/JXYS5PxqH+sRcYoxhbeA7HnnmJQdv1MRN3QDOZzzJuPbYrwLvUkWgkeBBTT6QBasc2qSgQeYM7sx4KVy9UhYJKMKxzPhIVGEvJfJPxUpt8MIMTfah4JOtGUck8GpRoQKXPWg6rRU4qkpemF6xYZxbmlaGPP6QfIso/Fp/a1O6BVgwJTjzr0wiRUdzualBzH9gAWQyAikorTL31QofkVTkVmWjhvA4q9ouBdiK1Pkft9NBI9f4Pd9HEMMpKeKIPYfNVwwSgTw+cNPssf/WfQ1Q3kU+VoeXZpLvL4M2fjDn+uSRVD0P55Aw54HjKFC1WPAqDjw8BjNFLyKGbkt1DYBRBBg7sz7jGaKsjycp+ufWF6+NIc03x9JYQrqWgM9sns927GFENdQnpQehxuBXcT/HFtFEJBkfmju5kI7on0MTroN4lJFGJnWP52dsZ+vBhYIxL3/YXl1MqkfHdoV+M/qvRuZCSP7+g33rzFZQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(39860400002)(396003)(376002)(451199015)(40470700004)(46966006)(36840700001)(82310400005)(36756003)(40480700001)(47076005)(316002)(426003)(83380400001)(6916009)(54906003)(1076003)(6666004)(26005)(186003)(103116003)(2906002)(86362001)(336012)(70206006)(70586007)(36860700001)(4326008)(8676002)(81166007)(478600001)(356005)(82740400003)(40460700003)(2616005)(8936002)(41300700001)(5660300002)(4744005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:51:32.6754 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eceb8df2-40e2-4297-68ea-08dad6d03338 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5121 Refer Arm IHI 0069H ID020922, 12.5.23, ICC_SGI1R is a 64 bit register on AArch32 systems. Thus, the function needs to change to reflect this. The reason being 'register_t' is defined as 'u32' on AArch32. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Updated the commit message. v2 - 1. No changes. v3 - 1. No changes. v4 - 1. No changes. xen/arch/arm/vgic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e0b636b95f..47575d4944 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1483,7 +1483,7 @@ write_reserved: return 1; } -static bool vgic_v3_to_sgi(struct vcpu *v, register_t sgir) +static bool vgic_v3_to_sgi(struct vcpu *v, uint64_t sgir) { int virq; int irqmode; From patchwork Mon Dec 5 13:26:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B83CC4321E for ; Mon, 5 Dec 2022 14:55:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453838.711457 (Exim 4.92) (envelope-from ) id 1p2CsA-0006IJ-JA; Mon, 05 Dec 2022 14:55:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453838.711457; Mon, 05 Dec 2022 14:55:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2CsA-0006IC-GH; Mon, 05 Dec 2022 14:55:10 +0000 Received: by outflank-mailman (input) for mailman id 453838; Mon, 05 Dec 2022 14:55:09 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cs9-0006I4-Dv for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:55:09 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on20612.outbound.protection.outlook.com [2a01:111:f400:7e8a::612]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ce740ee0-74ac-11ed-8fd2-01056ac49cbb; Mon, 05 Dec 2022 15:55:07 +0100 (CET) Received: from BN9PR03CA0970.namprd03.prod.outlook.com (2603:10b6:408:109::15) by PH8PR12MB6962.namprd12.prod.outlook.com (2603:10b6:510:1bd::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.11; Mon, 5 Dec 2022 14:55:03 +0000 Received: from BN8NAM11FT058.eop-nam11.prod.protection.outlook.com (2603:10b6:408:109:cafe::3e) by BN9PR03CA0970.outlook.office365.com (2603:10b6:408:109::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:55:03 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT058.mail.protection.outlook.com (10.13.177.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:55:03 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:28:13 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 05:28:12 -0800 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:28:11 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ce740ee0-74ac-11ed-8fd2-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KgGwLNd5/+YSv5n0K32vNNJ0Sgp4XXj367FieZbFQF9QAYIciIE6PBh6QDLBHUoh3dbj7YFvQYUyLcXNbTsPmgn4XHLSi3MA2Nm+eBPmugigAg1n9iZ159veL5fB95P9Xu/2SnAov5ehKBrIQ9hHrjZoaXq/49fRBct8XcmNrI1ctu67bSFPWLardnlcao+kLG0ZJo3+NGIC4E9ajqgdI8sEj5//o/IKR0WGhYPHdObKb/mNc+sO3zr2X23btG6dj4cxS16G6Ad6Y/OLC8vLOeucy/dIlLXxsBAZOh2JEg8x9bmWlgo+KkSVlyAUMiUXUTnWLEH8eY/jrZ0TcyyYpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pitUdhtGNwCL78oKiSmhss6QoDqvkOn2pEZ1iZlgPEI=; b=Q1Lgog1PcEixEH+vX2q5M7hm50jkXWFVMLqz4b5PVRu+gSd7cb5wvW4zwCK9c5Cr8BHHz89V3k3bl6UX7vOyOrzQ3JWXWo2s6ZgAfGPhVDTv+rAQ3NdjmafGpDztSdeA4dJRZYxgNMfzezSwEzqJXWaq7gtrO6T2mvLDYQpiNjLCvo8y5JaEU7WwA4vLEiyO1FiE/wDymjDEt6G3eD7cdTla4cBQnTXgq0Qlg2KY2FWcW9t3Yf6IXyO0lWxVlTCFmEXJRYKVFzezzxXePKOeJXvkwbETwPfBDMlOFzDPy+/jufVOEEfdidzkL7S4K9yP9eMPc/DDZZ9JQJW9qesnKA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pitUdhtGNwCL78oKiSmhss6QoDqvkOn2pEZ1iZlgPEI=; b=oZeof0KwOH9GZCbU0hTebZOsfU9KVzIdkJi+1wVnC1gKGiUqremkZfxJk/l/U1uepuRS2PUELOWIPaDosi0zR2MGUYK49eaxkktVP1htXwj8N0WIYmtuZCTbeUDeChPxSVFiYCpqkEikarN/Fz0OzVC6URkYRBCxTqBrZc0gUp8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 07/11] xen/Arm: GICv3: Define ICH_LR_EL2 on AArch32 Date: Mon, 5 Dec 2022 13:26:33 +0000 Message-ID: <20221205132637.26775-8-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT058:EE_|PH8PR12MB6962:EE_ X-MS-Office365-Filtering-Correlation-Id: 276fce4d-0e2b-426b-f189-08dad6d0b0fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zgcFa0pJxBzws6aenglcOYyaZOa2t7GjdWYTh7+KpBRRUdRz6IvFcABSsA8xEJ7weF9CGSpYYoYyaqH+XU/Ywpr9TKH46jrxO4v9zIEcVFIghsRM/zEkmY/SYbvBRPXZdywDpMdOb8VadylygpAz0KS7pBMdaQTshqInhWBqrW+rF8nkJT6T34UQKWsXfk1AGq5Ps3P7Gl4om/nlg2PfblrNokBDRwGXgZ7gaYVSg9BGl1PXCXKwOeBF1/9Sn0lw15P7BSoGLxSJUoS/lL5fvpODQadaLEK2oPGjD7pw/okWIfN1MI883ERZ2GRvhew+5I2vDlyLWoNAJ4O0SlkZ8HBs7O46HyC5y2Mq/+CL2wL6AQgUqG3ls/j+xD8CmaAQgdhbo1qESIbaH6rNy5FAUyp91rw3jSMhoej2AftcQBxXG3CKFD9eFtVTYr/skn7DTr0YI9SyYV2r6oJDbYukpaik70T9HAJ9B5UHqxoLN+NMzWezkcfaJ16/hrBFjnn6fUzAeFfUvAdYuwqRwTaMbHeHboUs4hW+mP1ibROCj/juqRPaaAh/Pg6/52asJGs1rUBU9d8n/jToVNKMu1B5hapkaFPuhnWsw1ZjmhSxU9zkrp/Vo60h/qnvoRj73tZjWdKoXH6wapfPDE9x8MuXUNsO4sPmZWplt1wke3AAchaVnWWU6bn9w8uFlMVeG/POqb5BORV15d1xtyDNmzFoyr32s1mhGn4BZ/4s3x9L2rE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(36840700001)(40470700004)(46966006)(82310400005)(36756003)(40480700001)(316002)(426003)(83380400001)(186003)(336012)(6916009)(1076003)(26005)(54906003)(6666004)(47076005)(86362001)(2906002)(103116003)(8676002)(70586007)(4326008)(36860700001)(70206006)(81166007)(82740400003)(40460700003)(478600001)(2616005)(356005)(30864003)(5660300002)(8936002)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:55:03.6655 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 276fce4d-0e2b-426b-f189-08dad6d0b0fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6962 Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_LR[31:0]. AArch64 System register ICH_LR_EL2 bits [63:32] are architecturally mapped to AArch32 System register ICH_LRC[31:0]. Defined ICH_LR<0...15>_EL2 and ICH_LRC<0...15>_EL2 for AArch32. For AArch32, the link register is stored as :- (((uint64_t) ICH_LRC<0...15>_EL2) << 32) | ICH_LR<0...15>_EL2 Also, ICR_LR macros need to be modified as ULL is 64 bits for AArch32 and AArch64. Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall --- Changes from :- v1 - 1. Moved the coproc register definitions to asm/cpregs.h. 2. Use GENMASK(31, 0) to represent 0xFFFFFFFF 3. Use READ_CP32()/WRITE_CP32() instead of READ_SYSREG()/WRITE_SYSREG(). 4. Multi-line macro definitions should be enclosed within ({ }). v2 - 1. Use WRITE_SYSREG_LR(V, R) to make it consistent with before. 2. Defined the register alias. 3. Style issues. v3 - 1. Addressed style issues. v4 - 1. Replaces ___CP32(foo) with foo. 2. Removed the definition of ___CP32(). xen/arch/arm/gic-v3.c | 132 +++++++++++------------ xen/arch/arm/include/asm/arm32/sysregs.h | 19 ++++ xen/arch/arm/include/asm/arm64/sysregs.h | 5 + xen/arch/arm/include/asm/cpregs.h | 74 +++++++++++++ xen/arch/arm/include/asm/gic_v3_defs.h | 8 +- 5 files changed, 168 insertions(+), 70 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 64a76307dd..6457e7033c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -73,37 +73,37 @@ static inline void gicv3_save_lrs(struct vcpu *v) switch ( gicv3_info.nr_lrs ) { case 16: - v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2); + v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); case 15: - v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2); + v->arch.gic.v3.lr[14] = READ_SYSREG_LR(14); case 14: - v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2); + v->arch.gic.v3.lr[13] = READ_SYSREG_LR(13); case 13: - v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2); + v->arch.gic.v3.lr[12] = READ_SYSREG_LR(12); case 12: - v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2); + v->arch.gic.v3.lr[11] = READ_SYSREG_LR(11); case 11: - v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2); + v->arch.gic.v3.lr[10] = READ_SYSREG_LR(10); case 10: - v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2); + v->arch.gic.v3.lr[9] = READ_SYSREG_LR(9); case 9: - v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2); + v->arch.gic.v3.lr[8] = READ_SYSREG_LR(8); case 8: - v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2); + v->arch.gic.v3.lr[7] = READ_SYSREG_LR(7); case 7: - v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2); + v->arch.gic.v3.lr[6] = READ_SYSREG_LR(6); case 6: - v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2); + v->arch.gic.v3.lr[5] = READ_SYSREG_LR(5); case 5: - v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2); + v->arch.gic.v3.lr[4] = READ_SYSREG_LR(4); case 4: - v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2); + v->arch.gic.v3.lr[3] = READ_SYSREG_LR(3); case 3: - v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2); + v->arch.gic.v3.lr[2] = READ_SYSREG_LR(2); case 2: - v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2); + v->arch.gic.v3.lr[1] = READ_SYSREG_LR(1); case 1: - v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2); + v->arch.gic.v3.lr[0] = READ_SYSREG_LR(0); break; default: BUG(); @@ -120,37 +120,37 @@ static inline void gicv3_restore_lrs(const struct vcpu *v) switch ( gicv3_info.nr_lrs ) { case 16: - WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[15], 15); case 15: - WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[14], 14); case 14: - WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[13], 13); case 13: - WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[12], 12); case 12: - WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[11], 11); case 11: - WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[10], 10); case 10: - WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[9], 9); case 9: - WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[8], 8); case 8: - WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[7], 7); case 7: - WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[6], 6); case 6: - WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[5], 5); case 5: - WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[4], 4); case 4: - WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[3], 3); case 3: - WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[2], 2); case 2: - WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[1], 1); case 1: - WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2); + WRITE_SYSREG_LR(v->arch.gic.v3.lr[0], 0); break; default: BUG(); @@ -161,22 +161,22 @@ static uint64_t gicv3_ich_read_lr(int lr) { switch ( lr ) { - case 0: return READ_SYSREG(ICH_LR0_EL2); - case 1: return READ_SYSREG(ICH_LR1_EL2); - case 2: return READ_SYSREG(ICH_LR2_EL2); - case 3: return READ_SYSREG(ICH_LR3_EL2); - case 4: return READ_SYSREG(ICH_LR4_EL2); - case 5: return READ_SYSREG(ICH_LR5_EL2); - case 6: return READ_SYSREG(ICH_LR6_EL2); - case 7: return READ_SYSREG(ICH_LR7_EL2); - case 8: return READ_SYSREG(ICH_LR8_EL2); - case 9: return READ_SYSREG(ICH_LR9_EL2); - case 10: return READ_SYSREG(ICH_LR10_EL2); - case 11: return READ_SYSREG(ICH_LR11_EL2); - case 12: return READ_SYSREG(ICH_LR12_EL2); - case 13: return READ_SYSREG(ICH_LR13_EL2); - case 14: return READ_SYSREG(ICH_LR14_EL2); - case 15: return READ_SYSREG(ICH_LR15_EL2); + case 0: return READ_SYSREG_LR(0); + case 1: return READ_SYSREG_LR(1); + case 2: return READ_SYSREG_LR(2); + case 3: return READ_SYSREG_LR(3); + case 4: return READ_SYSREG_LR(4); + case 5: return READ_SYSREG_LR(5); + case 6: return READ_SYSREG_LR(6); + case 7: return READ_SYSREG_LR(7); + case 8: return READ_SYSREG_LR(8); + case 9: return READ_SYSREG_LR(9); + case 10: return READ_SYSREG_LR(10); + case 11: return READ_SYSREG_LR(11); + case 12: return READ_SYSREG_LR(12); + case 13: return READ_SYSREG_LR(13); + case 14: return READ_SYSREG_LR(14); + case 15: return READ_SYSREG_LR(15); default: BUG(); } @@ -187,52 +187,52 @@ static void gicv3_ich_write_lr(int lr, uint64_t val) switch ( lr ) { case 0: - WRITE_SYSREG(val, ICH_LR0_EL2); + WRITE_SYSREG_LR(val, 0); break; case 1: - WRITE_SYSREG(val, ICH_LR1_EL2); + WRITE_SYSREG_LR(val, 1); break; case 2: - WRITE_SYSREG(val, ICH_LR2_EL2); + WRITE_SYSREG_LR(val, 2); break; case 3: - WRITE_SYSREG(val, ICH_LR3_EL2); + WRITE_SYSREG_LR(val, 3); break; case 4: - WRITE_SYSREG(val, ICH_LR4_EL2); + WRITE_SYSREG_LR(val, 4); break; case 5: - WRITE_SYSREG(val, ICH_LR5_EL2); + WRITE_SYSREG_LR(val, 5); break; case 6: - WRITE_SYSREG(val, ICH_LR6_EL2); + WRITE_SYSREG_LR(val, 6); break; case 7: - WRITE_SYSREG(val, ICH_LR7_EL2); + WRITE_SYSREG_LR(val, 7); break; case 8: - WRITE_SYSREG(val, ICH_LR8_EL2); + WRITE_SYSREG_LR(val, 8); break; case 9: - WRITE_SYSREG(val, ICH_LR9_EL2); + WRITE_SYSREG_LR(val, 9); break; case 10: - WRITE_SYSREG(val, ICH_LR10_EL2); + WRITE_SYSREG_LR(val, 10); break; case 11: - WRITE_SYSREG(val, ICH_LR11_EL2); + WRITE_SYSREG_LR(val, 11); break; case 12: - WRITE_SYSREG(val, ICH_LR12_EL2); + WRITE_SYSREG_LR(val, 12); break; case 13: - WRITE_SYSREG(val, ICH_LR13_EL2); + WRITE_SYSREG_LR(val, 13); break; case 14: - WRITE_SYSREG(val, ICH_LR14_EL2); + WRITE_SYSREG_LR(val, 14); break; case 15: - WRITE_SYSREG(val, ICH_LR15_EL2); + WRITE_SYSREG_LR(val, 15); break; default: return; @@ -417,12 +417,12 @@ static void gicv3_dump_state(const struct vcpu *v) if ( v == current ) { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" HW_LR[%d]=%lx\n", i, gicv3_ich_read_lr(i)); + printk(" HW_LR[%d]=%" PRIx64 "\n", i, gicv3_ich_read_lr(i)); } else { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]); + printk(" VCPU_LR[%d]=%" PRIx64 "\n", i, v->arch.gic.v3.lr[i]); } } diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 6841d5de43..22871999af 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -62,6 +62,25 @@ #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) +/* Wrappers for accessing interrupt controller list registers. */ +#define ICH_LR_REG(index) ICH_LR ## index ## _EL2 +#define ICH_LRC_REG(index) ICH_LRC ## index ## _EL2 + +#define READ_SYSREG_LR(index) ({ \ + uint64_t _val; \ + uint32_t _lrc = READ_CP32(ICH_LRC_REG(index)); \ + uint32_t _lr = READ_CP32(ICH_LR_REG(index)); \ + \ + _val = ((uint64_t) _lrc << 32) | _lr; \ + _val; \ +}) + +#define WRITE_SYSREG_LR(v, index) ({ \ + uint64_t _val = (v); \ + WRITE_CP32(_val & GENMASK(31, 0), ICH_LR_REG(index)); \ + WRITE_CP32(_val >> 32, ICH_LRC_REG(index)); \ +}) + /* MVFR2 is not defined on ARMv7 */ #define MVFR2_MAYBE_UNDEFINED diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index 54670084c3..4638999514 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -472,6 +472,11 @@ #define READ_SYSREG(name) READ_SYSREG64(name) #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) +/* Wrappers for accessing interrupt controller list registers. */ +#define ICH_LR_REG(index) ICH_LR ## index ## _EL2 +#define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) +#define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 6daf2b1a30..7550fb25f5 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -259,6 +259,48 @@ #define VBAR p15,0,c12,c0,0 /* Vector Base Address Register */ #define HVBAR p15,4,c12,c0,0 /* Hyp. Vector Base Address Register */ +/* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */ +#define __LR0(x) p15, 4, c12, c12, x +#define __LR8(x) p15, 4, c12, c13, x + +#define ICH_LR0 __LR0(0) +#define ICH_LR1 __LR0(1) +#define ICH_LR2 __LR0(2) +#define ICH_LR3 __LR0(3) +#define ICH_LR4 __LR0(4) +#define ICH_LR5 __LR0(5) +#define ICH_LR6 __LR0(6) +#define ICH_LR7 __LR0(7) +#define ICH_LR8 __LR8(0) +#define ICH_LR9 __LR8(1) +#define ICH_LR10 __LR8(2) +#define ICH_LR11 __LR8(3) +#define ICH_LR12 __LR8(4) +#define ICH_LR13 __LR8(5) +#define ICH_LR14 __LR8(6) +#define ICH_LR15 __LR8(7) + +/* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */ +#define __LRC0(x) p15, 4, c12, c14, x +#define __LRC8(x) p15, 4, c12, c15, x + +#define ICH_LRC0 __LRC0(0) +#define ICH_LRC1 __LRC0(1) +#define ICH_LRC2 __LRC0(2) +#define ICH_LRC3 __LRC0(3) +#define ICH_LRC4 __LRC0(4) +#define ICH_LRC5 __LRC0(5) +#define ICH_LRC6 __LRC0(6) +#define ICH_LRC7 __LRC0(7) +#define ICH_LRC8 __LRC8(0) +#define ICH_LRC9 __LRC8(1) +#define ICH_LRC10 __LRC8(2) +#define ICH_LRC11 __LRC8(3) +#define ICH_LRC12 __LRC8(4) +#define ICH_LRC13 __LRC8(5) +#define ICH_LRC14 __LRC8(6) +#define ICH_LRC15 __LRC8(7) + /* CP15 CR13: */ #define FCSEIDR p15,0,c13,c0,0 /* FCSE Process ID Register */ #define CONTEXTIDR p15,0,c13,c0,1 /* Context ID Register */ @@ -317,6 +359,38 @@ #define HCR_EL2 HCR #define HPFAR_EL2 HPFAR #define HSTR_EL2 HSTR +#define ICH_LR0_EL2 ICH_LR0 +#define ICH_LR1_EL2 ICH_LR1 +#define ICH_LR2_EL2 ICH_LR2 +#define ICH_LR3_EL2 ICH_LR3 +#define ICH_LR4_EL2 ICH_LR4 +#define ICH_LR5_EL2 ICH_LR5 +#define ICH_LR6_EL2 ICH_LR6 +#define ICH_LR7_EL2 ICH_LR7 +#define ICH_LR8_EL2 ICH_LR8 +#define ICH_LR9_EL2 ICH_LR9 +#define ICH_LR10_EL2 ICH_LR10 +#define ICH_LR11_EL2 ICH_LR11 +#define ICH_LR12_EL2 ICH_LR12 +#define ICH_LR13_EL2 ICH_LR13 +#define ICH_LR14_EL2 ICH_LR14 +#define ICH_LR15_EL2 ICH_LR15 +#define ICH_LRC0_EL2 ICH_LRC0 +#define ICH_LRC1_EL2 ICH_LRC1 +#define ICH_LRC2_EL2 ICH_LRC2 +#define ICH_LRC3_EL2 ICH_LRC3 +#define ICH_LRC4_EL2 ICH_LRC4 +#define ICH_LRC5_EL2 ICH_LRC5 +#define ICH_LRC6_EL2 ICH_LRC6 +#define ICH_LRC7_EL2 ICH_LRC7 +#define ICH_LRC8_EL2 ICH_LRC8 +#define ICH_LRC9_EL2 ICH_LRC9 +#define ICH_LRC10_EL2 ICH_LRC10 +#define ICH_LRC11_EL2 ICH_LRC11 +#define ICH_LRC12_EL2 ICH_LRC12 +#define ICH_LRC13_EL2 ICH_LRC13 +#define ICH_LRC14_EL2 ICH_LRC14 +#define ICH_LRC15_EL2 ICH_LRC15 #define ID_AFR0_EL1 ID_AFR0 #define ID_DFR0_EL1 ID_DFR0 #define ID_DFR1_EL1 ID_DFR1 diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 48a1bc401e..227533868f 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -185,9 +185,9 @@ #define ICH_LR_HW_SHIFT 61 #define ICH_LR_GRP_MASK 0x1 #define ICH_LR_GRP_SHIFT 60 -#define ICH_LR_MAINTENANCE_IRQ (1UL<<41) -#define ICH_LR_GRP1 (1UL<<60) -#define ICH_LR_HW (1UL<<61) +#define ICH_LR_MAINTENANCE_IRQ (1ULL << 41) +#define ICH_LR_GRP1 (1ULL << 60) +#define ICH_LR_HW (1ULL << 61) #define ICH_VTR_NRLRGS 0x3f #define ICH_VTR_PRIBITS_MASK 0x7 @@ -195,7 +195,7 @@ #define ICH_SGI_IRQMODE_SHIFT 40 #define ICH_SGI_IRQMODE_MASK 0x1 -#define ICH_SGI_TARGET_OTHERS 1UL +#define ICH_SGI_TARGET_OTHERS 1ULL #define ICH_SGI_TARGET_LIST 0 #define ICH_SGI_IRQ_SHIFT 24 #define ICH_SGI_IRQ_MASK 0xf From patchwork Mon Dec 5 13:26:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FCE9C4321E for ; Mon, 5 Dec 2022 13:30:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453628.711223 (Exim 4.92) (envelope-from ) id 1p2BYF-0006lD-0b; Mon, 05 Dec 2022 13:30:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453628.711223; Mon, 05 Dec 2022 13:30:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BYE-0006l1-SI; Mon, 05 Dec 2022 13:30:30 +0000 Received: by outflank-mailman (input) for mailman id 453628; Mon, 05 Dec 2022 13:30:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BYD-0006k4-3F for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 13:30:29 +0000 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on20612.outbound.protection.outlook.com [2a01:111:f400:7ea9::612]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id faa3389a-74a0-11ed-91b6-6bf2151ebd3b; Mon, 05 Dec 2022 14:30:27 +0100 (CET) Received: from BN9PR03CA0173.namprd03.prod.outlook.com (2603:10b6:408:f4::28) by SA0PR12MB4477.namprd12.prod.outlook.com (2603:10b6:806:92::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13; Mon, 5 Dec 2022 13:30:24 +0000 Received: from BN8NAM11FT026.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f4:cafe::12) by BN9PR03CA0173.outlook.office365.com (2603:10b6:408:f4::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 13:30:24 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT026.mail.protection.outlook.com (10.13.177.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 13:30:23 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:29:24 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:29:23 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: faa3389a-74a0-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TSe+x81C9rSBtuhuVQyIOh+NV6kLlPnQam2vy95kD9hSkUsfP59k5QKdP+pGi3Ybnn8wBbRV532T9KnhogugqsTllFY7i76BvGicBgnzqEzHvYAaqEgOBMutcO22s32MpJBYK7qKcCusUC29qvqqb5r8WiZkPeYCmfK5c+08mNowROQAy3hPUE+XeGhMzwZ4ZCR3BBJxM4REt3Sbrmen51HnjPhqp4GimPPMTNTDFaU/UnHZXpPoImXBSa4LfyOroyRg82LJZYH1iSLr3NpANCXw+6H4gK9YUe3oQlQim24g4vha8sWSgfLLRI9HSIn3zWHMTaLNlL/liZ+T4YIqmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UEjzoMMb5D+I2LUETb4z5YcCm8RBHeC1gTFrxO6duws=; b=a4+F1XnJCd6UVTMo9xJ1G1QGVkF1+3uditldi4fgF+BvRg7eidMWtsoirKJSPIzw45zYJKnUEExHTeKPO6MPxj9aV5rHKpDx+msTVy0evZPrBMolZviQdWOOIOMRmlLv2b3tIwn5LbCvc/2ca/q/UcsHJ2XWQoaKjidghGu8YwoD4JMTYGPGIBjwwAHv3N4Znr1WnVlbRXfzM0gI3Uwwk9ZCI5s/WMinPZiH9EQgVLqz/QMWfibHgL95XMNGmLXQfudR9jVaWddWwca3eK6B3nNWtPuaahadL1AojUDk7sZ8wVpbCOukBmbFswbJpI6vBgylN9+rNvIZLwVY8g67wA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UEjzoMMb5D+I2LUETb4z5YcCm8RBHeC1gTFrxO6duws=; b=fX0imxLanu2XAUY33N6LzykPGu8QBmNadiFy79hytLFuy7ZDE2VzNqbVWQ/eQJFIWSdqUvlBl0y4GAopzw9CL9OWbnEcBPOHYAyQtVrRilcu9fSDMa3j1cGMoHP5FvujLTxmA/QZVWVp+8s4evYq9C0OmssWIEbWe06VB+3YQnI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 08/11] xen/Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32 Date: Mon, 5 Dec 2022 13:26:34 +0000 Message-ID: <20221205132637.26775-9-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT026:EE_|SA0PR12MB4477:EE_ X-MS-Office365-Filtering-Correlation-Id: f9dd7ec8-8dd9-4bdd-55c7-08dad6c4dcfa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k4sNX5rjF3eK9txYeh9OpI2S4c5kVnXyapSrr+isKWolIDOH/pfDvpp0bKHRQhM0eNvlVxa6gFoiWRj4oJ+WqF/30jjgfPxkKOaA8sCshiYBeerNJdXZ3el/EKC1Ox7XiP+uR5qMX13On2DnishrdcFMMOXoOHSOvkxjpwQSheW4GzfiruCWIT7IaCClUvyVh4S2vN/S/5JAZG/ANYXW33rb6NIL9KSP059mXvIEl/7J/wZbmWvfwB3zLh2XrXcjk/079C8TtP4FryxW2SN6OeUC2LCyx/d++0Ji5i6sVvLKIqfXIp918veWMPf5mjR8h5Cuea7d4t/BrIGF4v1YFSTYa8EfqHog2ZyhMB899extA8BheWdxovDE76YYrJapaY0y7pQ89jhxFheM6PTBYcBEaUyHIsI/IUubCgsKxIEMRhRp8AWcKECYpaHut2U7pMcZ/GmSCb89J1aDgrQg4aQfktO+05bkVvN4Khr+uKNq7CHvtg4JnnHIaHWpVh3ScpwKRYZha5DxArB01YoXMwjgvqb3ll8BZb5NHEXPkkvWQFCeJtdmj+DP7PBKkUrjiVWHfPaznFmbIjY+/bgbG1ns0JStWINXV1s+ZCWwqCm3Ehzz4StX2UMG6Y4yI70z52kxKeaBEKMdqyyMlXGhJJBGqIXQhme1z6yPc5d+lj022GEUqIdE45ewP82o6Yn8LVsN8QeiZ9B4AAkm1JcAqBiLQZ5Fim6LZNTwin43uyA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199015)(36840700001)(40470700004)(46966006)(2906002)(82310400005)(83380400001)(2616005)(47076005)(316002)(8676002)(4326008)(103116003)(40480700001)(70206006)(8936002)(70586007)(36756003)(86362001)(40460700003)(426003)(5660300002)(41300700001)(54906003)(186003)(1076003)(336012)(6916009)(478600001)(36860700001)(82740400003)(6666004)(26005)(356005)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 13:30:23.5205 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9dd7ec8-8dd9-4bdd-55c7-08dad6c4dcfa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4477 Adapt save_aprn_regs()/restore_aprn_regs() for AArch32. For which we have defined the following registers:- 1. Interrupt Controller Hyp Active Priorities Group0 Registers 0-3 2. Interrupt Controller Hyp Active Priorities Group1 Registers 0-3 Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall --- Changes from :- v1 - 1. Moved coproc register definition to asm/cpregs.h. v2 - 1. Defined register alias. 2. Style issues. 3. Dropped R-b and Ack. v3 - 1. Style issues. v4 - 1. Replaced ___CP32(foo) with foo. xen/arch/arm/include/asm/cpregs.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 7550fb25f5..4476c9f11b 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -259,6 +259,26 @@ #define VBAR p15,0,c12,c0,0 /* Vector Base Address Register */ #define HVBAR p15,4,c12,c0,0 /* Hyp. Vector Base Address Register */ +/* + * CP15 CR12: Interrupt Controller Hyp Active Priorities Group 0 Registers, + * n = 0 - 3 + */ +#define __AP0Rx(x) p15, 4, c12, c8, x +#define ICH_AP0R0 __AP0Rx(0) +#define ICH_AP0R1 __AP0Rx(1) +#define ICH_AP0R2 __AP0Rx(2) +#define ICH_AP0R3 __AP0Rx(3) + +/* + * CP15 CR12: Interrupt Controller Hyp Active Priorities Group 1 Registers, + * n = 0 - 3 + */ +#define __AP1Rx(x) p15, 4, c12, c9, x +#define ICH_AP1R0 __AP1Rx(0) +#define ICH_AP1R1 __AP1Rx(1) +#define ICH_AP1R2 __AP1Rx(2) +#define ICH_AP1R3 __AP1Rx(3) + /* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */ #define __LR0(x) p15, 4, c12, c12, x #define __LR8(x) p15, 4, c12, c13, x @@ -359,6 +379,14 @@ #define HCR_EL2 HCR #define HPFAR_EL2 HPFAR #define HSTR_EL2 HSTR +#define ICH_AP0R0_EL2 ICH_AP0R0 +#define ICH_AP0R1_EL2 ICH_AP0R1 +#define ICH_AP0R2_EL2 ICH_AP0R2 +#define ICH_AP0R3_EL2 ICH_AP0R3 +#define ICH_AP1R0_EL2 ICH_AP1R0 +#define ICH_AP1R1_EL2 ICH_AP1R1 +#define ICH_AP1R2_EL2 ICH_AP1R2 +#define ICH_AP1R3_EL2 ICH_AP1R3 #define ICH_LR0_EL2 ICH_LR0 #define ICH_LR1_EL2 ICH_LR1 #define ICH_LR2_EL2 ICH_LR2 From patchwork Mon Dec 5 13:26:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7A42C4708C for ; Mon, 5 Dec 2022 13:30:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453629.711234 (Exim 4.92) (envelope-from ) id 1p2BYG-00071k-8h; Mon, 05 Dec 2022 13:30:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453629.711234; Mon, 05 Dec 2022 13:30:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BYG-00071b-4B; Mon, 05 Dec 2022 13:30:32 +0000 Received: by outflank-mailman (input) for mailman id 453629; Mon, 05 Dec 2022 13:30:30 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2BYE-0006k4-MB for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 13:30:30 +0000 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on20614.outbound.protection.outlook.com [2a01:111:f400:fe5b::614]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fc5c43d4-74a0-11ed-91b6-6bf2151ebd3b; Mon, 05 Dec 2022 14:30:29 +0100 (CET) Received: from BN9PR03CA0157.namprd03.prod.outlook.com (2603:10b6:408:f4::12) by SA3PR12MB7949.namprd12.prod.outlook.com (2603:10b6:806:31a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13; Mon, 5 Dec 2022 13:30:26 +0000 Received: from BN8NAM11FT026.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f4:cafe::4d) by BN9PR03CA0157.outlook.office365.com (2603:10b6:408:f4::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 13:30:26 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT026.mail.protection.outlook.com (10.13.177.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 13:30:25 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:29:37 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:29:35 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fc5c43d4-74a0-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=G6Mr0o0ZW6lOCuDIcfZYCDQhVMpRJx1t/fqOIsQJTynpzP4iXiMCXAXiNWk9SUGE+apIspDMknkVtBNLwCTfJYx+z9MKwYagVZVinJQVg3CbseEnNvAuOTgWbOPS5H64MxpYpx1kHotU3hq6mjKV5+LGY7Brl6L5fxYzyR/H7uOm53XgQ/fiuToZJXMHct22tk0CbBA/DAanQv1HN5PgVzM5yRBjA7mXGJGkipfdVx98ySZuRt9MH+jXhbPGgfuXhtCz317fESqoxl1kANroyV4E/Td/WtXefCcI9rwAdTaxuvDvglnZ3LMolQPhb9aojA7N5aYqkKNDHnLR6/I6pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+ycBL9vnbS90AEBJIm+fOecH7kLgLt9EJFNxYphA770=; b=PYyCBRTdd3sV+B11o5W3WtiXc56DxIv90FGFupO/BDmz0D5iAzmbw8ItR2576T4amGA61Wa1k7OnzEgmuke1wDTLYZNopERvDjG0X4+U7pW8zQS8p4quLpYIOvaJ14yOBJ4nRp0Lv6zO9ivB3B0BT9rzaSswQx/HAwUfMypKVEsMSogq+KMrYZkHmNk/vMkZ2HLtMcCiTj/tlPTWM12lU9VGlei9rUyc5f3HlnQQnTktRHovMbPv2k443nihbtG/U8Mho1rr/2PZ4Y/dpA37k4bXkThC9zohKrb8MjqYhSRn5GV0SKaWoo7IybtngfVaJwzTZEFK1donji5l7BTRsQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+ycBL9vnbS90AEBJIm+fOecH7kLgLt9EJFNxYphA770=; b=ZmYoHEZAKc98I3QhHr7QGiETU/YC9lf1LMP/D54ERVY8XzeKOb+3c5ao816pACymeyassgIr3v5+Fxd7QIPQcNzyVyN7HgpzbfKF0a0pwaS//sv7HDQD5L9dnLXhhr3S0KERjdsSSG/DgdPirlOafj1We1BiS85286RYoYudo+A= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 09/11] xen/Arm: GICv3: Define remaining GIC registers for AArch32 Date: Mon, 5 Dec 2022 13:26:35 +0000 Message-ID: <20221205132637.26775-10-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT026:EE_|SA3PR12MB7949:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a364457-2ba1-40c9-0abd-08dad6c4de73 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LSU8hTgdt2bB1MI8I6/fOgwtEKgLkAD9s6OVVQUvxto6H16YNnnQe21CoaWW0wQkuqlN+RXIWZMe+fBdLt/O/sGMAcU+Lq+h+9h1NOhvvEqD+UOY+TQwdlqA8p5Jgts8KlYdxDrO8OlkpGVBfTfzE3y3sKEG1e1HhP41GqeHQl9AizfSzzxihAfp94YDeRyPBFzreo7APPFEnGCNT8KPCCCxcTKq/IWMIo8cuaQxKTm0BW9zmBKFoC9qORycLdtIhGvVajcCU+Nhf00JbKaXTdnQ8xVZQ6Radrqyo4pW5jPJ9vQqPLXr4dpi4CgwsJv8YAKGdLWdQ0c6IV//VY38hzZiZGasKN/WnZSM29eOclCT4Z8LB/W+se8CPs4q+2PhBcMnzrrS4cJd8IIU65vVkGtYCMZmwz20OzihBT8+B2cji4E/Ax2ZrDwBTaZvWMoOcuJXHZXDB4ofjvLWZkkLqPzRE3NOM8Kwz8Ws0bry/N31ACPpx2IP9dHuISky6nRjZ5LhY07N/IMVgjf2VqdcEZvekzPqTmXL7Cf9df+eK6PIWPaeNRs+FFTOjQriJu76YG+HT07lXLOGgMsvu3FXytpin5BE7giF262uIj56FhVl1MxdFwwX9+ZqAYeuAUJQwQGEkdDxnlgx9ZslCuSB8gEWpuhDfWp1QPUEs3sU5IsLJKhhbaxEcxbnORnKNI5qKcxLECnqp1DuQfONQWlM/2AS3dU1JaBOrxHHvCs3h50= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199015)(46966006)(36840700001)(40470700004)(6916009)(41300700001)(4326008)(2906002)(70586007)(8676002)(70206006)(316002)(54906003)(82310400005)(186003)(478600001)(1076003)(356005)(103116003)(40480700001)(36756003)(336012)(426003)(2616005)(86362001)(26005)(83380400001)(82740400003)(5660300002)(8936002)(81166007)(40460700003)(47076005)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 13:30:25.9893 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a364457-2ba1-40c9-0abd-08dad6c4de73 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7949 Define missing assembly aliases for GIC registers on arm32, taking the ones defined already for arm64 as a base. Aliases are defined according to the GIC Architecture Specification ARM IHI 0069H. Defined the following registers:- 1. Interrupt Controller Interrupt Priority Mask Register 2. Interrupt Controller System Register Enable register 3. Interrupt Controller Deactivate Interrupt Register 4. Interrupt Controller End Of Interrupt Register 1 5. Interrupt Controller Interrupt Acknowledge Register 1 6. Interrupt Controller Binary Point Register 1 7. Interrupt Controller Control Register 8. Interrupt Controller Interrupt Group 1 Enable register 9. Interrupt Controller Maintenance Interrupt State Register 10. Interrupt Controller End of Interrupt Status Register 11. Interrupt Controller Empty List Register Status Register 12. Interrupt Controller Virtual Machine Control Register Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Moved coproc regs definition to asm/cpregs.h v2 - 1. Defined register alias. 2. Style issues. 3. Defined ELSR, MISR, EISR to make it consistent with AArch64. v3 - 1. Rectified some of the register names. v4 - 1. Placed ICC_DIR after VBAR. 2. Added Rb. xen/arch/arm/include/asm/cpregs.h | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 4476c9f11b..6b083de204 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -161,6 +161,7 @@ #define DACR p15,0,c3,c0,0 /* Domain Access Control Register */ /* CP15 CR4: */ +#define ICC_PMR p15,0,c4,c6,0 /* Interrupt Priority Mask Register */ /* CP15 CR5: Fault Status Registers */ #define DFSR p15,0,c5,c0,0 /* Data Fault Status Register */ @@ -257,6 +258,7 @@ #define ICC_ASGI1R p15,1,c12 /* Interrupt Controller Alias SGI Group 1 Register */ #define ICC_SGI0R p15,2,c12 /* Interrupt Controller SGI Group 0 */ #define VBAR p15,0,c12,c0,0 /* Vector Base Address Register */ +#define ICC_DIR p15,0,c12,c11,1 /* Interrupt Controller Deactivate Interrupt Register */ #define HVBAR p15,4,c12,c0,0 /* Hyp. Vector Base Address Register */ /* @@ -279,6 +281,20 @@ #define ICH_AP1R2 __AP1Rx(2) #define ICH_AP1R3 __AP1Rx(3) +#define ICC_IAR1 p15,0,c12,c12,0 /* Interrupt Controller Interrupt Acknowledge Register 1 */ +#define ICC_EOIR1 p15,0,c12,c12,1 /* Interrupt Controller End Of Interrupt Register 1 */ +#define ICC_BPR1 p15,0,c12,c12,3 /* Interrupt Controller Binary Point Register 1 */ +#define ICC_CTLR p15,0,c12,c12,4 /* Interrupt Controller Control Register */ +#define ICC_SRE p15,0,c12,c12,5 /* Interrupt Controller System Register Enable register */ +#define ICC_IGRPEN1 p15,0,c12,c12,7 /* Interrupt Controller Interrupt Group 1 Enable register */ +#define ICC_HSRE p15,4,c12,c9,5 /* Interrupt Controller Hyp System Register Enable register */ +#define ICH_HCR p15,4,c12,c11,0 /* Interrupt Controller Hyp Control Register */ +#define ICH_VTR p15,4,c12,c11,1 /* Interrupt Controller VGIC Type Register */ +#define ICH_MISR p15,4,c12,c11,2 /* Interrupt Controller Maintenance Interrupt State Register */ +#define ICH_EISR p15,4,c12,c11,3 /* Interrupt Controller End of Interrupt Status Register */ +#define ICH_ELRSR p15,4,c12,c11,5 /* Interrupt Controller Empty List Register Status Register */ +#define ICH_VMCR p15,4,c12,c11,7 /* Interrupt Controller Virtual Machine Control Register */ + /* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */ #define __LR0(x) p15, 4, c12, c12, x #define __LR8(x) p15, 4, c12, c13, x @@ -379,6 +395,15 @@ #define HCR_EL2 HCR #define HPFAR_EL2 HPFAR #define HSTR_EL2 HSTR +#define ICC_BPR1_EL1 ICC_BPR1 +#define ICC_CTLR_EL1 ICC_CTLR +#define ICC_DIR_EL1 ICC_DIR +#define ICC_EOIR1_EL1 ICC_EOIR1 +#define ICC_IGRPEN1_EL1 ICC_IGRPEN1 +#define ICC_PMR_EL1 ICC_PMR +#define ICC_SGI1R_EL1 ICC_SGI1R +#define ICC_SRE_EL1 ICC_SRE +#define ICC_SRE_EL2 ICC_HSRE #define ICH_AP0R0_EL2 ICH_AP0R0 #define ICH_AP0R1_EL2 ICH_AP0R1 #define ICH_AP0R2_EL2 ICH_AP0R2 @@ -387,6 +412,10 @@ #define ICH_AP1R1_EL2 ICH_AP1R1 #define ICH_AP1R2_EL2 ICH_AP1R2 #define ICH_AP1R3_EL2 ICH_AP1R3 +#define ICH_EISR_EL2 ICH_EISR +#define ICH_ELRSR_EL2 ICH_ELRSR +#define ICH_HCR_EL2 ICH_HCR +#define ICC_IAR1_EL1 ICC_IAR1 #define ICH_LR0_EL2 ICH_LR0 #define ICH_LR1_EL2 ICH_LR1 #define ICH_LR2_EL2 ICH_LR2 @@ -419,6 +448,9 @@ #define ICH_LRC13_EL2 ICH_LRC13 #define ICH_LRC14_EL2 ICH_LRC14 #define ICH_LRC15_EL2 ICH_LRC15 +#define ICH_MISR_EL2 ICH_MISR +#define ICH_VMCR_EL2 ICH_VMCR +#define ICH_VTR_EL2 ICH_VTR #define ID_AFR0_EL1 ID_AFR0 #define ID_DFR0_EL1 ID_DFR0 #define ID_DFR1_EL1 ID_DFR1 From patchwork Mon Dec 5 13:26:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 580E6C47088 for ; Mon, 5 Dec 2022 14:53:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453826.711436 (Exim 4.92) (envelope-from ) id 1p2Cqe-0005AR-V6; Mon, 05 Dec 2022 14:53:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453826.711436; Mon, 05 Dec 2022 14:53:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cqe-0005AI-Rw; Mon, 05 Dec 2022 14:53:36 +0000 Received: by outflank-mailman (input) for mailman id 453826; Mon, 05 Dec 2022 14:53:35 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cqd-0005A2-Jn for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:53:35 +0000 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on20600.outbound.protection.outlook.com [2a01:111:f400:7eae::600]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 96eadaad-74ac-11ed-91b6-6bf2151ebd3b; Mon, 05 Dec 2022 15:53:34 +0100 (CET) Received: from CY5PR16CA0003.namprd16.prod.outlook.com (2603:10b6:930:10::7) by PH7PR12MB5653.namprd12.prod.outlook.com (2603:10b6:510:132::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.8; Mon, 5 Dec 2022 14:53:30 +0000 Received: from CY4PEPF0000C969.namprd02.prod.outlook.com (2603:10b6:930:10:cafe::b4) by CY5PR16CA0003.outlook.office365.com (2603:10b6:930:10::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19 via Frontend Transport; Mon, 5 Dec 2022 14:53:30 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000C969.mail.protection.outlook.com (10.167.241.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.8 via Frontend Transport; Mon, 5 Dec 2022 14:53:29 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:29:48 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:29:47 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:29:46 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 96eadaad-74ac-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ibNqC8FoPo7rMaFCj9d/D0xnm0rvzJjzhtx/VdM5AJsRntfmyRaYL3l0lqvbHtlf/DW/x/LlAzGzBflmLNK8Z09k0k0OKy2J1FjCXm9H2szuMuZ+LdC2Fj8Mop9hhagFq1tJEMR2QuRp4Zv9piMxV3OUk7U8RXyMAPFeq9BAjTYZ35jc+oUaggdofbe16SYLc4Tkk7zTfHNaJBDCQcR1FWiFJCW+s6H4sowhKDfCXh+/vcIRI/XzfeAijPT+YtAu3V1Ghr7MpMVL0xKjSogjqJkQg9WrCyWN754ljmXAD3mMUjevxxvmTlL3PwvWKgu+2JCltSo/cbSPZREBQZMTvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=d/f6KcnxjmuXzQKyqBzEdB2sXtJfFweqelRMZY8EzeE=; b=nIurm1d6qwmxIfuRCQ/BR6fQmtj06FPJILsjE/RONtqspp1xJPrLd0eyAerJSk5hJ0ZJAvAO7+PehIkM+xwsVJRvChUx1j6ayWf1E0z3mFW41Px5/KWwjHXsFhGwJ2tW4PyPCZ3uFh1zNyn0n/5sJhh+9c6yP2pCQKMFR1d3GFZK9QMr5i71LBR74VCFj+qQlxuIzdu2AER5W+Xdo8JEhBxKcfyoPAoLyeWnBOAq7sax/hJbAnAvK2Qt75EDquRzTtmYdB8DYDb4tWH8q1gw9Eli72wGYUe6lwqkaRCoZbeE4AMGl/iiXO8N8o8UIxtuWZG+BHnTIEUGcMsVcRu5vg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=d/f6KcnxjmuXzQKyqBzEdB2sXtJfFweqelRMZY8EzeE=; b=IQa83p4DI6R/IvI4IXp399qbFszBd0GvnG/ohFcVk/1mF+RYt/35Uysa0yo6UiRzvaUsWbDxLPqJpLfTy+BC1NRt0usPYvnV4RtKdrDnsRBHe91ce+oUdsmlQ9QnbRe9ixtY+7Vq0D9ZF0WHNcUxivqIh465uaskTlbWaWLSNV0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 10/11] xen/Arm: GICv3: Define macros to read/write 64 bit Date: Mon, 5 Dec 2022 13:26:36 +0000 Message-ID: <20221205132637.26775-11-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C969:EE_|PH7PR12MB5653:EE_ X-MS-Office365-Filtering-Correlation-Id: da91b90d-46c1-41ef-78da-08dad6d0791f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OezsHa977F9yKJL3YLSi90ZqxnL3Gh5SMEJs9SMXRWe65O75vkk0zS1KN27zjameRLc6w2vuEYP/N5VDkZD7ijonJSoNdznCEmXTCiWbzy9gfEPfhFrsoO5GFg8BV13zflGyfc49jM86KKPejQ/yQ5sk4vxETJ7YlnTYXPpWO1SIX5+h10ZioXbodVwd9hMMN5bl3sjBI9xDetQDO7Gg2NTSTBMBCoWBhbNLi9C9Sy+Ml5UpIYcAWq7K1XWgIiVt/XgqCxDUrP0yLSHC/XQw+bM0k5dyVlMQCqGgnCbjtM1uBf4eSYUNh3XMPhxEwfUtCF/JRC7uA5ImlhzBJbt7HfSU9fJkcWPx5jOdFN5Q6/Cu3o58me45yWp4KUWVuOJkfqrIeIrpufar9gds3jOOHgKSt28/GxsY4jya//K7hLS3IQX0fR9IF/mzaOPVannFjhlwIKeTnid513joQ3M7NbKkx/cBU62zOnbU8n9yeT9fizP03IDf+4b7tHH1yFFz32RpyQYhzd9TGLssyfkgYZtuCOhHyt44xvgLHLfmkXoH3Dry7srRy/O6xsftXhUdLq6u8d38kqRGA0HwfpWEx26swoD6z8fqy2xjii/HMbPRyhCT9AkyG3efHhDyP4yFAtToJpWp5MN/uYh7N6GbqWMnYse+BRCludFF+vCF5o5S6ljeAGIeBFesIkNAU4bYUQBzG2h5/kHz2n8U5janEKvPNWCOh1CJURKnKVVvzwc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(136003)(396003)(376002)(451199015)(46966006)(40470700004)(36840700001)(1076003)(336012)(2616005)(54906003)(40460700003)(316002)(6916009)(81166007)(36756003)(103116003)(356005)(86362001)(40480700001)(426003)(82740400003)(83380400001)(82310400005)(5660300002)(186003)(26005)(47076005)(6666004)(36860700001)(2906002)(8936002)(70206006)(41300700001)(4326008)(478600001)(8676002)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:53:29.9056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da91b90d-46c1-41ef-78da-08dad6d0791f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C969.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5653 On AArch32, ldrd/strd instructions are not atomic when used to access MMIO. Furthermore, ldrd/strd instructions are not decoded by Arm when running as a guest to access emulated MMIO region. Thus, we have defined readq_relaxed_non_atomic()/writeq_relaxed_non_atomic() which in turn calls readl_relaxed()/writel_relaxed() for the lower and upper 32 bits. For AArch64, readq_relaxed_non_atomic()/writeq_relaxed_non_atomic() invokes readq_relaxed()/writeq_relaxed() respectively. As GICv3 registers (GICD_IROUTER, GICR_TYPER) can be accessed in a non atomic manner, so we have used readq_relaxed_non_atomic()/readq_relaxed_non_atomic(). However, the following points are noted for the non atomic access :- 1. In gicv3_dist_init(), using non atomic write on GICD_IROUTER is fine as this gets invoked when interrupts are disabled. 2. In gicv3_populate_rdist(), using non atomic read on GICR_TYPER is fine as the register is read and the interrupts are disabled as well. 3. In gicv3_irq_set_affinity(), using non atomic write on GICD_IROUTER. This may be called with interrupts enabled. So, a non-atomic access (on AArch32) means the GIC will see a transient value when only one of two 32-bit will be updated. However, only AFF3 is defined in the upper 32 bits and they are 0, so this will never change. On AArch64, writeq_relaxed_non_atomic() invokes writeq_relaxed() (which is atomic), so this problem does not arise. Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall --- Changes from :- v1 - 1. Use ldrd/strd for readq_relaxed()/writeq_relaxed(). 2. No need to use le64_to_cpu() as the returned byte order is already in cpu endianess. v2 - 1. Replace {read/write}q_relaxed with {read/write}q_relaxed_non_atomic(). v3 - 1. Use inline function definitions for {read/write}q_relaxed_non_atomic(). 2. For AArch64, {read/write}q_relaxed_non_atomic() should invoke {read/write}q_relaxed(). Thus, we can avoid any ifdef in gic-v3.c. v4 - 1. Updated the commit message. xen/arch/arm/gic-v3.c | 6 +++--- xen/arch/arm/include/asm/arm32/io.h | 20 ++++++++++++++++++++ xen/arch/arm/include/asm/arm64/io.h | 2 ++ 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 6457e7033c..3c5b88148c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -651,7 +651,7 @@ static void __init gicv3_dist_init(void) affinity &= ~GICD_IROUTER_SPI_MODE_ANY; for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ ) - writeq_relaxed(affinity, GICD + GICD_IROUTER + i * 8); + writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8); } static int gicv3_enable_redist(void) @@ -745,7 +745,7 @@ static int __init gicv3_populate_rdist(void) } do { - typer = readq_relaxed(ptr + GICR_TYPER); + typer = readq_relaxed_non_atomic(ptr + GICR_TYPER); if ( (typer >> 32) == aff ) { @@ -1265,7 +1265,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask) affinity &= ~GICD_IROUTER_SPI_MODE_ANY; if ( desc->irq >= NR_GIC_LOCAL_IRQS ) - writeq_relaxed(affinity, (GICD + GICD_IROUTER + desc->irq * 8)); + writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc->irq * 8)); spin_unlock(&gicv3.lock); } diff --git a/xen/arch/arm/include/asm/arm32/io.h b/xen/arch/arm/include/asm/arm32/io.h index 73a879e9fb..782b564809 100644 --- a/xen/arch/arm/include/asm/arm32/io.h +++ b/xen/arch/arm/include/asm/arm32/io.h @@ -80,10 +80,30 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) +/* + * ldrd instructions are not decoded by Arm when running as a guest to access + * emulated MMIO region. Thus, readq_relaxed_non_atomic() invokes readl_relaxed() + * twice to read the lower and upper 32 bits. + */ +static inline u64 readq_relaxed_non_atomic(const volatile void __iomem *addr) +{ + u64 val = (((u64)readl_relaxed(addr + 4)) << 32) | readl_relaxed(addr); + return val; +} #define writeb_relaxed(v,c) __raw_writeb(v,c) #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) +/* + * strd instructions are not decoded by Arm when running as a guest to access + * emulated MMIO region. Thus, writeq_relaxed_non_atomic() invokes writel_relaxed() + * twice to write the lower and upper 32 bits. + */ +static inline void writeq_relaxed_non_atomic(u64 val, volatile void __iomem *addr) +{ + writel_relaxed((u32)val, addr); + writel_relaxed((u32)(val >> 32), addr + 4); +} #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) diff --git a/xen/arch/arm/include/asm/arm64/io.h b/xen/arch/arm/include/asm/arm64/io.h index 30bfc78d9e..2e2ab24f78 100644 --- a/xen/arch/arm/include/asm/arm64/io.h +++ b/xen/arch/arm/include/asm/arm64/io.h @@ -102,11 +102,13 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; }) #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; }) #define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; }) +#define readq_relaxed_non_atomic(c) readq_relaxed(c) #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) +#define writeq_relaxed_non_atomic(v,c) writeq_relaxed(v,c) /* * I/O memory access primitives. Reads are ordered relative to any From patchwork Mon Dec 5 13:26:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13064589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 390FFC4321E for ; Mon, 5 Dec 2022 14:53:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.453827.711441 (Exim 4.92) (envelope-from ) id 1p2Cqf-0005Dw-80; Mon, 05 Dec 2022 14:53:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 453827.711441; Mon, 05 Dec 2022 14:53:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cqf-0005DV-4B; Mon, 05 Dec 2022 14:53:37 +0000 Received: by outflank-mailman (input) for mailman id 453827; Mon, 05 Dec 2022 14:53:36 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p2Cqe-0005AC-Di for xen-devel@lists.xenproject.org; Mon, 05 Dec 2022 14:53:36 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on20605.outbound.protection.outlook.com [2a01:111:f400:fe59::605]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 972fd834-74ac-11ed-8fd2-01056ac49cbb; Mon, 05 Dec 2022 15:53:35 +0100 (CET) Received: from DM6PR03CA0071.namprd03.prod.outlook.com (2603:10b6:5:100::48) by CH0PR12MB5219.namprd12.prod.outlook.com (2603:10b6:610:d2::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14; Mon, 5 Dec 2022 14:53:32 +0000 Received: from DS1PEPF0000E631.namprd02.prod.outlook.com (2603:10b6:5:100:cafe::d3) by DM6PR03CA0071.outlook.office365.com (2603:10b6:5:100::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Mon, 5 Dec 2022 14:53:32 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E631.mail.protection.outlook.com (10.167.17.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.8 via Frontend Transport; Mon, 5 Dec 2022 14:53:31 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 07:30:01 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 5 Dec 2022 05:29:59 -0800 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 5 Dec 2022 07:29:58 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 972fd834-74ac-11ed-8fd2-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iAQAdLU26zmxe102BZwnjzzvkYKXZ8J465eHsHC6cUq7/DJI4yOKx0+uWb2uCGN+VD2uP/IBgwv1PBHSuIlUjMmL7iWpwQTt4z2VAfLYmQWGGzCHvFA7INNB5mK3jicBZOkAsNLg206cSEiP40EWl/Epsr+eaAxdA4bkRmgz2knkYzvLlEsJEGY7uRsB2fbVEIeJqyu+ssyLEGQQkR44GSp4RTRtNciIciKaw/ijCxkSuadagob0ZZXWhV8B8UUmsiTfMpyOtmXM2TTMgsJuTVjPqbjCr88ODDrrTh4yIU8pFrENql9YYc80GjkjzOZxVCM7PUqZWL3vYEWGHuBWiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VTKYXoGyAgkPR5zIiQZmjQ3vxNlnyj3UelY+os3E+uM=; b=L9LKkvSrvjYAYk9da6QFbDai1iEikNO0ej6917bbokxN6k/b0uEYMfzfIxZRXXGpDHrQtXLGd5h/dHK3jTtk8NoXaPy0D/++OzwQUq1A+ILEPXWCNNvDOglZc/oQoDvrwF6MpQycL5MMLlCg4ayUFy4AvDE7Qv7k2YfWw6PkoGFMVi7VNS1k1PIDe7o1QuLmdACVygtxafCKQ4zpZBjZai35ohwAmSjPmpGcIgkLppoI5LNvGjcrLse64h/CD7ApypuJQ2v7frHxTL1EcGcJjfgnNKjFT0KlhAczs72G3v0PTnHcBmifVP0D30k4BK0YraMM0RFW0/UHixVVQ+V/iQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VTKYXoGyAgkPR5zIiQZmjQ3vxNlnyj3UelY+os3E+uM=; b=iIWX9p+gXLY2YgmB+2ePmtH2XvGKyintclYB0VGmW8Y9pUlM3IDgMZFEO5sAMrg/I9gShhHwLYGf30hx9j7h4AB5a5UTrBdRQ0XW443ggi1IEWIXivZD/ZrCSdcT/cIvZPOHEHZKq6JUONof1P7zWa7whSGFWSBfQpY/FFuir/A= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32 Date: Mon, 5 Dec 2022 13:26:37 +0000 Message-ID: <20221205132637.26775-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E631:EE_|CH0PR12MB5219:EE_ X-MS-Office365-Filtering-Correlation-Id: 452f5bd8-0cc1-4595-c4f6-08dad6d07a1c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BwNWk3zIIyeBRgo+cBkIwlyf3aIS/gQTZxQatgKh6Nz8yqvr1rTDwkZHgiFCIGKEQRKHZotzSx4r21FEt8VvY07YEJbEhIvsfAyyr7Hnu+PEB/pzXqnzXksKXQhadAke4xQAnv52Ye7XU5KNmKI5ASHVRNU69IVCC6NAbsYOUTy7jh2iYLpr7/svHeSIwi4Hxka2xtUIEfUnzx2ciQ7+k2W5/SK43vwr+Vw3i2qPqhDQr3vRL5J/1heP7U34ikRKVS2WNm8bc4yJvwbApo+oyzlUMEqziLFGAyt6BC/cUHlQpmAODO5a35OVqnjOmuSjLL7j8dIiVszahg5nwgu2Sq56Sa4aJiI6fLjDwizKw/Wc0F9QWnsv6KJAssal+oq/A1Y84U45awJTURH8lj179PhwrHt8LjdOKbU22k+HBXLMWwJloeBUFjz9OqNPBzboluMNYagdE9hj/hIvVwNoS8rK9afF6xr7wGvE3wWHDyKDbffeAC7cxQgGanWVUmowstHKrf0xHg1YQnVUikBeVc8CsIinquFVNF6mNUTvBE4fmeP94vrYySM6VdAlW7Pof7jI5njTpG3H/zzCon+YaRRmEdgTCNY/mHDWBa0WYjrkZV6xS223VNZHPwK1n6/+S6t6YiXz0gOBGPpl78SaG2kYwvPBrHAShOqDNXfZKWAXwANBLy1W1Wjly0LkaULVsrfZ2m2UsgK1yz+9mXU+nJHlFcoJcg5oiAj1K3T+Anc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199015)(46966006)(40470700004)(36840700001)(83380400001)(36860700001)(103116003)(356005)(86362001)(81166007)(82740400003)(5660300002)(41300700001)(40460700003)(8936002)(2906002)(4326008)(82310400005)(8676002)(40480700001)(186003)(26005)(336012)(47076005)(426003)(1076003)(6666004)(54906003)(316002)(2616005)(6916009)(70586007)(478600001)(70206006)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 14:53:31.5812 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 452f5bd8-0cc1-4595-c4f6-08dad6d07a1c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E631.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5219 One can now use GICv3 on AArch32 systems. However, ITS is not supported. The reason being currently we are trying to validate GICv3 on an AArch32_v8R system. Refer ARM DDI 0568A.c ID110520, B1.3.1, "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not implement LPI support." By default GICv3 is disabled on AArch32 and enabled on AArch64. Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changed from :- v1 - 1. Remove "ARM_64 || ARM_32" as it is always true. 2. Updated SUPPORT.md. v2 - 1. GICv3 is enabled by default only on ARM_64. 2. Updated SUPPORT.md. v3 - 1. GICv3 is not selected by ARM_64. Rather, it is optionally enabled. 2. GICv3 is disabled by default on ARM_32. v4 - 1. Updated the help message for GICV3. 2. I have kept the Rb given on v4 as the change looks trivial. SUPPORT.md | 7 +++++++ xen/arch/arm/Kconfig | 9 +++++---- xen/arch/arm/include/asm/cpufeature.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index ab71464cf6..295369998e 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -76,6 +76,13 @@ For the Cortex A57 r0p0 - r1p1, see Errata 832075. Status, ARM SMMUv3: Tech Preview Status, Renesas IPMMU-VMSA: Supported, not security supported +### ARM/GICv3 + +GICv3 is an interrupt controller specification designed by Arm. + + Status, Arm64: Security supported + Status, Arm32: Supported, not security supported + ### ARM/GICv3 ITS Extension to the GICv3 interrupt controller to support MSI. diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 52a05f704d..239d3aed3c 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -41,16 +41,17 @@ config ARM_EFI config GICV3 bool "GICv3 driver" - depends on ARM_64 && !NEW_VGIC - default y + depends on !NEW_VGIC + default n if ARM_32 + default y if ARM_64 ---help--- Driver for the ARM Generic Interrupt Controller v3. - If unsure, say Y + If unsure, use the default setting. config HAS_ITS bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED - depends on GICV3 && !NEW_VGIC + depends on GICV3 && !NEW_VGIC && !ARM_32 config HVM def_bool y diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index c86a2e7f29..c62cf6293f 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -33,6 +33,7 @@ #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) #ifdef CONFIG_ARM_32 +#define cpu_has_gicv3 (boot_cpu_feature32(gic) >= 1) #define cpu_has_gentimer (boot_cpu_feature32(gentimer) == 1) /* * On Armv7, the value 0 is used to indicate that PMUv2 is not