From patchwork Tue Dec 6 17:36:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13066184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 220BDC352A1 for ; Tue, 6 Dec 2022 17:37:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235297AbiLFRhA (ORCPT ); Tue, 6 Dec 2022 12:37:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235586AbiLFRgi (ORCPT ); Tue, 6 Dec 2022 12:36:38 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E5873C6CA; Tue, 6 Dec 2022 09:36:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=drYZGP/b+JmzZEHEGKwIK91yQ4nDPEcO2MEztxA74ZXk0mLLgQ2ER6fX2r6EUeTPlK9v1hAby8SfrP5JNE6oKK1HGYBb1Qm7IXjhAB1mHmPaBWwTxuYVdsOEbd18sSEmuJK4vlQRCIKvEDZTEaJ7nWSVicOATslqnbZxwEDrp8hrZBSkTqn89V3Qiwo76baHGUeT0V4YmXjFZAveAWviRsfzzOlIBRXw4HuXGSaDJtwENQCoTSe4NrWhUzQUFAPuGgiHJAUtKYec57O1lgNy9DwZVjtw4HU2v+B8OLD5n8M7s3pnz7FkIN7X/xFgV1CFl+c2H997yLLP5v5EATPrjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Auldu/nWsyb20QAB4PBQ5TaoIOsv5m3Y/qhsz9Ke73E=; b=Tc5qO+exwUXlF0vB60OJEB5Du93YltBllijMm30yxxmcAl9cnQaSEl+PTiMVIizNYq3vLf3TA5jZQguPlypYuLxcAlPHaoKxlaK74M990vfWQOfipCCVBRC8+INvhbsWDneeVTwLX/J+2Jq1KtZxzNq0+AZv5zXGEiiWVNn3Ob5ukwOnfRZh9+zGr1/pq4Qz5Nf4ltpHSn9QbA87yQtLh2kazV5xrqcHj474z7kP7usoOjr92kn2jq19JASmuvmBsXKo4lLNYgQWOqKtialGDIdGcIlPKahDKUafiOag4wtDeECWO8ygoQu41MYG8qEQChFu0JGAReYfe2VOTWg+9g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Auldu/nWsyb20QAB4PBQ5TaoIOsv5m3Y/qhsz9Ke73E=; b=GaFfyksUsEfcYe+ObUvC5cjRi08GBm1Tc5ZOflqUzgsPF7VS89slmenO7Pkn4cYs0zzQb6o5K5GtxD2YESoJ8W8x0ZikqKHTuP/CSsLk2Kuj8wsGVF3DvNwaefxvvdOt0W1fzuoMBo4FmV3R2W06oY5hfmDGN9Amav5IGCK3u/U= Received: from MW4PR04CA0225.namprd04.prod.outlook.com (2603:10b6:303:87::20) by DS0PR12MB8367.namprd12.prod.outlook.com (2603:10b6:8:fd::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14; Tue, 6 Dec 2022 17:36:21 +0000 Received: from CO1NAM11FT032.eop-nam11.prod.protection.outlook.com (2603:10b6:303:87:cafe::93) by MW4PR04CA0225.outlook.office365.com (2603:10b6:303:87::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT032.mail.protection.outlook.com (10.13.174.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:20 +0000 Received: from titanite-35bahost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Dec 2022 11:36:17 -0600 From: Yazen Ghannam To: CC: , , , , Borislav Petkov , "Yazen Ghannam" Subject: [PATCH v6 1/4] x86/mce: Cleanup bank processing on init Date: Tue, 6 Dec 2022 11:36:04 -0600 Message-ID: <20221206173607.1185907-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206173607.1185907-1-yazen.ghannam@amd.com> References: <20221206173607.1185907-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT032:EE_|DS0PR12MB8367:EE_ X-MS-Office365-Filtering-Correlation-Id: 30760b8b-1ea5-4bdf-1986-08dad7b0636a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5sdEwfMtjLXdNpUeqOh/9zj0+X5KPnnL3lTR6YeiJuJz4K2BuY2SDx6R+CzDuQBceyejU198TLzjQ+3BCrHnN4RKwu7G47k+pKzBaW6k17Q1CtyR/8EpREb71jkH+zvIUdajCfW9EQDoSn9nEJv2Sk7QAlapJZWEbFyHPTqThxFuQtwS63nfq9hpmJz/B8sBE6Y1OD1kzDtX18u/b0+7C1g5KpmMyT5KTKTOLLjFwh2e82GTxUNv1nh54rRxerAxo8Xi9Bnds00PDmzQ40li94Zo/87eR931JeDvN171Q0GyipDSpQ2fzc/G4HSZk/DZAQ8S8urrwBTURxlksb1RCibNUVqr23XlxbBQQiASYTv4fVFkDddrUulE8v29pYCWGJ3k9keoocbVM7c4P/RDZBqIXdkxCkFOQeDuepiIjhUQVAYn0c8/HFP1OxtZHsEMbt+qB0A37T8ZV6OxcYCIV4+nZk38nCiE7g5FT9uLHSrMkugkaHhxPWoRscPOW92HS2g9H8VpeollOuBzHAoiFNsJF0skDD6N3zX8giA1E3W/ZIvOH7b5XjFduoL7ghOahf72VQrOjE7VBRt34dxB79ZM8qm4fAf1TfcbdzSe9Dxllm/hwWFEF44ZxQQOZvHibdJPxNDdkhk1d2X8LRmsP9xkESXzkxVsEnnStC4tGd4pGBE5xjE/D+xm47IrAEBSoUPVYvaRu99+GUkp/M4BS0iLRBkt2nZQKoZN35CxfvAroyiypfzFJw964v4YOCb7CGLWkiWjHLVIl7phEbSzefk2c2dyeZWo+2Co0AqeK0M= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199015)(36840700001)(46966006)(40470700004)(426003)(47076005)(40460700003)(86362001)(7696005)(478600001)(966005)(40480700001)(81166007)(36756003)(8676002)(82740400003)(82310400005)(16526019)(186003)(2616005)(36860700001)(1076003)(336012)(44832011)(5660300002)(41300700001)(4326008)(26005)(6666004)(83380400001)(356005)(70206006)(15650500001)(54906003)(70586007)(316002)(8936002)(2906002)(6916009)(36900700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 17:36:20.6897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30760b8b-1ea5-4bdf-1986-08dad7b0636a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8367 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Borislav Petkov Unify the bank preparation into __mcheck_cpu_init_clear_banks(), rename that function to what it does now - prepares banks. Do this so that generic and vendor banks init goes first so that settings done during that init can take effect before the first bank polling takes place. Move __mcheck_cpu_check_banks() into __mcheck_cpu_init_prepare_banks() as it already loops over the banks. Signed-off-by: Borislav Petkov Reviewed-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/Ylb3/4oi6KAjdsJW@zn.tnic v6: New. Added Yazen's Reviewed-by. arch/x86/include/asm/mce.h | 3 +- arch/x86/kernel/cpu/mce/core.c | 64 ++++++++++------------------------ 2 files changed, 19 insertions(+), 48 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6e986088817d..0dd7752345ec 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -253,8 +253,7 @@ DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); enum mcp_flags { MCP_TIMESTAMP = BIT(0), /* log time stamp */ MCP_UC = BIT(1), /* log uncorrected errors */ - MCP_DONTLOG = BIT(2), /* only clear, don't log */ - MCP_QUEUE_LOG = BIT(3), /* only queue to genpool */ + MCP_QUEUE_LOG = BIT(2), /* only queue to genpool */ }; bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2c8ec5c71712..5f406d135d32 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -738,9 +738,6 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) log_it: error_seen = true; - if (flags & MCP_DONTLOG) - goto clear_it; - mce_read_aux(&m, i); m.severity = mce_severity(&m, NULL, NULL, false); /* @@ -1707,7 +1704,7 @@ static void __mcheck_cpu_mce_banks_init(void) /* * Init them all, __mcheck_cpu_apply_quirks() is going to apply * the required vendor quirks before - * __mcheck_cpu_init_clear_banks() does the final bank setup. + * __mcheck_cpu_init_prepare_banks() does the final bank setup. */ b->ctl = -1ULL; b->init = true; @@ -1746,21 +1743,8 @@ static void __mcheck_cpu_cap_init(void) static void __mcheck_cpu_init_generic(void) { - enum mcp_flags m_fl = 0; - mce_banks_t all_banks; u64 cap; - if (!mca_cfg.bootlog) - m_fl = MCP_DONTLOG; - - /* - * Log the machine checks left over from the previous reset. Log them - * only, do not start processing them. That will happen in mcheck_late_init() - * when all consumers have been registered on the notifier chain. - */ - bitmap_fill(all_banks, MAX_NR_BANKS); - machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); - cr4_set_bits(X86_CR4_MCE); rdmsrl(MSR_IA32_MCG_CAP, cap); @@ -1768,36 +1752,22 @@ static void __mcheck_cpu_init_generic(void) wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); } -static void __mcheck_cpu_init_clear_banks(void) +static void __mcheck_cpu_init_prepare_banks(void) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + mce_banks_t all_banks; + u64 msrval; int i; - for (i = 0; i < this_cpu_read(mce_num_banks); i++) { - struct mce_bank *b = &mce_banks[i]; - - if (!b->init) - continue; - wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); - wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); + /* + * Log the machine checks left over from the previous reset. Log them + * only, do not start processing them. That will happen in mcheck_late_init() + * when all consumers have been registered on the notifier chain. + */ + if (mca_cfg.bootlog) { + bitmap_fill(all_banks, MAX_NR_BANKS); + machine_check_poll(MCP_UC | MCP_QUEUE_LOG, &all_banks); } -} - -/* - * Do a final check to see if there are any unused/RAZ banks. - * - * This must be done after the banks have been initialized and any quirks have - * been applied. - * - * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. - * Otherwise, a user who disables a bank will not be able to re-enable it - * without a system reboot. - */ -static void __mcheck_cpu_check_banks(void) -{ - struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); - u64 msrval; - int i; for (i = 0; i < this_cpu_read(mce_num_banks); i++) { struct mce_bank *b = &mce_banks[i]; @@ -1805,6 +1775,9 @@ static void __mcheck_cpu_check_banks(void) if (!b->init) continue; + wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); + wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); + rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); b->init = !!msrval; } @@ -2169,8 +2142,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_init_early(c); __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(c); - __mcheck_cpu_init_clear_banks(); - __mcheck_cpu_check_banks(); + __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_setup_timer(); } @@ -2338,7 +2310,7 @@ static void mce_syscore_resume(void) { __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); - __mcheck_cpu_init_clear_banks(); + __mcheck_cpu_init_prepare_banks(); } static struct syscore_ops mce_syscore_ops = { @@ -2356,7 +2328,7 @@ static void mce_cpu_restart(void *data) if (!mce_available(raw_cpu_ptr(&cpu_info))) return; __mcheck_cpu_init_generic(); - __mcheck_cpu_init_clear_banks(); + __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_init_timer(); } From patchwork Tue Dec 6 17:36:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13066186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DA09C47090 for ; Tue, 6 Dec 2022 17:37:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235446AbiLFRhC (ORCPT ); Tue, 6 Dec 2022 12:37:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234866AbiLFRgi (ORCPT ); Tue, 6 Dec 2022 12:36:38 -0500 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2077.outbound.protection.outlook.com [40.107.100.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C7EA3C6CD; Tue, 6 Dec 2022 09:36:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kwVouJ79/r23e3rP0/D9xtFymij5qx1fPq+iVNmW5KBfaCDq4Gr9wzfGO7+RJCEXyZ2LVhiRw9OMql6safW5qmJqyOuM+uvgJY/WLrkzKGol2Kj9vItdLncFGUK7yon609sPIBQfkGYTxKjAG/JbE6dtL8f5/ej7CY7ua8/Dhbk8T4p9sIMMHcDzV5qc5yJGij5nLFEe7kqAj8KEURGAylD+s9HNjtSxDfVXbsnLqMPd53YPaPgsH3akxtnOJ0UkjTL9YBZFkCDJQihevNG0tDu0ehdyfugcc8/aOOsM2dE5SGqF67BCP/5y4SIaVLUTgj6rjWvGgun8tx4BT/bGNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rMF2H8/NQVQsNoyo2bC9s59caUM3T+h9DODdJ//at0k=; b=cQHhiW7qQeCvjU6qu8MsIgGSd82bC1XW/PWSKNX8ebnL7Kl0GP58HkJawdZCWcZkC8DRg+nINSzpYQPUOL963IUgnCpOPUlWMNJWzLQLCodjsDBxNBPuZgcnxneTdzqwpJsP5k8sNTwAKh8/hxn7waOm03+qDbV48WcSVYwb85bjiIZ7qzcgk6hwJDoVlLL1BEqRmCL1L0E9MdCegGqwQtaSr485a3R2TYX8+HoD4Vgcca7IiJu3uaet1yr+NiYCVtP31dUtrb/MD55xW9CG6uPs0WtNryJ7mOhq3p5fwoYKtrM8lxh0e2Prg/itXIYw+9kw7axz6CUXu00exiBapA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rMF2H8/NQVQsNoyo2bC9s59caUM3T+h9DODdJ//at0k=; b=yQ2ee0l/NwJPSYWwObTCRaxpBmh29v9Vec5pJ++be0ApNp9h2AxKrwGz8VdSue1353hZJ4TtTwqlIJ98s3Tq53rMurm2BIrXZxgBwhPZA3OVNlqzm3oUskdSazzn2C2qOW2tWwz/m2Wm2Uyy0mYG0NuxAR8OBPVoOwDcLj7O1yI= Received: from MW4PR04CA0225.namprd04.prod.outlook.com (2603:10b6:303:87::20) by MW4PR12MB6873.namprd12.prod.outlook.com (2603:10b6:303:20c::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13; Tue, 6 Dec 2022 17:36:22 +0000 Received: from CO1NAM11FT032.eop-nam11.prod.protection.outlook.com (2603:10b6:303:87:cafe::8e) by MW4PR04CA0225.outlook.office365.com (2603:10b6:303:87::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT032.mail.protection.outlook.com (10.13.174.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:21 +0000 Received: from titanite-35bahost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Dec 2022 11:36:18 -0600 From: Yazen Ghannam To: CC: , , , , Yazen Ghannam Subject: [PATCH v6 2/4] x86/mce: Remove __mcheck_cpu_init_early() Date: Tue, 6 Dec 2022 11:36:05 -0600 Message-ID: <20221206173607.1185907-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206173607.1185907-1-yazen.ghannam@amd.com> References: <20221206173607.1185907-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT032:EE_|MW4PR12MB6873:EE_ X-MS-Office365-Filtering-Correlation-Id: eccb75f5-beaa-42e9-5f93-08dad7b063f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kRiIJgoJoxvsVqanxf0L/Bs2PxkN0kNwZCHEd8cAEWfAv/9AGo9P3ggIddUAXapF03UVvOSg8lZ0UY1+WjqsSUJ/LhuRQhQy6tnmTd1aBNv9rfLB2QueQgVC1Bu+VJLV1NfrVH9l+faDvqniBoYdb2yezwnjqQu1pV6ZrEyNTMNflJtHLPk6K1RLba6KxmBB2aTF4VopRM5xnVaMgMrQiXTXStD4kgSwBZHUmMd4CUmjeP3vfqBTACg8soxn5YxcghEIgRSaoLqDwPJdOGQ+zf4S7zzOW43ctluwjPYVsYHXN+zGWy1ptdTRDNAzornyIjRNzLdl+xXkDnCy8hXlfy8+DeCj4vM0ihNjeLF6pAl1BfvVNQ7qmElIOlx8AAq2YmAx9YOWcc5Xf4vcihNxBwRdqtmN3Ul2UJ21C4Dk1IXcRIv89kDeWiSI5CqET/7Ls2Oqhe/NzsWLnzgi0aIkNy6dl8S41nOgC9dpaj4Ba7Z8YPAm50RCcP1+M250ft6rT4MRBcJY7Fwx5mQ8fL9omPINGr4zF+xHPbxuCv1QwaYT0Xg1kV4FZH8n9P1HFfKuo4d06A3ouWRix7TfJ+ntXJH5NJ/1LCE30avfh5VEiD8bZqef8brc5yU+8jmjqRbsE/QPRSaodHCmtD8owInp1wk17RJMh7GMItp7aybbotgeDeeaETTZq6ePFa6bbOljHcer2sorUivxVFet/o6r0ZAW9fUvYxcSTMXZXpipXkjrYPp1WDm07vr8UjZ+lbaWRHAirHVly6n5SkcAZgyaTkDBzhja4MsU9NpXx8L4M+Y= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199015)(46966006)(40470700004)(36840700001)(6916009)(54906003)(47076005)(478600001)(26005)(6666004)(81166007)(316002)(70206006)(70586007)(4326008)(8676002)(7696005)(966005)(44832011)(1076003)(2906002)(36860700001)(336012)(41300700001)(83380400001)(186003)(5660300002)(16526019)(40480700001)(36756003)(2616005)(82740400003)(40460700003)(356005)(426003)(8936002)(82310400005)(86362001)(36900700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 17:36:21.5959 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eccb75f5-beaa-42e9-5f93-08dad7b063f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6873 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The __mcheck_cpu_init_early() function was introduced so that some vendor-specific features are detected before the first MCA polling event done in __mcheck_cpu_init_generic(). Currently, __mcheck_cpu_init_early() is only used on AMD-based systems and additional code will be needed to support various system configurations. However, the current and future vendor-specific code should be done during vendor init. This keeps all the vendor code in a common location and simplifies the generic init flow. Move all the __mcheck_cpu_init_early() code into mce_amd_feature_init(). Also, move __mcheck_cpu_init_generic() after __mcheck_cpu_init_prepare_banks() so that MCA is enabled after the first MCA polling event. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/YqJHwXkg3Ny9fI3s@yaz-fattaah v6: New. arch/x86/kernel/cpu/mce/amd.c | 4 ++++ arch/x86/kernel/cpu/mce/core.c | 20 +++----------------- 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 10fb5b5c9efa..b80472a52ad8 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -681,6 +681,10 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; + mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); + mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); + mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); + mce_flags.amd_threshold = 1; for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 5f406d135d32..9efd6d010e2d 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1906,19 +1906,6 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) return 0; } -/* - * Init basic CPU features needed for early decoding of MCEs. - */ -static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) -{ - if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { - mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); - mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); - mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); - mce_flags.amd_threshold = 1; - } -} - static void mce_centaur_feature_init(struct cpuinfo_x86 *c) { struct mca_config *cfg = &mca_cfg; @@ -2139,10 +2126,9 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) mca_cfg.initialized = 1; - __mcheck_cpu_init_early(c); - __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(c); __mcheck_cpu_init_prepare_banks(); + __mcheck_cpu_init_generic(); __mcheck_cpu_setup_timer(); } @@ -2308,9 +2294,9 @@ static void mce_syscore_shutdown(void) */ static void mce_syscore_resume(void) { - __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); __mcheck_cpu_init_prepare_banks(); + __mcheck_cpu_init_generic(); } static struct syscore_ops mce_syscore_ops = { @@ -2327,8 +2313,8 @@ static void mce_cpu_restart(void *data) { if (!mce_available(raw_cpu_ptr(&cpu_info))) return; - __mcheck_cpu_init_generic(); __mcheck_cpu_init_prepare_banks(); + __mcheck_cpu_init_generic(); __mcheck_cpu_init_timer(); } From patchwork Tue Dec 6 17:36:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13066195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 316F5C352A1 for ; Tue, 6 Dec 2022 17:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234632AbiLFRhT (ORCPT ); Tue, 6 Dec 2022 12:37:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235477AbiLFRgo (ORCPT ); Tue, 6 Dec 2022 12:36:44 -0500 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2072.outbound.protection.outlook.com [40.107.243.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B0D83B9FF; Tue, 6 Dec 2022 09:36:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XQuS686Rmug8e8MGWOcwzDRE8g5ccuEjKIF45A9L/RVYPxe2C694J6d/kiJB/zKiFX1jPDEYf5rwB89wSKaBXIPns8/dZewxqhB9t75TNouPvn+2SXlxOASm3+7+sgTAT+OwdB4gkGB6Nfl3+Ra6FxNaoFNC+HVxDxrlKWdRda61i77geZ3J+H3W+s5GZ6kzVz1E5EHZ/cpcmQES+fMNMX+cYtMj/6+qR+RGu4dgUGnBOri6UO5emopaeQunKEVF/XWyU4tEZqxvlH0oEKovI2SSY6qK/0Jl1NifyMgFpzErk64ABqbKwZwZVxhQ2KBdBVjskqYSCUiog4dfIx1mgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yk0Jk8r1FtwBQZ5YKXHBLBG4RsB3g/EpJ6h6R5nZ0g4=; b=QVNIIu6k9hYRoc9LiVsPVKp2ynPtywQPJrwMpLkpI+oGHRtoFLCBchKVgIw14j+Ojs2ELGCTIE3U4iRGIdVtV/B6fRkyaj3nwWRlIlCNRnz1pHQqb3bleq87O7yW0LHsdq6Dpwl7R4qKAjmhZb6KKWr0mft9r5zPEoBpVxEojB63ovMLm0bu8DBBM/qDJY2Z7al2W1Yx5sq3XPHvGqy6lDPmUuWKEZHW40Igm/c7Wk5U1uOpeBr2dY2jTh2Fio+a48fUAnHdib9qQkarYZZHp5LZwQtf2cpqasYIgb7D9ULVGm74co+10h5AXj6pRmsDBz+5Bl/57ajQBt/VK06pjQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yk0Jk8r1FtwBQZ5YKXHBLBG4RsB3g/EpJ6h6R5nZ0g4=; b=OmBJbaeUkwlDOvSj1xpOd/1bgzO5aa9gZEhmDKoAtEBdXuYJ95KZsXBJI9h/CAN6bwfCteHqxAU3rSYAvbJmqLCFGw6qdSSLRK12m+9JNrG45o71JJVkZ/8wKdkztT4UM5dg/mntUNSCOcMJdYs8IpHahiQY3pcjC1bMZDfDRa8= Received: from MW4PR04CA0222.namprd04.prod.outlook.com (2603:10b6:303:87::17) by SJ0PR12MB6805.namprd12.prod.outlook.com (2603:10b6:a03:44f::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.13; Tue, 6 Dec 2022 17:36:23 +0000 Received: from CO1NAM11FT032.eop-nam11.prod.protection.outlook.com (2603:10b6:303:87:cafe::35) by MW4PR04CA0222.outlook.office365.com (2603:10b6:303:87::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT032.mail.protection.outlook.com (10.13.174.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:22 +0000 Received: from titanite-35bahost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Dec 2022 11:36:18 -0600 From: Yazen Ghannam To: CC: , , , , Yazen Ghannam Subject: [PATCH v6 3/4] x86/mce: Define function to extract ErrorAddr from MCA_ADDR Date: Tue, 6 Dec 2022 11:36:06 -0600 Message-ID: <20221206173607.1185907-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206173607.1185907-1-yazen.ghannam@amd.com> References: <20221206173607.1185907-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT032:EE_|SJ0PR12MB6805:EE_ X-MS-Office365-Filtering-Correlation-Id: 48f632c0-fff9-46cc-f577-08dad7b0646d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Atcz1p2CJgJQzHTXI8ejEX6EBj0J+7uUkzriPYewjp29mbDe/HEjnC4DI+oFVmdNMRfURHe2dwt9e581A0XbIGuxcgH5Te7pzYmMqS64nKNDEJHdeTHjR3jNilzdT1fhRH+ZnXdqs/G9l+9DZRmCktE7SNXDsKWOqPgqqOd5xocmrFQGFTuk+4RnLcPkj6VTOFn13sEcjwefvP9JWIUV5+xxRdP72VhwY3iotCzlbBwnRTr8PzMH0WmnTIuFJGTSoESaqhQkX2Oxey1XnTnfBB86rYOcQ4DyfF4SDFfiP1P8BT2iH+PjZPDu/J+O2YCGrzg/Ag4Pdwgcomh+PjLBk1Ja7sP+vxqt3p10c3lUtOHe0jefQZ+vQ9n24Bv8wHuQVPl2FupMIif8mBaa72/uElbz+M054nOUFiaQrpVg1O2LCpSBVPFLdKoNNWc5lm+qsZv7munywIf8t1qZ4HB+P0rAe2Dy76uNDW15lSTEIZ7j6fI/L0KczGMJnQC/J1+ciMuU5kqQJ35dw4gZLkAIzibdsH1gybIPsICiWbe1Unr+Hgmu6qLzgh7RiCbV8RM2LratgRNNDBA1F/AYSyyjQNaCUi/685SB5RllDIss6aLi+6K/K52DNnFM8R00k78P8gxlSgUFrQw0HQGQoFxKRbUJNARdok0rnBjFxbjWvolbvG4KfkggyjDruBSNvo0SniMHDmDFm3RrEpXO+YVrvjlBor8He4Dcc5+4WjQTOeZYRUni/VDitOaSfd0j/TX3qD5aWm66N3BQe8a2XQDKMQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199015)(36840700001)(46966006)(40470700004)(5660300002)(316002)(40460700003)(36756003)(6916009)(54906003)(81166007)(966005)(336012)(356005)(426003)(2616005)(41300700001)(83380400001)(82310400005)(36860700001)(82740400003)(7696005)(186003)(6666004)(40480700001)(47076005)(86362001)(8936002)(8676002)(478600001)(26005)(2906002)(4326008)(70586007)(70206006)(16526019)(1076003)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 17:36:22.3927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48f632c0-fff9-46cc-f577-08dad7b0646d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6805 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Smita Koralahalli Move MCA_ADDR[ErrorAddr] extraction into a separate helper function. This will be further refactored to support extended ErrorAddr bits in MCA_ADDR in newer AMD CPUs. [ bp: Massage. ] Signed-off-by: Smita Koralahalli Signed-off-by: Borislav Petkov Reviewed-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20220412154038.261750-2-Smita.KoralahalliChannabasappa@amd.com v2: No change. v3: Rebased on the latest tip tree. No functional changes. v4: Commit description change to be void of the patch linearity. v5: Extract entire function including comments. Define smca_extract_err_addr() in mce/internal.h v6: No functional change. Removed old link. arch/x86/kernel/cpu/mce/amd.c | 10 +--------- arch/x86/kernel/cpu/mce/core.c | 10 +--------- arch/x86/kernel/cpu/mce/internal.h | 15 +++++++++++++++ 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index b80472a52ad8..85977ca07825 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -740,15 +740,7 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) if (m.status & MCI_STATUS_ADDRV) { m.addr = addr; - /* - * Extract [55:] where lsb is the least significant - * *valid* bit of the address bits. - */ - if (mce_flags.smca) { - u8 lsb = (m.addr >> 56) & 0x3f; - - m.addr &= GENMASK_ULL(55, lsb); - } + smca_extract_err_addr(&m); } if (mce_flags.smca) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 9efd6d010e2d..757cc46298d3 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -633,15 +633,7 @@ static noinstr void mce_read_aux(struct mce *m, int i) m->addr <<= shift; } - /* - * Extract [55:] where lsb is the least significant - * *valid* bit of the address bits. - */ - if (mce_flags.smca) { - u8 lsb = (m->addr >> 56) & 0x3f; - - m->addr &= GENMASK_ULL(55, lsb); - } + smca_extract_err_addr(m); } if (mce_flags.smca) { diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 7e03f5b7f6bd..6dcb94fe0f65 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -189,8 +189,23 @@ extern bool filter_mce(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); + +/* Extract [55:] where lsb is the LS-*valid* bit of the address bits. */ +static __always_inline void smca_extract_err_addr(struct mce *m) +{ + u8 lsb; + + if (!mce_flags.smca) + return; + + lsb = (m->addr >> 56) & 0x3f; + + m->addr &= GENMASK_ULL(55, lsb); +} + #else static inline bool amd_filter_mce(struct mce *m) { return false; } +static inline void smca_extract_err_addr(struct mce *m) { } #endif #ifdef CONFIG_X86_ANCIENT_MCE From patchwork Tue Dec 6 17:36:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13066196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 320FCC4708C for ; Tue, 6 Dec 2022 17:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233661AbiLFRhV (ORCPT ); Tue, 6 Dec 2022 12:37:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235620AbiLFRgp (ORCPT ); Tue, 6 Dec 2022 12:36:45 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C562C3C6D7; Tue, 6 Dec 2022 09:36:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RbuDN7r5zgL2zWxcQHFahtriwqxVT9xCISP2nTi29WPqe9CEja1Dz4VyflJg1L89c8bV6B46F0Et4aLTYnE1/fHWBxQaO0ogSyUtPsYPCiF1TkgqSTDahyUOdds72oH7GLIAPh9hx1ZqmAUAIvhwVNAUSWODCINwrsnoP4fkRka5fLzvHCRzgoVdl+UtjF1JoxyJLMuqltZ9ek9aVKVHMjhYS4EPg/Cx7069XNwZhc+1xVITm8cXfMM/C4AnhEk+HCZBACeaSQ6A35C/QWyxcCWsChO+zcbWke8On7nnqAh/ZgfyF8gWR8rV1Jt0rwElfJLWzbKZnvP5iXHcPu9dLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=peZArhzZiIuSW/W7Oskw9Y9ta5KlclwJewQT4DBQuF8=; b=FVHuznbgwCWI26hwFcXvUrpdph8IG/lPxLVKyo1x6zEBda0x9Y9L5qzsTYsPNRBcHBIjYiIEC5o9vqPD1KL6pIhj1Svcrl1r4K0YSLysyFhaDmAqUoKTTXorbXjp+O2QmL7aoNNlKqEuxMfAjbdsqlR4Rq2phPQWPscTRkWicpE6IMevEq2geW8z+yJO3to5UMiwMHxzQMcYFpFGWPFWH7VLoAEMryOn3M1NQrCF9uFBU0I/mFzH+8Y7Ma4aGCCkT64X2eIMchSGFhs5JHsGDU/kWlha7SkLnu7PraPY4n+PQdAfbh9uFSYsZ5hIelhNjFSs2Kz3n8rPihybNpo4QA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=peZArhzZiIuSW/W7Oskw9Y9ta5KlclwJewQT4DBQuF8=; b=t7kILgLzs6ycEbCgCnGSPmC46cUjDoiB6Kndo4G8MugdJ6sAT4Nhw9H7uA27efQxBKApu/1laqm5Ght95vtr1H0clePfLsqKCMm5MdNeO2RvyH+ITw+a0h7StPj5s15CnBB653DwsueyUdudcacfWdb8xCLmaEnSnv1E2QGDPe8= Received: from MW4PR04CA0233.namprd04.prod.outlook.com (2603:10b6:303:87::28) by IA1PR12MB6330.namprd12.prod.outlook.com (2603:10b6:208:3e4::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.21; Tue, 6 Dec 2022 17:36:24 +0000 Received: from CO1NAM11FT032.eop-nam11.prod.protection.outlook.com (2603:10b6:303:87:cafe::50) by MW4PR04CA0233.outlook.office365.com (2603:10b6:303:87::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT032.mail.protection.outlook.com (10.13.174.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5880.14 via Frontend Transport; Tue, 6 Dec 2022 17:36:23 +0000 Received: from titanite-35bahost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Dec 2022 11:36:19 -0600 From: Yazen Ghannam To: CC: , , , , Yazen Ghannam Subject: [PATCH v6 4/4] x86/mce: Add support for Extended Physical Address MCA changes Date: Tue, 6 Dec 2022 11:36:07 -0600 Message-ID: <20221206173607.1185907-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206173607.1185907-1-yazen.ghannam@amd.com> References: <20221206173607.1185907-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT032:EE_|IA1PR12MB6330:EE_ X-MS-Office365-Filtering-Correlation-Id: 80b3b745-d666-4c11-1289-08dad7b06510 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dTdhXGNawvjZ4sknIYZR0JEnLDS1TIfclmmZ5d6JxXuCxlZHMePSt44pSbMp/mq2Qu9Z19pXhYksfqHFpkno538j0T4SYHGFw1DHeeUJedh5+nz7Vx9NzOGFaRSSnBqjKx4nNOiNbr7ou9U6taw7nRXGI5KTHJqxeGtBlT3D9qwcG57uWO3otTQ12CLOV+4f6bAgI3OvTYgzFKgUjp4G+zvkhJw+5Y2vKDd0ekaPcNit09Gr7rc+0PCUciA+X0TcGr7eS9JkQJq+QufwNW5FOhzJG3vbWYL8v3zAUPjaXJYw0oPoPSd2TTX08IcKupQJcsBUExPK6mpjDtFthKgwHic0aqVkyoDVhW/7reryPgmhjG3y2oK5xtUShkdpvTHJIOAH87RZyGn+bSYXfhjK7ZOXBbOdBHxdNwzHrfZ53o9/4rbbjM8gbTDgnPUY+L0nU832HhSWifamD5CHXwaPhLVeOtJalg7jUrgjoH0/547KnQmC6zzGTD+Edy3DWB63Gn9ELQ29Z9l+MssAP38MhcYGKNDBApj9j+kkihk2uqpGtqCL9QFM2NUHZw1LXZg+d0T471oWiHBSAFMGPO32pbGDQjoxrCJITjsJKbc7zqVCW8BWaTDox2aqsJFlvOQT6xDfhSo80hvpizTnX7Qfws6BJZI2ljHMCouMQ2Ao3t/635net9VaRiKJeMiooMe33kDDPd1+9B5IWVbYFbxxfq57FBoZQYW/sqjrv72z2d4Xhn8YAN7F0hnFP2abgjxR0ntqE+tv8cOqorPG42ffsQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199015)(46966006)(36840700001)(40470700004)(36860700001)(83380400001)(86362001)(36756003)(44832011)(47076005)(426003)(966005)(82740400003)(41300700001)(40460700003)(2906002)(54906003)(186003)(16526019)(5660300002)(40480700001)(4326008)(7696005)(1076003)(336012)(6666004)(26005)(82310400005)(8936002)(316002)(478600001)(2616005)(6916009)(8676002)(70586007)(70206006)(356005)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 17:36:23.4552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80b3b745-d666-4c11-1289-08dad7b06510 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6330 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Smita Koralahalli Newer AMD CPUs support more physical address bits. That is the MCA_ADDR registers on Scalable MCA systems contain the ErrorAddr in bits [56:0] instead of [55:0]. Hence the existing LSB field from bits [61:56] in MCA_ADDR must be moved around to accommodate the larger ErrorAddr size. MCA_CONFIG[McaLsbInStatusSupported] indicates this change. If set, the LSB field will be found in MCA_STATUS rather than MCA_ADDR. Each logical CPU has unique MCA bank in hardware and is not shared with other logical CPUs. Additionally on SMCA systems, each feature bit may be different for each bank within same logical CPU. Check for MCA_CONFIG[McaLsbInStatusSupported] for each MCA bank and for each CPU. Additionally, all MCA banks do not support maximum ErrorAddr bits in MCA_ADDR. Some banks might support fewer bits but the remaining bits are marked as reserved. [Yazen: Rebased and fixed up formatting.] Signed-off-by: Smita Koralahalli Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20220412154038.261750-3-Smita.KoralahalliChannabasappa@amd.com v2: Declared lsb_in_status in existing mce_bank[] struct. Moved struct mce_bank[] declaration from core.c -> internal.h v3: Rebased on the latest tip tree. No functional changes. v4: No change. v5: Extend comment for smca_extract_err_addr if AddrLsb is found in MCA_STATUS registers. v6: Rebase and fix up formatting. arch/x86/kernel/cpu/mce/amd.c | 2 ++ arch/x86/kernel/cpu/mce/core.c | 8 +------- arch/x86/kernel/cpu/mce/internal.h | 31 +++++++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 85977ca07825..d4ec9b3481b8 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -306,6 +306,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) if ((low & BIT(5)) && !((high >> 5) & 0x3)) high |= BIT(5); + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); + wrmsr(smca_config, low, high); } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 757cc46298d3..8b67e0284564 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -67,13 +67,7 @@ DEFINE_PER_CPU(unsigned, mce_exception_count); DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); -struct mce_bank { - u64 ctl; /* subevents to enable */ - - __u64 init : 1, /* initialise bank? */ - __reserved_1 : 63; -}; -static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); +DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); #define ATTR_LEN 16 /* One object for each MCE bank, shared by all CPUs */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 6dcb94fe0f65..867bcf9ee424 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -177,6 +177,24 @@ struct mce_vendor_flags { extern struct mce_vendor_flags mce_flags; +struct mce_bank { + /* subevents to enable */ + u64 ctl; + + /* initialise bank? */ + __u64 init : 1, + + /* + * (AMD) MCA_CONFIG[McaLsbInStatusSupported]: This bit indicates + * the LSB field is found in MCA_STATUS, when set. + */ + lsb_in_status : 1, + + __reserved_1 : 62; +}; + +DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); + enum mca_msr { MCA_CTL, MCA_STATUS, @@ -190,7 +208,10 @@ extern bool filter_mce(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); -/* Extract [55:] where lsb is the LS-*valid* bit of the address bits. */ +/* + * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits + * [56:0], else in bits [55:0] of MCA_ADDR. + */ static __always_inline void smca_extract_err_addr(struct mce *m) { u8 lsb; @@ -198,6 +219,14 @@ static __always_inline void smca_extract_err_addr(struct mce *m) if (!mce_flags.smca) return; + if (this_cpu_ptr(mce_banks_array)[m->bank].lsb_in_status) { + lsb = (m->status >> 24) & 0x3f; + + m->addr &= GENMASK_ULL(56, lsb); + + return; + } + lsb = (m->addr >> 56) & 0x3f; m->addr &= GENMASK_ULL(55, lsb);