From patchwork Wed Dec 7 13:59:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDBA3C352A1 for ; Wed, 7 Dec 2022 14:00:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230192AbiLGOAK (ORCPT ); Wed, 7 Dec 2022 09:00:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229918AbiLGN7n (ORCPT ); Wed, 7 Dec 2022 08:59:43 -0500 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 634705C0E0 for ; Wed, 7 Dec 2022 05:59:42 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id 124so17553596pfy.0 for ; Wed, 07 Dec 2022 05:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nbt/wWAyXr8PXcpioECD5vFFYMiQG8G3AvxtqAGhEMs=; b=kFfZArHTfDZyg80wIAXF2jXhRpajwGRdSNrIM3HfbngbOS0QtYcZPhbpe5uywZzdZH eLlbtPhDElNZb29dTOLVwJNEzDn30mD3CXEIsZC1EqXA7i4TtJEXPnRNU9X8C3UG0fKo KcSbcpLX7VnuZANz8Rgq16oceq0ru5Utg4qYw4uQ3nYv3iefE53We/AJ4t+7fHjE5BE2 PGUVRG8oikyKil9hkWrvppK+FobpOF6g9wGO0xzvgulFp4SpAZ8v+N1EuhVcS+YPNfkX YE3gQ5SGN1O8QrWsZkLUlL2+on8lIO3jvDSHWU2o9l6gqXAFf5z1edVF5e4BwwNyiGlD vgpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nbt/wWAyXr8PXcpioECD5vFFYMiQG8G3AvxtqAGhEMs=; b=a+a/mG+8ffW1YvwOddLij0zHIp2lA3j9kGsqZJBrNb3OlhINQKv1+09OmLGj99LTid K6NdvAArZ8vp8TW+rfNMHgOMp6nSibBQ+JD+r2IsRHKmx3kNuOCtrZ2ooqqHbm0DrMas kMUlncvOGJHk6CbtfHXM1yF1RaBP3UJkQ1vL0aKOsK8wMAHofjkdDrCvBTU6YWrhcVEo AvfO7EiK6vMT4ueuXiUfD/TVbSzxcoY2sXjn0jExpd8N6ITle9R65uh+FqnEMTTXdp2K LQ7d6mR3jsUgVPB2H+duaRYFZCGthvzUZCS9ZpbBKUOQ6EWqvDvj85Mfg0gOo0zoEcfA FLJA== X-Gm-Message-State: ANoB5pnpwmqKrPMaMRN7xcrAef114K4koVfjStbtwcIsGxGVNjb7x/uG eJ3J0kpqwQemUyoGHdqfeLQo X-Google-Smtp-Source: AA0mqf4QQLyq9qg7F06RacynLG0Ato69wyZRZbPYGStTm+etW2JDllqAdNf2n23oFnUs7Rv+XpRwpg== X-Received: by 2002:a05:6a00:2883:b0:572:7b49:4f47 with SMTP id ch3-20020a056a00288300b005727b494f47mr76693326pfb.16.1670421581852; Wed, 07 Dec 2022 05:59:41 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.05.59.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 05:59:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 01/12] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Wed, 7 Dec 2022 19:29:10 +0530 Message-Id: <20221207135922.314827-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Signed-off-by: Manivannan Sadhasivam Acked-by: Sai Prakash Ranjan --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From patchwork Wed Dec 7 13:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CF70C63705 for ; Wed, 7 Dec 2022 14:00:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230257AbiLGOAS (ORCPT ); Wed, 7 Dec 2022 09:00:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230218AbiLGN7t (ORCPT ); Wed, 7 Dec 2022 08:59:49 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 761E15C75B for ; Wed, 7 Dec 2022 05:59:48 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id y17so17105707plp.3 for ; Wed, 07 Dec 2022 05:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vwHmJ0i8eRrdJL4Dl+R0aoA35/USIsHe1f5AGZFuBf8=; b=OD+cAweOssXB7azBKYQhL+0oMitp8X6VJm/J895F1RNtF5D7DB1DvZ5FPUk7WhE8rw isXLpinkr3G7y9cKcfV3FnVjIDieOZatDAOcVxyNQ/vwXiL23F/naOEvoVsgsgG9P8mJ GpDJEYXA4NF6NoPM0+ueSkwmAgMnHOX//uHCAHEg/YNYNOAFmpsEwygOVZ5ovSLVKArw i9yqbZ9pGodF0R+JWSoyxYQB+cwRwNq9HHY0ejgPlBCDZB+ZAXwn0lD1Ajq33IPwBAm6 pHeHa4+QnZ1kMCk533DbWJILyP2X2/MlBW3bFWfjJ4tjwc9fTYTN65ZEChSzaHG8udnU cZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vwHmJ0i8eRrdJL4Dl+R0aoA35/USIsHe1f5AGZFuBf8=; b=nA9nvA5r0qWpqYOE32yAPdfb6ORHfGZctMaEUL+xWTWf634hZu2my/E6ANZyIeZHhl rhxUlC6XrejO2ZBXXHj9MpxeEaoBLRO64pfIU5FoN3323rCYQPjI+r2Ak6UTzoqSk8Zg EsYndivhV6RJNrv+1kt8MBII1gkVR5oHOl2qGe2jGUZ+JrUOoIaWiSVaMAw+y1ygeEed bdUNUkE/MMvph7eoo6ub5PjfKAp1PDHXplSSTst7NZCxxgJVllDU4prFjmtn7JQ1QxGu kHObykY8qKojQuFhBZTQIfgeYSuvMMnN52LW2c4BuLEknrFIrX/91O/oL2DstWiO0IhT p7+w== X-Gm-Message-State: ANoB5ple5TWPOxJWiTN7cwfILYGT0UKVQHl72GqK517OVUsDIHSCnR0c 6olj9DexNVCkNGDyUmsjHes1 X-Google-Smtp-Source: AA0mqf6NdZEB+vu0KzJADmdPGIY1PLQc10iKrjmXLFRFsLnXOzvyvN7SngE59U2WWlLhLkXXNN7N3A== X-Received: by 2002:a17:902:e005:b0:189:c62e:ac2f with SMTP id o5-20020a170902e00500b00189c62eac2fmr21071383plo.144.1670421587941; Wed, 07 Dec 2022 05:59:47 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.05.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 05:59:47 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 02/12] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Wed, 7 Dec 2022 19:29:11 +0530 Message-Id: <20221207135922.314827-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Register regions of the LLCC banks are located at separate addresses. Currently, the binding just lists the LLCC0 base address and specifies the size to cover all banks. This is not the correct approach since, there are holes and other registers located in between. So let's specify the base address of each LLCC bank. It should be noted that the bank count differs for each SoC, so that also needs to be taken into account in the binding. Cc: # 4.19 Fixes: 7e5700ae64f6 ("dt-bindings: Documentation for qcom, llcc") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..7f694baa017c 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From patchwork Wed Dec 7 13:59:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9374AC63706 for ; Wed, 7 Dec 2022 14:00:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230241AbiLGOAb (ORCPT ); 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Wed, 07 Dec 2022 05:59:53 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 03/12] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:12 +0530 Message-Id: <20221207135922.314827-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.4 Fixes: ba0411ddd133 ("arm64: dts: sdm845: Add device node for Last level cache controller") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..e1c0d9faf46e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,11 @@ uart15: serial@a9c000 { llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 7 13:59:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DEDDC63708 for ; Wed, 7 Dec 2022 14:00:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbiLGOAg (ORCPT ); Wed, 7 Dec 2022 09:00:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230136AbiLGOAF (ORCPT ); Wed, 7 Dec 2022 09:00:05 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E675311462 for ; Wed, 7 Dec 2022 06:00:00 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id y4so17104570plb.2 for ; Wed, 07 Dec 2022 06:00:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iUBfene/cnQwgTF0aG4S0NjKk1KSg5LGCh8ripuPt50=; b=H8wT7XpkqvaHjQ6Po/goMKj6V6jL/8Ey8Hf+GqZvdwrHx75UStaopLvvwyARJc7qO5 5UoJNpiMgUPfBpM1ZyE6UT7VLrFXYXeoGRckbpFv5xvbBUxLlTvOj8sqS5KRCwaQ1Fzi qztmo5Z4rB7+/QyLfJCSJIa1uG7AvVCX3XtsZI2rC5nfb6nvLpRJVPky+FSR204kiFNF BhDV1+OswALIVZavXenT6tiQ01rKxTbsg/oMCnlYCKLWTf2TB5yWAC2oFsw/AWa0/HNF z0gAf7S5LzBhpitYnxVtjOdLT50vK76PfjLoQfcJFur8TtrtNyauTbmHDx3nnT3sDQXT x+vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iUBfene/cnQwgTF0aG4S0NjKk1KSg5LGCh8ripuPt50=; b=pscrnS0XqUWHRm9X4MXeFVoIIR2v3FElbG65yWd5a4vIWLpZ3O46QSxVuqNzdz0gtL CmHcuzOh5xDF3zU86NnPTYZOlnAing859OR2nuzwumS/qJEqLfErcQ2TLdQosr9f+hsv c/Kw95RSnxvKV0BfDTKfF3ZQGM/JHgHN544eMw9SuDEpVX7eqjPGUWUlfVx67m4/1WK/ b0jqNT/aGEsNtyDkJUNvkxT6e4HpCXGCLoPmg1sy1iAky2LoEOw/hdLioUjNHoxRjWPr MxGhc96ZLrBsfuf+v4yXHT9SLp4tBJPXL/4bx+Gzq3DiizACfRTq7RjWccoXI/NfsV+W bgDg== X-Gm-Message-State: ANoB5pnLcwm4fEfKNqDx1u7LXyZKDLb7ldUwBENTJaz/Ustx3neK/uXI hoHUwoaXQLjxZDONr6ODnipI X-Google-Smtp-Source: AA0mqf6BwCJ/ScoZvW+2XcQjX3QSYrL5niNqC+Kve9LZHguQz+jHID3tQYcmqCpRfB+QgrDtXk0OYg== X-Received: by 2002:a17:90a:3da1:b0:219:61e5:4994 with SMTP id i30-20020a17090a3da100b0021961e54994mr37329693pjc.213.1670421600398; Wed, 07 Dec 2022 06:00:00 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.05.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 05:59:59 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 04/12] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:13 +0530 Message-Id: <20221207135922.314827-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Cc: # 5.6 Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..f861f692c9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 7 13:59:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23A8FC63707 for ; Wed, 7 Dec 2022 14:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230023AbiLGOAo (ORCPT ); Wed, 7 Dec 2022 09:00:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229918AbiLGOAL (ORCPT ); Wed, 7 Dec 2022 09:00:11 -0500 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 192015C0E6 for ; Wed, 7 Dec 2022 06:00:07 -0800 (PST) Received: by mail-pg1-x52b.google.com with SMTP id h33so16435108pgm.9 for ; Wed, 07 Dec 2022 06:00:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5n0Bzk4oRcwoQ/X+7mKiinSvd0WlsPB4Sg7t77MHfrg=; b=bDfohewvK322PkyoaoeVx5utUGw02oRSdwD7E5T8JwmGQGI+eGv/eQmEAHEeI4vGL5 hZP4IorHbJ7MPDJkhHCOylqWDMSvmVSbLnJFLDTIEgY332WwAzDu189nbcYWtp+S4rNi z9STzDjpH/T0zBBOuHixzfS0FAqQNeMFZQf32hyw3yJhIIa909ZYhOuXKdNHbdafKcCl x4pcKDcJrV4bKkKB5rVESJiPcJMHfFC9n+KwxTy5Um5J2DkyeLigZnE0kjnzUawwxsDi JpmdU2q2fGPdoQvAiatfiJlIBZ+xxYPaPQ/CgfmUda81/rErjmpxirMtZgJtL6fg1qta Tq1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5n0Bzk4oRcwoQ/X+7mKiinSvd0WlsPB4Sg7t77MHfrg=; b=42w8mBBsQJX1FhvazjcWUrYEPR61wClHcsRRrXmtohl5DJ4xZ3LcwZR6ZYGHQcZ3SP cRIA98OgFlVnjLwwx5YiqikAt4TtXqFfVvIT+IETOso3S/9BrZDPpJNQmRKQo1S1nCjx OZ+cAuZfVXijZOM2Ge3SsmJdgPm5vfo02hatXILoQbALSJ+NXGASR4g7vbkQgc0mdJu0 v+DEeA9TD9RIBj/iH5rxAYjAywStGbCjf0dqrJFHTEKfV92fLztltU6RURQKcrmWKutM 3F3V9e7drL5fIBNoPmRaso89Q9bSV06JSPIWZ5Yh6HV0UTcHfq0OOdNSuYdcuY7crpeT WsJw== X-Gm-Message-State: ANoB5pmLtHPo+gAccCL9BGQo/Fy1Av4EN5YlRegv3OlRPrXdiq4R2/rJ on/96izjmY+STaszWmfD85HQ X-Google-Smtp-Source: AA0mqf7B1Q/KziWYaacazkXY2TuYKm/263tGdPPAdJ/GFN2M21J5u/BfEWI8V+2vKrdEBpBV0oyxOQ== X-Received: by 2002:a63:5b4d:0:b0:478:ae0a:bd86 with SMTP id l13-20020a635b4d000000b00478ae0abd86mr15223904pgm.239.1670421606382; Wed, 07 Dec 2022 06:00:06 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:05 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 05/12] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:14 +0530 Message-Id: <20221207135922.314827-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Cc: # 5.13 Fixes: 0392968dbe09 ("arm64: dts: qcom: sc7280: Add device tree node for LLCC") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..6c6eb6f4f650 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 7 13:59:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAAE7C4708E for ; Wed, 7 Dec 2022 14:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229603AbiLGOAw (ORCPT ); Wed, 7 Dec 2022 09:00:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230262AbiLGOAU (ORCPT ); Wed, 7 Dec 2022 09:00:20 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B0ADC4E for ; Wed, 7 Dec 2022 06:00:14 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so1527907pjj.2 for ; Wed, 07 Dec 2022 06:00:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jGefmKMEXqWoGu7xIFjnC5m/g9TolIorwDYvhcWeeRg=; b=oJK7a30Mr2LkFqooyVg0pm63JlyQOjxUpyH9huMRz1fbq5VA3YR5KjoaoRdBcl+i88 A7DAAvJDi78hXvVmHf1AWOrZ7jAOnfomvc+ch7/fUd8RHbzmSkrxt7KeTpXaTV9VJ0a+ lnwhKxRY01WNGsIrusLM2xijeXHZvrMbO2fRUeWZCMTc1ewPPzxadUdtIZO81hQ5swr0 21QVZveUsYIfw3yrvmKZVec0rRAu1/18evngrlhb2Er0TOq8Yb82F726ctjooUwYIcVx c5LI0N+WmGnJd5swAWQbcaG/MY3QZSTyQT8gw9ezKxkVckL5+bT5hcbm73WTozlUGRnN ASTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jGefmKMEXqWoGu7xIFjnC5m/g9TolIorwDYvhcWeeRg=; b=WYL6aN2kEXenJYOCqLjyZBnvRd94jyqohuQPfX5ogzZaz8LAD7tcSAkDOYdMXQ+lnq w8cfHUG8NSYs6iVgKspYA/jFj4GLgKh7uUIgwlPavHzl4BBjzxZhouiEF2nL0gyZvhd8 DAjBhwFizkJGi9p+pRTNuwwSMy82e6PWPpkZiMb2uRH8JLSlB2UEnXYoCD95UcsfpfjG 5ccpVOHyD1Eh0oGW3GHanDbP/A5JM9xcCnudEFUiGMdaUU3Mxi4B+9vU9Nrgu0RfbFuP RgomTVBI65Jjm98lyduuHGQsgGdvLAzsytrXydP2lp789rcMSNcRLLeGNw08L/RWtPt+ +Q5w== X-Gm-Message-State: ANoB5pk7OBkqqKM4Pag5L05Zmg4fvwXDh4MSAVjMlLO8EFgnlspTU8nE fLb6ngi0okBW9gZyNZONqQ5R X-Google-Smtp-Source: AA0mqf4zcdu1I6R57Zdsr7a6QFCdrc4ms6nXqRhPXfMXqpJqJsAtmwTd57t6p5rBlswXOWu2573K6w== X-Received: by 2002:a17:903:181:b0:189:8f11:f2f with SMTP id z1-20020a170903018100b001898f110f2fmr48579907plg.133.1670421612815; Wed, 07 Dec 2022 06:00:12 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 06/12] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:15 +0530 Message-Id: <20221207135922.314827-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 6.0 Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..0510a5d510e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,14 @@ opp-6 { system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 7 13:59:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26A26C63705 for ; Wed, 7 Dec 2022 14:01:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230028AbiLGOA5 (ORCPT ); Wed, 7 Dec 2022 09:00:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230227AbiLGOAW (ORCPT ); Wed, 7 Dec 2022 09:00:22 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A81E5C74B for ; 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Wed, 07 Dec 2022 06:00:18 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 07/12] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:16 +0530 Message-Id: <20221207135922.314827-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.11 Fixes: bb1f7cf68a2d ("arm64: dts: qcom: sm8150: Add LLC support for sm8150") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..7fd2291b2638 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,11 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 7 13:59:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 508D9C352A1 for ; Wed, 7 Dec 2022 14:01:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230246AbiLGOBW (ORCPT ); Wed, 7 Dec 2022 09:01:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230267AbiLGOAf (ORCPT ); Wed, 7 Dec 2022 09:00:35 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 970ED5CD2A for ; Wed, 7 Dec 2022 06:00:26 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id s196so16475650pgs.3 for ; Wed, 07 Dec 2022 06:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m9wB8HfZl3VNPDfTiqbYvNGJ+C+gB7rjqwIL9QWVnZY=; b=bGJ7XILZ3JHnO065vPE2FpcT5z5uAqEEOiqARKZHZKX1ckjPjdgSBW7/EndyCXEewr Q49oC/fEuNxkoKmzhr4ydHYcnY/AnyBBqMg6hHvdJx6UNHEnOK6ztT3ZsF10V95wIT2g kHVfZoBPYd6qYAEOulgTgIkd/uCLB8iNs3zR05aOc8sx1Agb+jxQGS1HhfcyNb27QmQ2 NEQ7/ND6zf+R1aE1JkeEx0SBmyDRR2nGxpla/+RU8aJwD2J98sCU0a/gdL/W222S04ZL p4won3uXWRqZ7DrpQdS5Ftrql3RkrA06ZQGB8yP0Tsf5iX2zC7wyjo667mA/AlZydMjc Ui6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m9wB8HfZl3VNPDfTiqbYvNGJ+C+gB7rjqwIL9QWVnZY=; b=p1+vy7q62XzXglBp0PN2+LY6Xnpzd8dDKzgyPQn/uZfG8ZzXWK3520L7gzxfoQKVKj q5wzE6mjiIzjEisXmmGQ0jsWoxGnJyg7a9aqCgdV7GHe1C6fi8ZXu3Ble+8VVUbIYnT7 Hw7JpbnDq4yzuVXn4j2UnngZys77EIludNy2Y3DEWMfPeTfgkpljFgGlgsseYTvdf7yb fWxVxqGagN2/SwD5nVyiaolkU9rkAZahwNjfu8SjIIfGqbfrd1KfvcXPP76+VS5MJgp4 SNr7kaZyKcCdRWBAS4RC7xlAHDqoNvWU29ge4vD+G+u6huM1w7eJX5KkT++fh0ljuPB5 fJVA== X-Gm-Message-State: ANoB5pmoaFNLq4V+0ex85CyiaE5ef9xLE4EYUq3kBqy1m0Nctrlw6zgm 3vbK4a7oqlzdeVpx0H96qkqw X-Google-Smtp-Source: AA0mqf4JhLpEzJBzUDoRUDShe0fazOM5Kybl/zUECelo4UCHl7ghB2yXwXg+IkCFhIl8itdGB0URaQ== X-Received: by 2002:a05:6a00:1ad2:b0:576:f761:d381 with SMTP id f18-20020a056a001ad200b00576f761d381mr14371016pfv.59.1670421626221; Wed, 07 Dec 2022 06:00:26 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:25 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 08/12] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:17 +0530 Message-Id: <20221207135922.314827-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.12 Fixes: 0085a33a25cc ("arm64: dts: qcom: sm8250: Add support for LLCC block") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..d1b65fb3f3f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,11 @@ usb_1_dwc3: usb@a600000 { system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { From patchwork Wed Dec 7 13:59:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3750C4708E for ; Wed, 7 Dec 2022 14:01:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229848AbiLGOB3 (ORCPT ); Wed, 7 Dec 2022 09:01:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229872AbiLGOAo (ORCPT ); Wed, 7 Dec 2022 09:00:44 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B5ED5CD3C for ; Wed, 7 Dec 2022 06:00:33 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id w15-20020a17090a380f00b0021873113cb4so1737226pjb.0 for ; Wed, 07 Dec 2022 06:00:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vfunYPN7pQzIq/aXuuYsh9BqM9fjFphrjnxLDwW5HDM=; b=P/D+hvsSzs5/Z2g+hUwoSTGiCaJQRcrqbPrEN3djw3epYnLFlbXktZajYPahX5bTnY Ro130UAGILR62rxsSXDZ7b5kM6S6yvNxWGoq6LVWl79Cajn0bPQT8OKkjger2zTNuBdS k0FP8H1x1NWDJIX+j2/Biaw23GI/3/Z5n3tGFa6Ukd3rUkE8MuO8K6pin/D18dIXOuxo jc28OHhgT2kWkqoZaoSe0TbvkPulj4hBNI7Vwmuks4Bn5Psj/0oIWEUx/Vf0iCkiKRUP bSDza/ogKT+CSehmv3ULvp/XU5wOSlCTAYvUxvXzUg+IC8mMa88hlA8wg5d2pdRPwa+K nsQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vfunYPN7pQzIq/aXuuYsh9BqM9fjFphrjnxLDwW5HDM=; b=mwdxA2pBvfy6+nvoseVlpJN+0p+6uaq1nX0qZyxgl8F+GwCeE05lJiBcqt3Dz61Gxu Y/YN3m05R6ESaKum/8mlvulm21DJ25s0vDjdNGoxubG+L5pV7hLSnNOrTZ7J/CdLCHhZ RfxGzhiU+YolAWYiVx0Rp9FXFi8elcdb8kwbbNcVXAtixa6xePlBY+dh5B1MY28ByR2C DOyiQsiPxsjQPDP8/OK3T2YOA5hi0Y2ZqXMfKJH6h+9PVcQPsDyLErlcXaE1uFZm//O/ vlux1VCDY+sEbe1+dvigbjv4NBQo46IXwzFXFrFJr8E5cS9g7xK6pgfxDViMWu0F+qsy +CSw== X-Gm-Message-State: ANoB5pnTXfRwsfdyZnQWqCVNXWDy1/MZNTtF7Vtb+q1tX+1f+OopXUiz hO/nCQfdzMkmRlq5muk8299+ X-Google-Smtp-Source: AA0mqf6e6lJbaOA8uQds3om0jADfzRMHAvMsP7NLMRU5y1QZh9n7PUcvTRC/GPic/srqltROqfBZrA== X-Received: by 2002:a17:902:ed94:b0:189:66dc:4af4 with SMTP id e20-20020a170902ed9400b0018966dc4af4mr59310310plj.149.1670421632460; Wed, 07 Dec 2022 06:00:32 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:31 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 09/12] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:18 +0530 Message-Id: <20221207135922.314827-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.17 Fixes: 9ac8999e8d6c ("arm64: dts: qcom: sm8350: Add LLCC node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..836732d16635 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,11 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_1: usb@a6f8800 { From patchwork Wed Dec 7 13:59:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58442C4708E for ; Wed, 7 Dec 2022 14:02:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbiLGOCa (ORCPT ); Wed, 7 Dec 2022 09:02:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbiLGOBZ (ORCPT ); Wed, 7 Dec 2022 09:01:25 -0500 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83D4E5CD20 for ; Wed, 7 Dec 2022 06:00:43 -0800 (PST) Received: by mail-pg1-x531.google.com with SMTP id w37so16457865pga.5 for ; Wed, 07 Dec 2022 06:00:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4HXFRaipNAA/3SVXX4rMylP7rXb8WAB5NgKEFsbHAGk=; b=mIbtkx5ZYYnroshvQ2t9MPgSjjE3QsY4ZeLxclpuzT+W76Iwc3E11RHLejCqci1+D9 9WtB0A54+LWedD3UwQkLkB7LEmqvAY19WypkTGi+TXwbf/fjH/kk4nLeRLs7zVaYUvbA t23Qsx47tB0Fi00bZVv6ftKAJpO+PHeY+S218JUg5vGPFUYP0/ZAfmKzO4vuBt+5nohQ kDZLJJN+R/wPCeKIRBKNg3Z4/aCacZsBCsm2lZSKTbEG+tunELjGU+pfhRlSfAvJqoJj MEBna6VUxY/BmXsUnS8lGe8zjELxJoq3DwXBJkJSvs85ARPApD8fxgKplvqbznD442t4 AedQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4HXFRaipNAA/3SVXX4rMylP7rXb8WAB5NgKEFsbHAGk=; b=PiTMxxo10aHZZ3AIwZ3ChKBzaSKWI67XIuy120IcqxjYoyiWC4pjBI94R31YB90xtU AgNG9DPyLiVLL8TjLDVMntUtlT/KrhmXCjUHLh8o3akitYsm1Tj2SkEj0+1Lc28rvcc9 b5RhHx0YfPw3MI/UglWItVkiNc8or8uXLWDvpd9Ee/jb4HUaXkdSGJh/BATO+quVAYzM oUeH/6WXm7Oi0cOUMdi7HDd7cxUSQdRTOp1B1+67UHchWoYr4nhEsn16FSFMZA8knErf 1fFdgV8BfXKKgkb+etki+hq8HQt4/1QVQKl0yo4o6p6kijgYl897fRES9wIgjWAHQcdN xTEA== X-Gm-Message-State: ANoB5pmYaDDXpAudK4eb7nopobdvJsb52Zg+Nj6WII027Fu7CabSmBc2 ae7h4YzWZBVgj2ATh9Omc5xP X-Google-Smtp-Source: AA0mqf6PkeIpX8wdc7FSgLEftKEzJvmNEAp1iukvNMuqhE5V8GCSkPkULyLzQqbsPZY9MO2mkEQy8w== X-Received: by 2002:a63:eb16:0:b0:477:6fe1:cd6d with SMTP id t22-20020a63eb16000000b004776fe1cd6dmr69810826pgh.334.1670421639019; Wed, 07 Dec 2022 06:00:39 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:38 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 10/12] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:19 +0530 Message-Id: <20221207135922.314827-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Cc: # 5.18 Fixes: 1dc3e50eb680 ("arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..12549a2912c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 7 13:59:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1DDAC352A1 for ; Wed, 7 Dec 2022 14:02:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229562AbiLGOC3 (ORCPT ); Wed, 7 Dec 2022 09:02:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230271AbiLGOB3 (ORCPT ); Wed, 7 Dec 2022 09:01:29 -0500 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8A485D68C for ; Wed, 7 Dec 2022 06:00:45 -0800 (PST) Received: by mail-pf1-x42c.google.com with SMTP id g1so9470630pfk.2 for ; Wed, 07 Dec 2022 06:00:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AGwgSnOhYi02xVu+IbkUS49u1T5vi+3uXVqLwkjF92c=; b=RelowFhh6oDnHAyNKyX5GbA0mViEyG82HTuOCWYZ5qrEcSdJzwUBvwFBBkWMWJVLJS XQ3r67OTKq+d0YJ+zYjUP+DwVXu6cA4OsIXmXxXwuJz0ZYIEj2jbu7bUdy/uIB64TN/B 3wp1Jd1vmyS5dBY19RdVefXiyHrbBtesuuq5FyzuRz0fd3ZAWF+Mbz0rRWgrPWxl2EWt DDesFiVgla6qIu4YzL9mosel0xcmbHZQ4Q913AxLMXeXPl67p9ko9DuQWmDMSrp9yxgt 5kM9BPICjX/IMuGDeziQRWvE5dnp7fZGCifql6pp8otxSixvDtscV77RApqMb76xzJc8 +Kag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AGwgSnOhYi02xVu+IbkUS49u1T5vi+3uXVqLwkjF92c=; b=vGowCf7Z0k6ThnYKkVjybnQxD7I1h5Zk6CHgi253Bnqod1DqQd4DBn/TS3qf3hVUuG MABU9I6hx4qSmqnBmPJsKSMFLICiAvT7mBC1NpmKZ7q0u/nRb2JMFsm1Jp5fkJmmOjfW P+v5aHaQeTXHAwXu7RZv4qDw4kt0vTwPj/58vK33mbVmZxSzAiloJc4WblrDkHLzq4kV NNhjT3T/03/eGChlpXzOxAg9qn6naU8rKZ3wsJWULeUwFAIZYaS7XJpUJTmhHgIg9f0W fVI/WZEh2hTYxqsZxn/NSFCweXlqnkAl1jSZz4lA0POpeUi6iWmpFtM3elxMGAiPsayO e0oQ== X-Gm-Message-State: ANoB5pmz+7HDdUnNKr9pJ1wgSH5K5r68kZ+KA9EzCzSmaUynKSWMCkqX w6eKblXsk4vqPCsn3T2RJvHDdpTKf/kMXDA= X-Google-Smtp-Source: AA0mqf4xthVb9iLjHkSf+QcyPhznIdyUnH2woOTMyd/m/Su3Q10nTYhwPFoFW3QGv3znCqBN5a1TjQ== X-Received: by 2002:a62:ee0f:0:b0:56c:8dbc:f83e with SMTP id e15-20020a62ee0f000000b0056c8dbcf83emr73052440pfi.41.1670421645105; Wed, 07 Dec 2022 06:00:45 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:44 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 11/12] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Wed, 7 Dec 2022 19:29:20 +0530 Message-Id: <20221207135922.314827-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Cc: # 5.16 Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..c7701f5e4af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From patchwork Wed Dec 7 13:59:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13067198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59707C6370C for ; Wed, 7 Dec 2022 14:02:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229918AbiLGOCb (ORCPT ); Wed, 7 Dec 2022 09:02:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230102AbiLGOBz (ORCPT ); Wed, 7 Dec 2022 09:01:55 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 082155E3CA for ; Wed, 7 Dec 2022 06:00:53 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id u15-20020a17090a3fcf00b002191825cf02so1714094pjm.2 for ; Wed, 07 Dec 2022 06:00:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/tmf4FhGP2SUfnQq67BBBvYtBbMtS0YXHrJVypV9j0Y=; b=jJKHCRg2Vybbn81b+bh3LhDDZKfk6Zo4u+chNJ134DR47RDufb6UiGNDlWNKDWAVBn 5YHBNMa8bWOD8MhBE8cEtjcdPqrx39mIauUf5FAAQ+10zcTwvTvmveZ28tMwcKcDt+7C MUjdQufCjZpdPyMEvZW0ISl1mXNlVuKKXK66SlA/wqH8dtxN5GSrFb8AXgV8dHYhBq7P f8cayHyFOYtR+AQ5GNJrkxjTPCMSEwhW1rqy+JPu9wDrBwZFM48e4AdkI/Yb7YYy3ph2 +TRue+hi4xHgBreIskOrLJPuu82H66zLOpfVIReN8YHDXZ07Qj4WPGX5pLU61t3QLX4m ePVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/tmf4FhGP2SUfnQq67BBBvYtBbMtS0YXHrJVypV9j0Y=; b=jQvChi7hWAlZXHKWDyIq1k6cy3Ia0AYx9wp8PttbzmqvJJH7P5BvQQdUJTgM46nozu ifsfzeinPWvIOyJPiAm3hJNLyYe2sbz1POczAlcXonDbXdzAQCLeSWyA+Tvvm0JiQYyO DXbmKVdlr3atRAA6xeglPzyyf7mUQHQeplb+U3RI3233FHElt33tBVPQprCTCrja0P3m 5gIQR+XnKIEaawDEMRyxk4QJ6ID1rAXE3LR4BXiUr2t2IUdglodMsi2Fk10e2HKUXxFX WH89uXWhNZ/ln/iwQdTOxUaIw1oIC5mbRsrg7N5muGoKkSinDBrB3UnaTLPY0/p9jrdy OSrQ== X-Gm-Message-State: ANoB5pnbmahR4GUIWXidQif0N/lJJb7n6pmHD/swJ847TXJuI/ajr8x1 lEdv6lZ8N1DfWArvLk9AIKiM X-Google-Smtp-Source: AA0mqf4DdbseasoYATfDJ7od5fTSrO9ZdSchGfXWVYpuzkqBUxpv6xlPrmwgrzdB0/R3N8B1Nas3Pw== X-Received: by 2002:a17:90a:708a:b0:20a:eaab:137 with SMTP id g10-20020a17090a708a00b0020aeaab0137mr101141295pjk.206.1670421652404; Wed, 07 Dec 2022 06:00:52 -0800 (PST) Received: from localhost.localdomain ([117.216.123.5]) by smtp.gmail.com with ESMTPSA id c18-20020a170902d49200b00186b69157ecsm14720160plg.202.2022.12.07.06.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 06:00:51 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH 12/12] llcc/edac: Fix the base address used for accessing LLCC banks Date: Wed, 7 Dec 2022 19:29:21 +0530 Message-Id: <20221207135922.314827-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> References: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC driver has been using a fixed register offset stride for accessing the CSRs of each LLCC bank. This offset only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. Hence, obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. Cc: # 4.20 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++---- drivers/soc/qcom/llcc-qcom.c | 64 ++++++++++++++++++------------ include/linux/soc/qcom/llcc-qcom.h | 4 +- 3 files changed, 44 insertions(+), 38 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..70bd39a91b89 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmap[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmap[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmap[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmap[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmap[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..7264ac9993e0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,12 +933,46 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + goto err; + } + + cfg = of_device_get_match_data(&pdev->dev); + + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], + &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmap = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmap), GFP_KERNEL); + if (!drv_data->regmap) { + ret = -ENOMEM; goto err; } + drv_data->regmap[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmap[i] = qcom_llcc_init_mmio(pdev, base); + if (IS_ERR(drv_data->regmap[i])) { + ret = PTR_ERR(drv_data->regmap[i]); + kfree(base); + goto err; + } + + kfree(base); + } + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { @@ -947,8 +980,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - cfg = of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +988,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +995,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..4b8bf585f9ba 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmap; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; };