From patchwork Wed Dec 7 23:24:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Collins X-Patchwork-Id: 13067759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3C27C6370A for ; Wed, 7 Dec 2022 23:26:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbiLGX0Q (ORCPT ); Wed, 7 Dec 2022 18:26:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbiLGX0N (ORCPT ); Wed, 7 Dec 2022 18:26:13 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B888988B69; Wed, 7 Dec 2022 15:26:12 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B7MjFm4001443; Wed, 7 Dec 2022 23:26:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=mz/oLDXD5a9DkSIPd5g99uMG+kM+zWR0kKaG8HwnncY=; b=nvHj99n0bLphTZoylmcRU2VdkahroHehPzSSAVSuzBKMyMtoHgOj4kw10m0UGNcqgghd sIsJ8/EC24STXdRr62sS7EGWGechQmoBOLU0cB2cw4RITcaFxJfIDjCU6Zqvfrg2eu65 6ekW0sMErmtek5pH35/oFEhGfOmxMFBCTgsolyv/E8vicAuBGQ3aWBbyVZJwsjUEg5S7 rOKgQrXAJm/zXsMLpoP6HjSXAqPZ8eJGqWGEeG9zoU1dqmX3uJihB/gkMG3sH4hhVww0 xW/Wi7vCjLlFskGtYdozrqUCGRFBF3NvFkIG2DYqLr2TOwOtpHDWO7Thu9eMBAUnN393 9Q== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3majt4aapr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Dec 2022 23:26:03 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2B7NQ2NG029188 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 7 Dec 2022 23:26:02 GMT Received: from hu-collinsd-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 7 Dec 2022 15:26:01 -0800 From: David Collins To: Daniel Lezcano , "Rafael J . Wysocki" , Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson CC: David Collins , Konrad Dybcio , Zhang Rui , , , Subject: [PATCH v3 1/3] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Wed, 7 Dec 2022 15:24:56 -0800 Message-ID: <795bf935ba201519da3d505332d8b7cadecb0435.1670454176.git.quic_collinsd@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UVTULML2Xjz8BE7T6XKPZRT2bwcO3roH X-Proofpoint-ORIG-GUID: UVTULML2Xjz8BE7T6XKPZRT2bwcO3roH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-07_11,2022-12-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 adultscore=0 mlxscore=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212070198 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index be785ab37e53..895a2d7bff02 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -18,6 +19,7 @@ #include "../thermal_core.h" #include "../thermal_hwmon.h" +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -73,6 +75,7 @@ struct qpnp_tm_chip { struct device *dev; struct thermal_zone_device *tz_dev; unsigned int subtype; + unsigned int dig_revision; long temp; unsigned int thresh; unsigned int stage; @@ -224,6 +227,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1]; long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown = false; + bool require_s2_shutdown = false; u8 reg; WARN_ON(!mutex_is_locked(&chip->lock)); @@ -255,9 +259,25 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n"); } + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) { + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (chip->dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + require_s2_shutdown = true; + break; + } + } + skip: reg |= chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !require_s2_shutdown) reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -372,7 +392,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; + u8 type, subtype, dig_major, dig_minor; u32 res; int ret, irq; @@ -428,6 +448,14 @@ static int qpnp_tm_probe(struct platform_device *pdev) return ret; } + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) { + dev_err(&pdev->dev, "could not read dig_minor\n"); + return ret; + } + + chip->dig_revision = (dig_major << 8) | dig_minor; + if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 && subtype != QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", From patchwork Wed Dec 7 23:24:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Collins X-Patchwork-Id: 13067758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B45CC63705 for ; Wed, 7 Dec 2022 23:26:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229685AbiLGX0P (ORCPT ); Wed, 7 Dec 2022 18:26:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbiLGX0O (ORCPT ); Wed, 7 Dec 2022 18:26:14 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 141848930F; Wed, 7 Dec 2022 15:26:13 -0800 (PST) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B7NAWZt008943; Wed, 7 Dec 2022 23:26:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Cgt3fdZmNLERHrjukVY2m0H3nHmNMpuE6vEmF6iAatc=; b=ZFJZl6KQ2ySi7syN/H2LCHNXaYUs+55B+y1GK1LY4Gfo0oYU3oxpJjG7Aa08o6/8DILB P1/jcOYO618SRz59pz7Jzc+r60umT07Fql78JxvL1SNMf0niqAPxkuPiDCIcOxDN9hcO KmtqgVu/nAIv60zIpfRizq6P1WHDPN0yQUzwiN190LiH9w+X6iNjdDkaMQyQn6HEcle4 OYwa3pnrEbMafeIhQgqjeK5GPm4jVEUUusOSuJR0DKMf7dZZCiSTES8/u/1gE9lTJEH6 Ug4cNkQqyeJYcicaNPU6xUWLjbjrXgv+enAEzzECDrLjSoDZyQfe2eX0XVMUVdJTlaJv lA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mahgp2qs1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Dec 2022 23:26:04 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2B7NQ2ZH013780 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 7 Dec 2022 23:26:02 GMT Received: from hu-collinsd-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 7 Dec 2022 15:26:02 -0800 From: David Collins To: Daniel Lezcano , "Rafael J . Wysocki" , Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson CC: David Collins , Konrad Dybcio , Zhang Rui , , , Subject: [PATCH v3 2/3] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Wed, 7 Dec 2022 15:24:57 -0800 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jBWEX_CS0WmyhnuLyWTOKoh-TuI4musO X-Proofpoint-ORIG-GUID: jBWEX_CS0WmyhnuLyWTOKoh-TuI4musO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-07_11,2022-12-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212070198 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual registers to set the threshold temperature for over-temperature stages 1, 2, and 3 instead of a single register to specify a set of thresholds. Signed-off-by: David Collins --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 162 +++++++++++++++++++- 1 file changed, 156 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index 895a2d7bff02..a8b288de6b52 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -26,6 +26,10 @@ #define QPNP_TM_REG_STATUS 0x08 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 +/* TEMP_DAC_* registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 @@ -67,6 +71,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { #define TEMP_STAGE_HYSTERESIS 2000 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the threshold + * for each stage independently. + * TEMP_DAC_STG* = 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] = { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 @@ -87,6 +110,9 @@ struct qpnp_tm_chip { struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + + bool has_temp_dac; + long temp_dac_map[STAGE_COUNT]; }; /* This array maps from GEN2 alarm state to GEN1 alarm stage */ @@ -120,6 +146,13 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) { + if (chip->has_temp_dac) { + if (stage == 0 || stage > STAGE_COUNT) + return 0; + + return chip->temp_dac_map[stage - 1]; + } + if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || stage > STAGE_COUNT) return 0; @@ -221,6 +254,34 @@ static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp) return 0; } +static int qpnp_tm_set_temp_dac_thresh(struct qpnp_tm_chip *chip, int trip, + int temp) +{ + int ret, temp_cfg; + u8 reg; + + if (trip < 0 || trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip = %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp = %d\n", temp); + return -EINVAL; + } + + reg = TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg = TEMP_DAC_REG_TO_TEMP(reg); + + ret = qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_dac_map[trip] = temp_cfg; + + return 0; +} + static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { @@ -308,6 +369,24 @@ static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = { .set_trip_temp = qpnp_tm_set_trip_temp, }; +static int qpnp_tm_set_temp_dac_trip_temp(struct thermal_zone_device *tz, + int trip, int temp) +{ + struct qpnp_tm_chip *chip = tz->devdata; + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_set_temp_dac_thresh(chip, trip, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_sensor_temp_dac_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_set_temp_dac_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -340,6 +419,60 @@ static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip) return THERMAL_TEMP_INVALID; } +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_temp_dac_update_trip_temps(struct qpnp_tm_chip *chip) +{ + const struct thermal_trip *trips; + int ret, ntrips, i; + + ntrips = of_thermal_get_ntrips(chip->tz_dev); + /* Keep hardware defaults if no DT trips are defined. */ + if (ntrips <= 0) + return 0; + + trips = of_thermal_get_trip_points(chip->tz_dev); + if (!trips) + return -EINVAL; + + for (i = 0; i < ntrips; i++) { + if (of_thermal_is_trip_valid(chip->tz_dev, i)) { + ret = qpnp_tm_set_temp_dac_thresh(chip, i, + trips[i].temperature); + if (ret < 0) + return ret; + } + } + + /* Verify that trips are strictly increasing. */ + for (i = 1; i < STAGE_COUNT; i++) { + if (chip->temp_dac_map[i] <= chip->temp_dac_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", + i, chip->temp_dac_map[i], i - 1, + chip->temp_dac_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_temp_dac_init(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg = 0; + + for (i = 0; i < STAGE_COUNT; i++) { + ret = qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_dac_map[i] = TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -372,10 +505,16 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) if (stage) chip->temp = qpnp_tm_decode_temp(chip, stage); - crit_temp = qpnp_tm_get_critical_trip_temp(chip); - ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); - if (ret < 0) - goto out; + if (chip->has_temp_dac) { + ret = qpnp_tm_temp_dac_update_trip_temps(chip); + if (ret < 0) + goto out; + } else { + crit_temp = qpnp_tm_get_critical_trip_temp(chip); + ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); + if (ret < 0) + goto out; + } /* Enable the thermal alarm PMIC module in always-on mode. */ reg = ALARM_CTRL_FORCE_ENABLE; @@ -392,6 +531,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; + const struct thermal_zone_device_ops *ops; u8 type, subtype, dig_major, dig_minor; u32 res; int ret, irq; @@ -463,19 +603,29 @@ static int qpnp_tm_probe(struct platform_device *pdev) return -ENODEV; } + ops = &qpnp_tm_sensor_ops; chip->subtype = subtype; - if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) + if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 2) + chip->has_temp_dac = true; + else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) chip->temp_map = &temp_map_gen2_v1; else chip->temp_map = &temp_map_gen1; + if (chip->has_temp_dac) { + ops = &qpnp_tm_sensor_temp_dac_ops; + ret = qpnp_tm_temp_dac_init(chip); + if (ret < 0) + return ret; + } + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature * before the hardware initialization is completed. */ chip->tz_dev = devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); + &pdev->dev, 0, chip, ops); if (IS_ERR(chip->tz_dev)) { dev_err(&pdev->dev, "failed to register sensor\n"); return PTR_ERR(chip->tz_dev); From patchwork Wed Dec 7 23:24:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Collins X-Patchwork-Id: 13067760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22B88C63703 for ; Wed, 7 Dec 2022 23:26:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230116AbiLGX0Q (ORCPT ); Wed, 7 Dec 2022 18:26:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230109AbiLGX0O (ORCPT ); Wed, 7 Dec 2022 18:26:14 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13C838930D; Wed, 7 Dec 2022 15:26:12 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B7NQ4HD014549; Wed, 7 Dec 2022 23:26:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=V2RHTNYj+y3MoQL8XxgBIwmq8NM9acbI0Zw8SiwpklU=; b=f+MkYFL0jkfY9rOscS11AOd6ZlBMqCqrRd2ccYFqMGIlNihfAjk+xBniGYIsZ+Hl6PRz QImci5mCQLzvkhbICeGBfIYPHIrA3CTI8sgORZGpGPcFagoNYEnGjdHRkqxQ2eInRAMs 2ieOiLJovBkhOy66/UKuS+H4eWTFrKY1D5tJaQwugDQ78/Zc8OEgjbJW5T7ick5CXYee 9PcSOQFZotNiY84+VkaSmQAWkgStKj90+pf2y6ld4e1R1EEED49fB6dZIkI++d7mfLJQ vOEXv6hoZTZ0O+F/F2nrYf6AfsseEJBcgzHz2/6y4+ZrX3YQ3own84uxrUdkLYknRK1H pw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3maype0gck-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Dec 2022 23:26:04 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2B7NQ3tx002834 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 7 Dec 2022 23:26:03 GMT Received: from hu-collinsd-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 7 Dec 2022 15:26:02 -0800 From: David Collins To: Daniel Lezcano , "Rafael J . Wysocki" , Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson CC: David Collins , Konrad Dybcio , Zhang Rui , , , Subject: [PATCH v3 3/3] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Wed, 7 Dec 2022 15:24:58 -0800 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uH_dleP4cT9BAGG7ZZmCTha0BR2SOmq8 X-Proofpoint-ORIG-GUID: uH_dleP4cT9BAGG7ZZmCTha0BR2SOmq8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-07_11,2022-12-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212070198 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 217 +++++++++++++++++++- 1 file changed, 208 insertions(+), 9 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index a8b288de6b52..8fde75e8fd16 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -4,6 +4,7 @@ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -24,21 +25,28 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 /* TEMP_DAC_* registers are only present for TEMP_GEN2 v2.0 */ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) #define STATUS_GEN2_STATE_SHIFT 4 +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -46,6 +54,8 @@ #define ALARM_CTRL_FORCE_ENABLE BIT(7) +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 @@ -90,6 +100,19 @@ static const long temp_dac_max[STAGE_COUNT] = { 119375, 159375, 159375 }; +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_map_lite_warning[THRESH_COUNT] = { + 115000, 125000, 135000, 145000 +}; + +static const long temp_map_lite_shutdown[THRESH_COUNT] = { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 @@ -146,7 +169,7 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) { - if (chip->has_temp_dac) { + if (chip->has_temp_dac || chip->subtype == QPNP_TM_SUBTYPE_LITE) { if (stage == 0 || stage > STAGE_COUNT) return 0; @@ -164,19 +187,26 @@ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) * qpnp_tm_get_temp_stage() - return over-temperature stage * @chip: Pointer to the qpnp_tm chip * - * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. + * Return: stage (GEN1), state (GEN2), or alarm interrupt state (LITE) on + * success; or errno on failure. */ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) { int ret; + u16 addr = QPNP_TM_REG_STATUS; u8 reg = 0; - ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (chip->subtype == QPNP_TM_SUBTYPE_LITE) + addr = QPNP_TM_REG_IRQ_STATUS; + + ret = qpnp_tm_read(chip, addr, ®); if (ret < 0) return ret; if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) ret = reg & STATUS_GEN1_STAGE_MASK; + else if (chip->subtype == QPNP_TM_SUBTYPE_LITE) + ret = reg & IRQ_STATUS_MASK; else ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; @@ -199,7 +229,8 @@ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) return ret; stage = ret; - if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) { + if (chip->subtype == QPNP_TM_SUBTYPE_GEN1 + || chip->subtype == QPNP_TM_SUBTYPE_LITE) { stage_new = stage; stage_old = chip->stage; } else { @@ -282,6 +313,78 @@ static int qpnp_tm_set_temp_dac_thresh(struct qpnp_tm_chip *chip, int trip, return 0; } +static int qpnp_tm_set_temp_lite_thresh(struct qpnp_tm_chip *chip, int trip, + int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u16 addr; + u8 reg, thresh; + + if (trip < 0 || trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip = %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map = temp_map_lite_warning; + addr = QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map = temp_map_lite_shutdown; + addr = QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp = %d\n", temp); + return -EINVAL; + } + + thresh = 0; + temp_cfg = temp_map[thresh]; + for (i = THRESH_MAX; i >= THRESH_MIN; i--) { + if (temp >= temp_map[i]) { + thresh = i; + temp_cfg = temp_map[i]; + break; + } + } + + if (temp_cfg == chip->temp_dac_map[trip]) + return 0; + + ret = qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=%d\n", ret); + return ret; + } + + reg &= ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |= FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret = qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_dac_map[trip] = temp_cfg; + + return 0; +} + static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { @@ -387,6 +490,24 @@ static const struct thermal_zone_device_ops qpnp_tm_sensor_temp_dac_ops = { .set_trip_temp = qpnp_tm_set_temp_dac_trip_temp, }; +static int qpnp_tm_set_temp_lite_trip_temp(struct thermal_zone_device *tz, + int trip, int temp) +{ + struct qpnp_tm_chip *chip = tz->devdata; + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_set_temp_lite_thresh(chip, trip, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_sensor_temp_lite_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_set_temp_lite_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -473,6 +594,71 @@ static int qpnp_tm_temp_dac_init(struct qpnp_tm_chip *chip) return 0; } +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_temp_lite_update_trip_temps(struct qpnp_tm_chip *chip) +{ + const struct thermal_trip *trips; + int ret, ntrips, i; + + ntrips = of_thermal_get_ntrips(chip->tz_dev); + /* Keep hardware defaults if no DT trips are defined. */ + if (ntrips <= 0) + return 0; + + trips = of_thermal_get_trip_points(chip->tz_dev); + if (!trips) + return -EINVAL; + + for (i = 0; i < ntrips; i++) { + if (of_thermal_is_trip_valid(chip->tz_dev, i)) { + ret = qpnp_tm_set_temp_lite_thresh(chip, i, + trips[i].temperature); + if (ret < 0) + return ret; + } + } + + /* Verify that trips are strictly increasing. */ + if (chip->temp_dac_map[2] <= chip->temp_dac_map[0]) { + dev_err(chip->dev, "Threshold 2=%ld <= threshold 0=%ld\n", + chip->temp_dac_map[2], chip->temp_dac_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_temp_lite_init(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg = 0; + + /* + * Store the warning trip temp in temp_dac_map[0] and the shutdown trip + * temp in temp_dac_map[2]. The second trip point is purely in software + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_dac_map[0] = temp_map_lite_warning[thresh]; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_dac_map[2] = temp_map_lite_shutdown[thresh]; + + return 0; +} + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -499,13 +685,18 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) goto out; chip->stage = ret; - stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1 - ? chip->stage : alarm_state_map[chip->stage]; + stage = (chip->subtype == QPNP_TM_SUBTYPE_GEN1 + || chip->subtype == QPNP_TM_SUBTYPE_LITE) + ? chip->stage : alarm_state_map[chip->stage]; if (stage) chip->temp = qpnp_tm_decode_temp(chip, stage); - if (chip->has_temp_dac) { + if (chip->subtype == QPNP_TM_SUBTYPE_LITE) { + ret = qpnp_tm_temp_lite_update_trip_temps(chip); + if (ret < 0) + goto out; + } else if (chip->has_temp_dac) { ret = qpnp_tm_temp_dac_update_trip_temps(chip); if (ret < 0) goto out; @@ -597,7 +788,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->dig_revision = (dig_major << 8) | dig_minor; if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 - && subtype != QPNP_TM_SUBTYPE_GEN2)) { + && subtype != QPNP_TM_SUBTYPE_GEN2 + && subtype != QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -609,7 +801,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->has_temp_dac = true; else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) chip->temp_map = &temp_map_gen2_v1; - else + else if (subtype == QPNP_TM_SUBTYPE_GEN1) chip->temp_map = &temp_map_gen1; if (chip->has_temp_dac) { @@ -619,6 +811,13 @@ static int qpnp_tm_probe(struct platform_device *pdev) return ret; } + if (chip->subtype == QPNP_TM_SUBTYPE_LITE) { + ops = &qpnp_tm_sensor_temp_lite_ops; + ret = qpnp_tm_temp_lite_init(chip); + if (ret < 0) + return ret; + } + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature