From patchwork Thu Dec 8 06:25:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13067985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 044F9C63708 for ; Thu, 8 Dec 2022 06:25:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229754AbiLHGZW (ORCPT ); Thu, 8 Dec 2022 01:25:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbiLHGZT (ORCPT ); Thu, 8 Dec 2022 01:25:19 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5549848767 for ; Wed, 7 Dec 2022 22:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670480718; x=1702016718; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G8LA9vVA0WKBbYhT4If4VLWUJUlVJA5e/5pnoBEZ5hY=; b=lpXqmpSoNZcRQM7aJqCjLxA+wSYzy7AmiZSwT9tAe2ERwoce2Sg7dm+4 +EW9bHX+STj/tv6KpBaD2ZbfkwegnvCn7nZ+udonDsd8BAAqAl4Zzl4J8 ICDSRsBg55P8QumbSFdxkBplBFiqaWkqTVlXDc9VFGZSvunOaeBX+9g0N HpUq9LkBBC+Z4LWBKGdLYyKZ1CYWfYb960LS90h89CKRFAdWQNcVTQVUb pXbLCa2wCJ1z7c9pmqdIYvKf0vrI1GQJMFYmdGGqzhFVxB99vkoqF07m0 NCV1hUOQk9NQS7DLN1r7KdpRBd3MGTCUbjUcY7Ud92lRfGypJGJ0l7L/0 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="297444446" X-IronPort-AV: E=Sophos;i="5.96,226,1665471600"; d="scan'208";a="297444446" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 22:25:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413383" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413383" Received: from lxy-dell.sh.intel.com ([10.239.48.100]) by orsmga001.jf.intel.com with ESMTP; 07 Dec 2022 22:25:15 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 1/8] target/i386: Print CPUID subleaf info for unsupported feature Date: Thu, 8 Dec 2022 14:25:06 +0800 Message-Id: <20221208062513.2589476-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some CPUID leaves have meaningful subleaf index. Print the subleaf info in feature_word_description for CPUID features. Signed-off-by: Xiaoyao Li Reviewed-by: Eduardo Habkost --- target/i386/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 22b681ca37dd..8d95202f6a42 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4244,8 +4244,9 @@ static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { const char *reg = get_register_name_32(f->cpuid.reg); assert(reg); - return g_strdup_printf("CPUID.%02XH:%s", - f->cpuid.eax, reg); + return g_strdup_printf("CPUID.%02XH_%02XH:%s", + f->cpuid.eax, + f->cpuid.needs_ecx ? f->cpuid.ecx : 0, reg); } case MSR_FEATURE_WORD: return g_strdup_printf("MSR(%02XH)", From patchwork Thu Dec 8 06:25:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13067986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F393C4332F for ; Thu, 8 Dec 2022 06:25:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229756AbiLHGZX (ORCPT ); Thu, 8 Dec 2022 01:25:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229737AbiLHGZU (ORCPT ); Thu, 8 Dec 2022 01:25:20 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65A389D2CF for ; Wed, 7 Dec 2022 22:25:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670480719; x=1702016719; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ANSGjufLLPoRfF/om6K+WGEXxzVfJiLQYuBjX7wdEwA=; b=csC+28siBumV0S/XQMgFCGhpbeOSP15t6n+yO8OfVK7b5eTQNc1VTFrJ VKiz4zqVCEr7RhkAxPRa2tRadUWbWqidWHN0V9rBmme1mk3PTu8NdmPI5 8UnJ0XEU6z0BB4axnQvmsyeyj75WHeRDlZYDr+d5iBmVLWHGj2DES8MoE Ep7g/eY/9/tuyoszraPzeoM4Qn1FA6zwE9dLO5pJGf1NB41AK0Edj17W+ iW09p1dtiVqijPboJpjEsjsBFDwrhGwYR2Gxb0tPCB4FcNevaKifyjT24 XZGsGOGpyh2ScAk4wxUmT30YNkUlH59Ce6I5uHJAjjFQ6f9mNVzyTXcCv Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="297444455" X-IronPort-AV: E=Sophos;i="5.96,226,1665471600"; d="scan'208";a="297444455" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 22:25:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413394" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413394" Received: from lxy-dell.sh.intel.com ([10.239.48.100]) by orsmga001.jf.intel.com with ESMTP; 07 Dec 2022 22:25:17 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK Date: Thu, 8 Dec 2022 14:25:07 +0800 Message-Id: <20221208062513.2589476-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Per Intel SDM, bits 2:0 of CPUID(0x14,0x1).EAX indicate the number of address ranges for INTEL-PT. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8d95202f6a42..9ae36639d380 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -570,7 +570,7 @@ static CPUCacheInfo legacy_l3_cache = { /* generated packets which contain IP payloads have LIP values */ #define INTEL_PT_IP_LIP (1 << 31) #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ From patchwork Thu Dec 8 06:25:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13067987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBA4EC63709 for ; Thu, 8 Dec 2022 06:25:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229763AbiLHGZY (ORCPT ); Thu, 8 Dec 2022 01:25:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229752AbiLHGZW (ORCPT ); Thu, 8 Dec 2022 01:25:22 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC2E1F2EC for ; Wed, 7 Dec 2022 22:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670480721; x=1702016721; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qqDomaWAedABch5XRX7qa2ftKhkbEh7yFAQLtdbNsts=; b=mjJSurAlEv71715LfQJmP6wltSkfZw2ws7mXIi5adNq9z+uUP97Xz3mM bXC4baggrn7wFweBABvQ0Tx7iKTIP4Krxl9UX6+Dbmvkf+t21sodjP0ur ii7jbLXH+AZ2JmaRQ7BhVvC7XJyf3LpiB8Rw1IJqyyKqj1ooZkjuEPTMF igd/scTnxSiRDdYHtiVZSU986Ya0osymy0gxwPiOXMNjzQhfMELZJqARc Db/F9qU4zMWKILbv+9mByxMbipuWJc5gxh7q1hKim+ii0MXQyGf6NYBqr 594QdDrikqnP5+I/qI2rjAGpDGuxJKQYn785a3wdgKZQORQyDfxCsrgr6 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="297444459" X-IronPort-AV: E=Sophos;i="5.96,226,1665471600"; d="scan'208";a="297444459" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 22:25:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413402" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413402" Received: from lxy-dell.sh.intel.com ([10.239.48.100]) by orsmga001.jf.intel.com with ESMTP; 07 Dec 2022 22:25:19 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 3/8] target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0x14 Date: Thu, 8 Dec 2022 14:25:08 +0800 Message-Id: <20221208062513.2589476-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and capability of Intel PT. Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX and FEAT_14_1_EBX, and complete FEAT_14_0_ECX. Thus all the features of Intel PT can be expanded when "-cpu host/max" and can be configured in named CPU model. Signed-off-by: Xiaoyao Li --- v3: - Add bit 7 and 8 of FEAT_14_0_EBX --- target/i386/cpu.c | 138 +++++++++++++++++++++++++++++++++++++++++++--- target/i386/cpu.h | 3 + 2 files changed, 132 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9ae36639d380..65c6f8ae771a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1208,17 +1208,34 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { } }, + [FEAT_14_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [0] = "intel-pt-cr3-filter", + [1] = "intel-pt-psb", + [2] = "intel-pt-ip-filter", + [3] = "intel-pt-mtc", + [4] = "intel-pt-ptwrite", + [5] = "intel-pt-power-event", + [6] = "intel-pt-psb-pmi-preservation", + [7] = "intel-pt-event-trace", + [8] = "intel-pt-tnt-disable", + }, + .cpuid = { + .eax = 0x14, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + }, + }, + [FEAT_14_0_ECX] = { .type = CPUID_FEATURE_WORD, .feat_names = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, "intel-pt-lip", + [0] = "intel-pt-topa", + [1] = "intel-pt-multi-topa-entries", + [2] = "intel-pt-single-range", + [3] = "intel-pt-trace-transport-subsystem", + [31] = "intel-pt-lip", }, .cpuid = { .eax = 0x14, @@ -1228,6 +1245,79 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .tcg_features = TCG_14_0_ECX_FEATURES, }, + [FEAT_14_1_EAX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [0] = "intel-pt-addr-range-num-bit0", + [1] = "intel-pt-addr-range-num-bit1", + [2] = "intel-pt-addr-range-num-bit2", + [16] = "intel-pt-mtc-period-encoding-0", + [17] = "intel-pt-mtc-period-encoding-1", + [18] = "intel-pt-mtc-period-encoding-2", + [19] = "intel-pt-mtc-period-encoding-3", + [20] = "intel-pt-mtc-period-encoding-4", + [21] = "intel-pt-mtc-period-encoding-5", + [22] = "intel-pt-mtc-period-encoding-6", + [23] = "intel-pt-mtc-period-encoding-7", + [24] = "intel-pt-mtc-period-encoding-8", + [25] = "intel-pt-mtc-period-encoding-9", + [26] = "intel-pt-mtc-period-encoding-10", + [27] = "intel-pt-mtc-period-encoding-11", + [28] = "intel-pt-mtc-period-encoding-12", + [29] = "intel-pt-mtc-period-encoding-13", + [30] = "intel-pt-mtc-period-encoding-14", + [31] = "intel-pt-mtc-period-encoding-15", + }, + .cpuid = { + .eax = 0x14, + .needs_ecx = true, .ecx = 1, + .reg = R_EAX, + }, + }, + + [FEAT_14_1_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [0] = "intel-pt-cyc-thresh-0", + [1] = "intel-pt-cyc-thresh-1", + [2] = "intel-pt-cyc-thresh-2", + [3] = "intel-pt-cyc-thresh-4", + [4] = "intel-pt-cyc-thresh-8", + [5] = "intel-pt-cyc-thresh-16", + [6] = "intel-pt-cyc-thresh-32", + [7] = "intel-pt-cyc-thresh-64", + [8] = "intel-pt-cyc-thresh-128", + [9] = "intel-pt-cyc-thresh-256", + [10] = "intel-pt-cyc-thresh-512", + [11] = "intel-pt-cyc-thresh-1024", + [12] = "intel-pt-cyc-thresh-2048", + [13] = "intel-pt-cyc-thresh-4096", + [14] = "intel-pt-cyc-thresh-8192", + [15] = "intel-pt-cyc-thresh-16384", + [16] = "intel-pt-psb-freq-2k", + [17] = "intel-pt-psb-freq-4k", + [18] = "intel-pt-psb-freq-8k", + [19] = "intel-pt-psb-freq-16k", + [20] = "intel-pt-psb-freq-32k", + [21] = "intel-pt-psb-freq-64k", + [22] = "intel-pt-psb-freq-128k", + [23] = "intel-pt-psb-freq-256k", + [24] = "intel-pt-psb-freq-512k", + [25] = "intel-pt-psb-freq-1m", + [26] = "intel-pt-psb-freq-2m", + [27] = "intel-pt-psb-freq-4m", + [28] = "intel-pt-psb-freq-8m", + [29] = "intel-pt-psb-freq-16m", + [30] = "intel-pt-psb-freq-32m", + [31] = "intel-pt-psb-freq-64m", + }, + .cpuid = { + .eax = 0x14, + .needs_ecx = true, .ecx = 1, + .reg = R_EBX, + }, + }, + [FEAT_SGX_12_0_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { @@ -1367,10 +1457,22 @@ static FeatureDep feature_dependencies[] = { .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, }, + { + .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to = { FEAT_14_0_EBX, ~0ull }, + }, { .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, .to = { FEAT_14_0_ECX, ~0ull }, }, + { + .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to = { FEAT_14_1_EAX, ~0ull }, + }, + { + .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to = { FEAT_14_1_EBX, ~0ull }, + }, { .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, @@ -6332,7 +6434,25 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) uint64_t host_feat = x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features = env->features[w]; - uint64_t unavailable_features = requested_features & ~host_feat; + uint64_t unavailable_features; + + switch (w) { + case FEAT_14_1_EAX: + /* Handling the bits except INTEL_PT_ADDR_RANGES_NUM_MASK */ + unavailable_features = (requested_features & ~host_feat) & + ~INTEL_PT_ADDR_RANGES_NUM_MASK; + /* Bits 2:0 are as a whole to represent INTEL_PT_ADDR_RANGES */ + if ((requested_features & INTEL_PT_ADDR_RANGES_NUM_MASK) > + (host_feat & INTEL_PT_ADDR_RANGES_NUM_MASK)) { + unavailable_features |= requested_features & + INTEL_PT_ADDR_RANGES_NUM_MASK; + } + break; + default: + unavailable_features = requested_features & ~host_feat; + break; + } + mark_unavailable_features(cpu, w, unavailable_features, prefix); } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a21..d8b3535d5aa7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -617,7 +617,10 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_14_0_EBX, FEAT_14_0_ECX, + FEAT_14_1_EAX, + FEAT_14_1_EBX, FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ From patchwork Thu Dec 8 06:25:09 2022 Content-Type: text/plain; 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07 Dec 2022 22:25:21 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 4/8] target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM Date: Thu, 8 Dec 2022 14:25:09 +0800 Message-Id: <20221208062513.2589476-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Bit[2:0] of CPUID.14H_01H:EAX stands as a whole for the number of INTEL PT ADDR RANGES. For unsupported value that exceeds what KVM reports, report it as a whole in mark_unavailable_features() as well. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 65c6f8ae771a..4d7beccc0af7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4387,7 +4387,14 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, return; } - for (i = 0; i < 64; ++i) { + if ((w == FEAT_14_1_EAX) && (mask & INTEL_PT_ADDR_RANGES_NUM_MASK)) { + warn_report("%s: CPUID.14H_01H:EAX [bit 2:0]", verbose_prefix); + i = 3; + } else { + i = 0; + } + + for (; i < 64; ++i) { if ((1ULL << i) & mask) { g_autofree char *feat_word_str = feature_word_description(f, i); warn_report("%s: %s%s%s [bit %d]", From patchwork Thu Dec 8 06:25:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13067989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 883B1C4332F for ; Thu, 8 Dec 2022 06:25:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229694AbiLHGZ3 (ORCPT ); Thu, 8 Dec 2022 01:25:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229781AbiLHGZ0 (ORCPT ); Thu, 8 Dec 2022 01:25:26 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACE299E457 for ; Wed, 7 Dec 2022 22:25:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670480725; x=1702016725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lch6sm3NRezR1vVEDr9IXJOolqbfpx/CiBwZlMb65y4=; b=jzDFWaBcaj6wzBt3jJETlxNiMhh0Y1LeQV+NwWQuf9t/4DWcX9pIXwgI jxrbQhZ4dV3fiUf6jNA+armOrjqQk2DwJzPACqP0cmMgveNc85MCsjMJ4 Wklxvj9cHd/V5DF05B8sDbp3SWd5xIVwgyWacJ6VKbdCjuGrNI/s8R825 9nb1InycjLytIxL9o2F5AlkD+gVJFqdtcEVP80T0OTdk24o9Zh5ecKz9N Tz9fJmcuCcPZ0+ILcVGGvynG0+u3hxRPX3c8SplBxVYWDe/aR5NuAoLHf HT5K04VlEmpjHoVgn73cKooqdtTqmUhU659ovEHXgsLHxR2vbqqoQ/of2 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="297444482" X-IronPort-AV: E=Sophos;i="5.96,226,1665471600"; d="scan'208";a="297444482" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 22:25:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413421" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413421" Received: from lxy-dell.sh.intel.com ([10.239.48.100]) by orsmga001.jf.intel.com with ESMTP; 07 Dec 2022 22:25:22 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set Date: Thu, 8 Dec 2022 14:25:10 +0800 Message-Id: <20221208062513.2589476-6-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Historically the Intel PT feature set reported from ICX silicon was chosen as the fixed feature set for Intel PT. If want to enable and expose INTEL-PT to guest, the supported Intel PT reported by host must cover the fixed feature set, which are named with MINIMAL in INTEL_PT_MINIMAL_EBX and INTEL_PT_MINIMAL_ECX. However, it's not accurate that it's more as default than minimal since SPR has less capabilities regarding CPUID(0x14,1):EBX[15:0]. Rename the feature set name to avoid future confusion and opportunistically define each feature bit. No functional change intended. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 70 ++++++++++++++++++++++------------------------- target/i386/cpu.h | 34 ++++++++++++++++++++++- 2 files changed, 65 insertions(+), 39 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4d7beccc0af7..e302cbbebfc5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -546,34 +546,29 @@ static CPUCacheInfo legacy_l3_cache = { #define L2_ITLB_4K_ASSOC 4 #define L2_ITLB_4K_ENTRIES 512 -/* CPUID Leaf 0x14 constants: */ -#define INTEL_PT_MAX_SUBLEAF 0x1 -/* - * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH - * MSR can be accessed; - * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; - * bit[02]: Support IP Filtering, TraceStop filtering, and preservation - * of Intel PT MSRs across warm reset; - * bit[03]: Support MTC timing packet and suppression of COFI-based packets; - */ -#define INTEL_PT_MINIMAL_EBX 0xf -/* - * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and - * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be - * accessed; - * bit[01]: ToPA tables can hold any number of output entries, up to the - * maximum allowed by the MaskOrTableOffset field of - * IA32_RTIT_OUTPUT_MASK_PTRS; - * bit[02]: Support Single-Range Output scheme; - */ -#define INTEL_PT_MINIMAL_ECX 0x7 -/* generated packets which contain IP payloads have LIP values */ -#define INTEL_PT_IP_LIP (1 << 31) -#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 -#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ -#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ -#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ +/* INTEL PT definitions: */ + +#define INTEL_PT_MAX_SUBLEAF 0x1 + +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 +#define INTEL_PT_DEFAULT_ADDR_RANGES_NUM 0x2 + +/* Support ART(0,3,6,9) */ +#define INTEL_PT_DEFAULT_MTC_BITMAP (0x0249 << 16) +/* Support 0,2^(0~11) */ +#define INTEL_PT_DEFAULT_CYCLE_BITMAP 0x1fff +/* Support 2K,4K,8K,16K,32K,64K */ +#define INTEL_PT_DEFAULT_PSB_BITMAP (0x003f << 16) + +#define INTEL_PT_DEFAULT_0_EBX (CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | \ + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC) + +#define INTEL_PT_DEFAULT_0_ECX (CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | \ + CPUID_14_0_ECX_SINGLE_RANGE) + +#define INTEL_PT_DEFAULT_1_EAX (INTEL_PT_DEFAULT_MTC_BITMAP | INTEL_PT_DEFAULT_ADDR_RANGES_NUM) + +#define INTEL_PT_DEFAULT_1_EBX (INTEL_PT_DEFAULT_PSB_BITMAP | INTEL_PT_DEFAULT_CYCLE_BITMAP) /* CPUID Leaf 0x1D constants: */ #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 @@ -5721,14 +5716,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (count == 0) { *eax = INTEL_PT_MAX_SUBLEAF; - *ebx = INTEL_PT_MINIMAL_EBX; - *ecx = INTEL_PT_MINIMAL_ECX; + *ebx = INTEL_PT_DEFAULT_0_EBX; + *ecx = INTEL_PT_DEFAULT_0_ECX; if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { *ecx |= CPUID_14_0_ECX_LIP; } } else if (count == 1) { - *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; - *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; + *eax = INTEL_PT_DEFAULT_1_EAX; + *ebx = INTEL_PT_DEFAULT_1_EBX; } break; } @@ -6473,13 +6468,12 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); if (!eax_0 || - ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || - ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || - ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || + ((ebx_0 & INTEL_PT_DEFAULT_0_EBX) != INTEL_PT_DEFAULT_0_EBX) || + ((ecx_0 & INTEL_PT_DEFAULT_0_ECX) != INTEL_PT_DEFAULT_0_ECX) || + ((eax_1 & INTEL_PT_DEFAULT_MTC_BITMAP) != INTEL_PT_DEFAULT_MTC_BITMAP) || ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < - INTEL_PT_ADDR_RANGES_NUM) || - ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || + INTEL_PT_DEFAULT_ADDR_RANGES_NUM) || + ((ebx_1 & INTEL_PT_DEFAULT_1_EBX) != INTEL_PT_DEFAULT_1_EBX) || ((ecx_0 & CPUID_14_0_ECX_LIP) != (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { /* diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d8b3535d5aa7..93fb5a87b40e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -906,8 +906,40 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) +/* + * IA32_RTIT_CTL.CR3 filter can be set to 1 and + * IA32_RTIT_CR3_MATCH can be accessed + */ +#define CPUID_14_0_EBX_CR3_FILTER (1U << 0) +/* Support Configurable PSB and Cycle-Accurate Mode */ +#define CPUID_14_0_EBX_PSB (1U << 1) +/* + * Support IP Filtering, IP TraceStop, and preservation + * of Intel PT MSRs across warm reset + */ +#define CPUID_14_0_EBX_IP_FILTER (1U << 2) +/* Support MTC timing packet */ +#define CPUID_14_0_EBX_MTC (1U << 3) +/* Support PTWRITE */ +#define CPUID_14_0_EBX_PTWRITE (1U << 4) +/* Support Power Event Trace packet generation */ +#define CPUID_14_0_EBX_POWER_EVENT (1U << 5) +/* Support PSB and PMI Preservation */ +#define CPUID_14_0_EBX_PSB_PMI_PRESERVATION (1U << 6) + +/* Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 */ +#define CPUID_14_0_ECX_TOPA (1U << 0) +/* + * ToPA tables can hold any number of output entries, up to the maximum allowed + * by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS + */ +#define CPUID_14_0_ECX_MULTI_ENTRIES (1U << 1) +/* Support Single-Range Output scheme */ +#define CPUID_14_0_ECX_SINGLE_RANGE (1U << 2) +/* Support IA32_RTIT_CTL.FabricEn */ +#define CPUID_14_0_ECX_TRACE_TRANS_SUBSYSTEM (1U << 3) /* Packets which contain IP payload have LIP values */ -#define CPUID_14_0_ECX_LIP (1U << 31) +#define CPUID_14_0_ECX_LIP (1U << 31) /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) From patchwork Thu Dec 8 06:25:11 2022 Content-Type: text/plain; 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07 Dec 2022 22:25:24 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 6/8] target/i386/intel-pt: Enable host pass through of Intel PT Date: Thu, 8 Dec 2022 14:25:11 +0800 Message-Id: <20221208062513.2589476-7-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") added the support of Intel PT by making CPUID[14] of PT as fixed feature set (from ICX) for any CPU model on any host. This truly breaks the PT exposure on Intel SPR platform because SPR has less supported bitmap of CPUID(0x14,1):EBX[15:0] than ICX. To fix the problem, enable pass through of host's PT capabilities for the cases "-cpu host/max" that it won't use default fixed PT feature set of ICX but expand automatically based on get_supported_cpuid reported by host. Meanwhile, it needs to ensure named CPU model still has the fixed PT feature set to not break the live migration case of "-cpu named_cpu_model,+intel-pt" Introduces env->use_default_intel_pt flag. - True means it's old CPU model that uses fixed PT feature set of ICX. - False means the named CPU model has its own PT feature set. Besides, to keep the same behavior for old CPU models that validate PT feature set against default fixed PT feature set of ICX in addition to validate from host's capabilities (via get_supported_cpuid) in x86_cpu_filter_features(). In the future, new named CPU model, e.g., Sapphire Rapids, can define its own PT feature set by setting @has_specific_intel_pt_feature_set to true and defines it's own FEAT_14_0_EBX, FEAT_14_0_ECX, FEAT_14_1_EAX and FEAT_14_1_EBX. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 71 ++++++++++++++++++++++++++--------------------- target/i386/cpu.h | 1 + 2 files changed, 40 insertions(+), 32 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e302cbbebfc5..24f3c7b06698 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5194,6 +5194,21 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) env->features[w] = def->features[w]; } + /* + * All (old) named CPU models have the same default values for INTEL_PT_* + * + * Assign the default value here since we don't want to manually copy/paste + * it to all entries in builtin_x86_defs. + */ + if (!env->features[FEAT_14_0_EBX] && !env->features[FEAT_14_0_ECX] && + !env->features[FEAT_14_1_EAX] && !env->features[FEAT_14_1_EBX]) { + env->use_default_intel_pt = true; + env->features[FEAT_14_0_EBX] = INTEL_PT_DEFAULT_0_EBX; + env->features[FEAT_14_0_ECX] = INTEL_PT_DEFAULT_0_ECX; + env->features[FEAT_14_1_EAX] = INTEL_PT_DEFAULT_1_EAX; + env->features[FEAT_14_1_EBX] = INTEL_PT_DEFAULT_1_EBX; + } + /* legacy-cache defaults to 'off' if CPU model provides cache info */ cpu->legacy_cache = !def->cache_info; @@ -5716,14 +5731,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (count == 0) { *eax = INTEL_PT_MAX_SUBLEAF; - *ebx = INTEL_PT_DEFAULT_0_EBX; - *ecx = INTEL_PT_DEFAULT_0_ECX; - if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { - *ecx |= CPUID_14_0_ECX_LIP; - } + *ebx = env->features[FEAT_14_0_EBX]; + *ecx = env->features[FEAT_14_0_ECX]; } else if (count == 1) { - *eax = INTEL_PT_DEFAULT_1_EAX; - *ebx = INTEL_PT_DEFAULT_1_EBX; + *eax = env->features[FEAT_14_1_EAX]; + *ebx = env->features[FEAT_14_1_EBX]; } break; } @@ -6425,6 +6437,7 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) CPUX86State *env = &cpu->env; FeatureWord w; const char *prefix = NULL; + uint64_t host_feat; if (verbose) { prefix = accel_uses_host_cpuid() @@ -6433,8 +6446,7 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) } for (w = 0; w < FEATURE_WORDS; w++) { - uint64_t host_feat = - x86_cpu_get_supported_feature_word(w, false); + host_feat = x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features = env->features[w]; uint64_t unavailable_features; @@ -6458,31 +6470,26 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) mark_unavailable_features(cpu, w, unavailable_features, prefix); } - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && - kvm_enabled()) { - KVMState *s = CPU(cpu)->kvm_state; - uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); - uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); - uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); - uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); - uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); - - if (!eax_0 || - ((ebx_0 & INTEL_PT_DEFAULT_0_EBX) != INTEL_PT_DEFAULT_0_EBX) || - ((ecx_0 & INTEL_PT_DEFAULT_0_ECX) != INTEL_PT_DEFAULT_0_ECX) || - ((eax_1 & INTEL_PT_DEFAULT_MTC_BITMAP) != INTEL_PT_DEFAULT_MTC_BITMAP) || - ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < - INTEL_PT_DEFAULT_ADDR_RANGES_NUM) || - ((ebx_1 & INTEL_PT_DEFAULT_1_EBX) != INTEL_PT_DEFAULT_1_EBX) || - ((ecx_0 & CPUID_14_0_ECX_LIP) != - (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { - /* - * Processor Trace capabilities aren't configurable, so if the - * host can't emulate the capabilities we report on - * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. - */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { + /* + * env->use_default_intel_pt is true means the CPU model doesn't have + * INTEL_PT_* specified. In this case, we need to check it has the + * value of default INTEL_PT to not break live migration + */ + if (env->use_default_intel_pt && + ((env->features[FEAT_14_0_EBX] != INTEL_PT_DEFAULT_0_EBX) || + ((env->features[FEAT_14_0_ECX] & ~CPUID_14_0_ECX_LIP) != + INTEL_PT_DEFAULT_0_ECX) || + (env->features[FEAT_14_1_EAX] != INTEL_PT_DEFAULT_1_EAX) || + (env->features[FEAT_14_1_EBX] != INTEL_PT_DEFAULT_1_EBX))) { mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); } + + host_feat = x86_cpu_get_supported_feature_word(FEAT_14_0_ECX, false); + if ((env->features[FEAT_14_0_ECX] ^ host_feat) & CPUID_14_0_ECX_LIP) { + warn_report("Cannot configure different Intel PT IP payload format than hardware"); + mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, NULL); + } } } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 93fb5a87b40e..91a3971c1c29 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1784,6 +1784,7 @@ typedef struct CPUArchState { uint32_t cpuid_vendor2; uint32_t cpuid_vendor3; uint32_t cpuid_version; + bool use_default_intel_pt; FeatureWordArray features; /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; From patchwork Thu Dec 8 06:25:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13067991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17424C63708 for ; Thu, 8 Dec 2022 06:25:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229786AbiLHGZf (ORCPT ); Thu, 8 Dec 2022 01:25:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229781AbiLHGZa (ORCPT ); Thu, 8 Dec 2022 01:25:30 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A36189E459 for ; Wed, 7 Dec 2022 22:25:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670480729; x=1702016729; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fOmR1JCdiaffCYVDbb1S5VJR9D6xo/R7Jt4fOToUMvU=; b=HEtKk9vUjHbx8/tvkS6YIoo2sdqtEumedfoS3jF6YiQJMi2nVOB0P8zu WHI6Ws1vjpDDAI3NiuyjJmurh3ZK6Sg0we2pzo7EZcBhvj6xnNi4kAoVG vc0Y1BeKA9aNbjUeqeF6BBoX9TljLtHHTDKFDTG+V2wV9pBrKWUrzdTqQ Q04V5GE8HS7fdyqrLKmKvlWQ75VYXUUKJ3HuQNZq5MXl+VWAD/bhp2F06 S3+fpMSqRDwMTaIAQw5UtBxH69Kose5KTdZ+x3NPdFdhoQfsUqjciyrpY sgMB8BDQFkOtUkrU/GwYSxUA5oWQkf6YtgkygUrYx2K9yzur8pB8+Aplq g==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="297444505" X-IronPort-AV: E=Sophos;i="5.96,226,1665471600"; d="scan'208";a="297444505" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 22:25:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413433" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413433" Received: from lxy-dell.sh.intel.com ([10.239.48.100]) by orsmga001.jf.intel.com with ESMTP; 07 Dec 2022 22:25:26 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge Date: Thu, 8 Dec 2022 14:25:12 +0800 Message-Id: <20221208062513.2589476-8-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org For IceLake-server, it's just the same as using the default PT feature set since the default one is exact taken from ICX. For Snowridge, define it according to real SNR silicon capabilities. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 24f3c7b06698..ef574c819671 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3458,6 +3458,14 @@ static const X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ + .features[FEAT_14_0_EBX] = + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC, + .features[FEAT_14_0_ECX] = + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | + CPUID_14_0_ECX_SINGLE_RANGE, + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2, + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x1fff, .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | @@ -3735,6 +3743,16 @@ static const X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XGETBV1, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, + .features[FEAT_14_0_EBX] = + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC | + CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_POWER_EVENT | + CPUID_14_0_EBX_PSB_PMI_PRESERVATION, + .features[FEAT_14_0_ECX] = + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | + CPUID_14_0_ECX_SINGLE_RANGE | CPUID_14_0_ECX_LIP, + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2, + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0xffff, .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | From patchwork Thu Dec 8 06:25:13 2022 Content-Type: text/plain; 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07 Dec 2022 22:25:28 -0800 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 8/8] target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration Date: Thu, 8 Dec 2022 14:25:13 +0800 Message-Id: <20221208062513.2589476-9-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM only allows userspace to access legal number of MSR_IA32_RTIT_ADDRn, which is enumrated by guest's CPUID(0x14,0x1):EAX[2:0], i.e., env->features[FEAT_14_1_EAX] & INTEL_PT_ADDR_RANGES_NUM_MASK Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 2 ++ target/i386/kvm/kvm.c | 8 ++++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 91a3971c1c29..1156813ed0ad 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -941,6 +941,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 + /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* Always save/restore FP error pointers */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a21320937943..e06a25f5e3ee 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3446,8 +3446,8 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { - int addr_num = kvm_arch_get_supported_cpuid(kvm_state, - 0x14, 1, R_EAX) & 0x7; + int addr_num = env->features[FEAT_14_1_EAX] & + INTEL_PT_ADDR_RANGES_NUM_MASK; kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, env->msr_rtit_ctrl); @@ -3889,8 +3889,8 @@ static int kvm_get_msrs(X86CPU *cpu) } if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { - int addr_num = - kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; + int addr_num = env->features[FEAT_14_1_EAX] & + INTEL_PT_ADDR_RANGES_NUM_MASK; kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);