From patchwork Thu Dec 8 09:56:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13068383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A20ABC4332F for ; Thu, 8 Dec 2022 13:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DfbBhOmm3eBn8zOlkeeecn/R2SS/pz84Hpi8GfyCoq8=; b=w9Mq9Hry44gtMy fUEoyTFUKexm3b+SgbrBFLgo4DOAPX2L1xs5D37CW6xnpE0LFiuWg+ohVO8by1lgalUY1h4lnJywJ L+t+a2gY0s50OMstSLQ9Z1XXHsiIubDozHhzHkHvpBWnmxd1DcedbNJI0wPK615YLKeVImxDAkDTY 9TrUnI0/z3Ku+s2eSXro3i4B6UlTd+bGjX9ltZj3lfQcd5LBpBbfs3VK7fWiAK0/2tqD6292PfYFK ADfD98v6ENg+OW+M7tlXuEycWLsxYOgEEamQfcQOxUuEjgR0fwgcVEEwALiYfah628ctbI2QiAE9Y JzKrTUS99zHv1tT3JBOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3Gcq-000KeX-Tq; Thu, 08 Dec 2022 13:07:45 +0000 Received: from andre.telenet-ops.be ([2a02:1800:120:4::f00:15]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3Gcl-000KIP-T1 for linux-arm-kernel@lists.infradead.org; Thu, 08 Dec 2022 13:07:42 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:5574:4fdf:a801:888e]) by andre.telenet-ops.be with bizsmtp id tp7X280022deJRf01p7XxN; Thu, 08 Dec 2022 14:07:32 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1p3GIF-002tBF-Lc; Thu, 08 Dec 2022 13:46:27 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1p3DeN-002fmw-3l; Thu, 08 Dec 2022 10:57:07 +0100 From: Geert Uytterhoeven To: Magnus Damm , Michael Turquette , Stephen Boyd Cc: Tho Vu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 1/3] clk: renesas: r8a779g0: Add custom clock for PLL2 Date: Thu, 8 Dec 2022 10:56:58 +0100 Message-Id: <76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221208_050740_230498_07F7D001 X-CRM114-Status: GOOD ( 21.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core clock) to request PLL rate changes, and enable boost mode for the High Performance mode. For now this is limited to integer multiplication modes. Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H. On R-Car S4-8, the integer and fractional multiplication fields are one bit larger resp. smaller, but R-Car S4-8 does not support High Performance mode. Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 +-- drivers/clk/renesas/rcar-gen4-cpg.c | 156 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.h | 1 + 3 files changed, 164 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 745ff9214fe8609d..48d9f34bbf37657a 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -66,13 +66,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ - DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), - DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), - DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), - DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), - DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), - DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), - DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2_VAR, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index e27832e5114fbdf0..c68d8b987054131b 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "renesas-cpg-mssr.h" @@ -27,6 +28,152 @@ static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; +#define CPG_PLLECR 0x0820 /* PLL Enable Control Register */ + +#define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \ + (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */ + +#define CPG_PLL1CR0 0x830 /* PLLn Control Registers */ +#define CPG_PLL1CR1 0x8b0 +#define CPG_PLL2CR0 0x834 +#define CPG_PLL2CR1 0x8b8 +#define CPG_PLL3CR0 0x83c +#define CPG_PLL3CR1 0x8c0 +#define CPG_PLL4CR0 0x844 +#define CPG_PLL4CR1 0x8c8 +#define CPG_PLL6CR0 0x84c +#define CPG_PLL6CR1 0x8d8 + +#define CPG_PLLxCR0_KICK BIT(31) +#define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */ +#define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */ +#define CPG_PLLxCR0_SSMODE_FM BIT(18) /* Fractional Multiplication */ +#define CPG_PLLxCR0_SSMODE_DITH BIT(17) /* Frequency Dithering */ +#define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */ +#define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */ +#define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */ + +#define SSMODE_FM BIT(2) /* Fractional Multiplication */ +#define SSMODE_DITHER BIT(1) /* Frequency Dithering */ +#define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */ + +/* PLL Clocks */ +struct cpg_pll_clk { + struct clk_hw hw; + void __iomem *pllcr0_reg; + void __iomem *pllecr_reg; + u32 pllecr_pllst_mask; +}; + +#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw) + +static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; + + mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; + + return parent_rate * mult * 2; +} + +static int cpg_pll_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned int min_mult, max_mult, mult; + unsigned long prate; + + prate = req->best_parent_rate * 2; + min_mult = max(div64_ul(req->min_rate, prate), 1ULL); + max_mult = min(div64_ul(req->max_rate, prate), 256ULL); + if (max_mult < min_mult) + return -EINVAL; + + mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); + mult = clamp(mult, min_mult, max_mult); + + req->rate = prate * mult; + return 0; +} + +static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; + u32 val; + + mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); + mult = clamp(mult, 1U, 256U); + + if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) + return -EBUSY; + + cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI, + FIELD_PREP(CPG_PLLxCR0_NI, mult - 1)); + + /* + * Set KICK bit in PLLxCR0 to update hardware setting and wait for + * clock change completion. + */ + cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK); + + /* + * Note: There is no HW information about the worst case latency. + * + * Using experimental measurements, it seems that no more than + * ~45 µs are needed, independently of the CPU rate. + * Since this value might be dependent on external xtal rate, pll + * rate or even the other emulation clocks rate, use 1000 as a + * "super" safe value. + */ + return readl_poll_timeout(pll_clk->pllecr_reg, val, + val & pll_clk->pllecr_pllst_mask, 0, 1000); +} + +static const struct clk_ops cpg_pll_clk_ops = { + .recalc_rate = cpg_pll_clk_recalc_rate, + .determine_rate = cpg_pll_clk_determine_rate, + .set_rate = cpg_pll_clk_set_rate, +}; + +static struct clk * __init cpg_pll_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + unsigned int cr0_offset, + unsigned int cr1_offset, + unsigned int index) + +{ + struct cpg_pll_clk *pll_clk; + struct clk_init_data init = {}; + struct clk *clk; + + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &cpg_pll_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll_clk->hw.init = &init; + pll_clk->pllcr0_reg = base + cr0_offset; + pll_clk->pllecr_reg = base + CPG_PLLECR; + pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); + + /* Disable Fractional Multiplication and Frequency Dithering */ + writel(0, base + cr1_offset); + cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0); + + clk = clk_register(NULL, &pll_clk->hw); + if (IS_ERR(clk)) + kfree(pll_clk); + + return clk; +} /* * Z0 Clock & Z1 Clock */ @@ -205,6 +352,15 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, div = cpg_pll_config->pll1_div; break; + case CLK_TYPE_GEN4_PLL2_VAR: + /* + * PLL2 is implemented as a custom clock, to change the + * multiplier when cpufreq changes between normal and boost + * modes. + */ + return cpg_pll_clk_register(core->name, __clk_get_name(parent), + base, CPG_PLL2CR0, CPG_PLL2CR1, 2); + case CLK_TYPE_GEN4_PLL2: mult = cpg_pll_config->pll2_mult; div = cpg_pll_config->pll2_div; diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h index 0a0e3bdb3a664c10..006537e29e4eb10e 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.h +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -13,6 +13,7 @@ enum rcar_gen4_clk_types { CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, CLK_TYPE_GEN4_PLL1, CLK_TYPE_GEN4_PLL2, + CLK_TYPE_GEN4_PLL2_VAR, CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */ CLK_TYPE_GEN4_PLL3, CLK_TYPE_GEN4_PLL4, From patchwork Thu Dec 8 09:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13068387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEEE5C3A5A7 for ; Thu, 8 Dec 2022 13:09:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ruMTjYOBUrlgJtU79OPKwUsiD1/b7W7AWLuRRE+perE=; b=lZ1wJwAl2VlneD AHuDRphIj9rCHASWpVJSJc/JssyLstontTTGUJCHC7TqMUwGABn6VgzdR9OPRvEqNRC0QHSZkfJYu DY/wPuY4aD6Qf2z5IJvOiFj/GVbPhQY+/9CWiugu24uaforgA7wrRQzY2pHLQZN2mgTGDfc2E7ZW8 CnT0my91s/a3tnBJP55yUc5pYnnPwM8XThMHwWd0IQ4VgzC48cYumY5LPMT13qRBsYJdpp6BRdT6Z F4be+4IsoRaSpOC+K2fKhn5DDYBzV52RA6aL+zbVl8z01of5FO9qzynUAKaLXG+zQDQ/bMJxKA2SN j6Lxx7i3ITKTDofGoh1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3GdZ-000LZi-QP; Thu, 08 Dec 2022 13:08:29 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3Gd0-000Kfi-MK for linux-arm-kernel@lists.infradead.org; Thu, 08 Dec 2022 13:07:58 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:5574:4fdf:a801:888e]) by laurent.telenet-ops.be with bizsmtp id tp7n280032deJRf01p7nsB; Thu, 08 Dec 2022 14:07:47 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1p3GIF-002tBF-JX; Thu, 08 Dec 2022 13:46:27 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1p3DeN-002fn0-4a; Thu, 08 Dec 2022 10:57:07 +0100 From: Geert Uytterhoeven To: Magnus Damm , Michael Turquette , Stephen Boyd Cc: Tho Vu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 2/3] clk: renesas: rcar-gen4: Add support for fractional multiplication Date: Thu, 8 Dec 2022 10:56:59 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221208_050754_944524_8AD45A02 X-CRM114-Status: GOOD ( 19.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org R-Car Gen4 PLLs support fractional multiplication, which can improve accuracy when configuring a specific frequency. Add support for fractional multiplication to the custom clock driver for PLLs, which is currently used only for PLL2 on R-Car V4H. Signed-off-by: Geert Uytterhoeven --- I am not so sure it is worth supporting this. On R-Car V4H, the following clock rates are seen for PLL2 and the Cortex-A76 CPU core clock, when using the Normal vs. the High-Performance mode: Multiplication Mode Integer Frational ---------- ---------- Normal (1.7 GHz): PLL2 3399999864 3399999997 Z0 1699999932 1699999999 High-Performance (1.8 GHz): PLL2 3599999856 3599999997 Z0 1799999928 1799999999 The improvement is of a similar order of magnitude as the accuracy of the external crystal, hence insignificant... With the current implementation, fractional multiplication does not have any impact on lower performance points, as those rely on changing the Z0 divider (which supports 32 steps only), instead of changing the PLL. --- drivers/clk/renesas/rcar-gen4-cpg.c | 69 ++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 15 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index c68d8b987054131b..54dc3aa82b499725 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -57,10 +57,13 @@ static u32 cpg_mode __initdata; #define SSMODE_DITHER BIT(1) /* Frequency Dithering */ #define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */ +#define CPG_PLLxCR1_NF GENMASK(24, 0) /* Fractional mult. factor */ + /* PLL Clocks */ struct cpg_pll_clk { struct clk_hw hw; void __iomem *pllcr0_reg; + void __iomem *pllcr1_reg; void __iomem *pllecr_reg; u32 pllecr_pllst_mask; }; @@ -71,17 +74,26 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); - unsigned int mult; - - mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; + u32 cr0 = readl(pll_clk->pllcr0_reg); + unsigned int ni, nf; + unsigned long rate; + + ni = (FIELD_GET(CPG_PLLxCR0_NI, cr0) + 1) * 2; + rate = parent_rate * ni; + if (cr0 & CPG_PLLxCR0_SSMODE_FM) { + nf = FIELD_GET(CPG_PLLxCR1_NF, readl(pll_clk->pllcr1_reg)); + rate += ((u64)parent_rate * nf) >> 24; + } - return parent_rate * mult * 2; + return rate; } static int cpg_pll_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - unsigned int min_mult, max_mult, mult; + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int min_mult, max_mult, ni, nf; + u32 cr0 = readl(pll_clk->pllcr0_reg); unsigned long prate; prate = req->best_parent_rate * 2; @@ -90,10 +102,23 @@ static int cpg_pll_clk_determine_rate(struct clk_hw *hw, if (max_mult < min_mult) return -EINVAL; - mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); - mult = clamp(mult, min_mult, max_mult); + if (cr0 & CPG_PLLxCR0_SSMODE_FM) { + ni = div64_ul(req->rate, prate); + if (ni < min_mult) { + ni = min_mult; + nf = 0; + } else { + ni = min(ni, max_mult); + nf = ((u64)(req->rate - prate * ni) << 24) / + req->best_parent_rate; + } + } else { + ni = DIV_ROUND_CLOSEST_ULL(req->rate, prate); + ni = clamp(ni, min_mult, max_mult); + nf = 0; + } + req->rate = prate * ni + (((u64)req->best_parent_rate * nf) >> 24); - req->rate = prate * mult; return 0; } @@ -101,17 +126,31 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); - unsigned int mult; + unsigned long prate = parent_rate * 2; + u32 cr0 = readl(pll_clk->pllcr0_reg); + unsigned int ni, nf; + int error; u32 val; - mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); - mult = clamp(mult, 1U, 256U); + if (cr0 & CPG_PLLxCR0_SSMODE_FM) { + ni = div64_ul(rate, prate); + if (ni < 1) { + ni = 1; + nf = 0; + } else { + ni = min(ni, 256U); + nf = ((u64)(rate - prate * ni) << 24) / parent_rate; + } + } else { + ni = DIV_ROUND_CLOSEST_ULL(rate, prate); + ni = clamp(ni, 1U, 256U); + } if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) return -EBUSY; cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI, - FIELD_PREP(CPG_PLLxCR0_NI, mult - 1)); + FIELD_PREP(CPG_PLLxCR0_NI, ni - 1)); /* * Set KICK bit in PLLxCR0 to update hardware setting and wait for @@ -161,12 +200,12 @@ static struct clk * __init cpg_pll_clk_register(const char *name, pll_clk->hw.init = &init; pll_clk->pllcr0_reg = base + cr0_offset; + pll_clk->pllcr1_reg = base + cr1_offset; pll_clk->pllecr_reg = base + CPG_PLLECR; pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); - /* Disable Fractional Multiplication and Frequency Dithering */ - writel(0, base + cr1_offset); - cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0); + /* Enable Fractional Multiplication */ + cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_SSMODE_FM); clk = clk_register(NULL, &pll_clk->hw); if (IS_ERR(clk)) From patchwork Thu Dec 8 09:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13068384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73FAEC3A5A7 for ; Thu, 8 Dec 2022 13:08:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hGSLPmSbQEcubHaN9Q+OIPaINmanENA9Rfy3olbVoiM=; b=L0Vfk/SQvovfF2 YqsikKRg5w4h3iJmIiijhkXpxqKfxQymtZ7tgSvh6NOoG9wVcy/O1mi1JbeM08JmAad0KJqyPUHfz +1iGVVBoJ5JvXaqfq6RheXdFN0wVItROMz30BcIOug4rd08APWQxKIUfTICMr7SleMt575vdNf0qN JST/vdFZijnXxhS02z0wPjdzlCvgDImZv6iUTr6GL7il+/4OtNIXQyd5BwmmMm9wObL8ysiORwzuR 3XByIRvD0pbt/u+TLIyTCiqch6AjU4t3AAJpGO7RFu8repgw46YmwxiwM5I4dYnwJZNmahjihTSsJ KOXZqTK+dJUzdcLKQJWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3Gd4-000KxP-2Y; Thu, 08 Dec 2022 13:07:58 +0000 Received: from albert.telenet-ops.be ([2a02:1800:110:4::f00:1a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p3Gd0-000Key-MB for linux-arm-kernel@lists.infradead.org; Thu, 08 Dec 2022 13:07:56 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:5574:4fdf:a801:888e]) by albert.telenet-ops.be with bizsmtp id tp7m2800D2deJRf06p7mz3; Thu, 08 Dec 2022 14:07:46 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1p3GIF-002tBF-HV; Thu, 08 Dec 2022 13:46:27 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1p3DeN-002fnQ-6n; Thu, 08 Dec 2022 10:57:07 +0100 From: Geert Uytterhoeven To: Magnus Damm , Michael Turquette , Stephen Boyd Cc: Tho Vu , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 3/3] arm64: dts: renesas: r8a779g0: Add Cortex-A76 1.8 GHz opp Date: Thu, 8 Dec 2022 10:57:00 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221208_050754_916615_F2FD4AFE X-CRM114-Status: GOOD ( 10.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an operating point for running the Cortex-A76 CPU cores on R-Car V4H at 1.8 GHz (High Performance mode). Based on a patch in the BSP by Tho Vu. Signed-off-by: Geert Uytterhoeven --- Tested on the Renesas White-Hawk development board by using the CPUfreq userspace governor, enabling boost mode, writing the desired CPU clock rate to the CPUfreq policy's "scaling_setspeed" file in sysfs, verifying the clock rate of the Z0φ clock in debugfs, and running the dhrystones benchmark on the various CPU cores. $ echo 1 > /sys/devices/system/cpu/cpufreq/boost $ echo 1800000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 83d1666a2ea16de2..7a87a5dc1b6ad219 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -39,6 +39,12 @@ opp-1700000000 { clock-latency-ns = <500000>; opp-suspend; }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + turbo-mode; + }; }; cpus {