From patchwork Fri Dec 9 04:45:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED022C10F1E for ; Fri, 9 Dec 2022 04:46:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229731AbiLIEqN (ORCPT ); Thu, 8 Dec 2022 23:46:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229646AbiLIEqI (ORCPT ); Thu, 8 Dec 2022 23:46:08 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4772131A for ; Thu, 8 Dec 2022 20:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561167; x=1702097167; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f9Ju0Am7Mf1YQQSImWs/npuBwtvt0RgWPw7i8w/BMnI=; b=Sid1m3A9VQMqfSQLHuGRfW26ipVTE2h4hXRwltOocE+6+pKCy8WxmakB pYN0CslsP4VdkkrdAICfY5QQOe+BahJcERROxhLBnRSjFOU5oJXZSj3tH +vTA+PPG7P6JxqYlS+JY4Amox+AlRHjpDXxDHTtti6xOTecr9ESEPly7G N3Y+B3FKcVuE7k74RMaYQw8p+qbQlRgykmOYJqxsdfBKX3D9o5wcd0CAi rrP5DTSTowLNOmAyTxrDuqAIydN84Ht6HhQ2JFKIzb1TTzZfSX3LVlfNG b4S/SGMKONiEkWP/Sfva4FFaD/1KRTrn4hpV65twI2zldTzdtTG+KlA0g g==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530822" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530822" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524428" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524428" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:05 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo Subject: [PATCH v3 1/9] KVM: x86: Rename cr4_reserved/rsvd_* variables to be more readable Date: Fri, 9 Dec 2022 12:45:49 +0800 Message-Id: <20221209044557.1496580-2-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_vcpu_arch::cr4_guest_owned_bits and kvm_vcpu_arch::cr4_guest_rsvd_bits looks confusing. Rename latter to cr4_host_rsvd_bits, because it in fact decribes the effective host reserved cr4 bits from the vcpu's perspective. Meanwhile, rename other related variables/macros to be better descriptive: * CR4_RESERVED_BITS --> CR4_HOST_RESERVED_BITS, which describes host bare metal CR4 reserved bits. * cr4_reserved_bits --> cr4_kvm_reserved_bits, which describes CR4_HOST_RESERVED_BITS + !kvm_cap_has() = kvm level cr4 reserved bits. * __cr4_reserved_bits() --> __cr4_calc_reserved_bits(), which to calc effective cr4 reserved bits for kvm or vm level, by corresponding x_cpu_has() input. Thus, by these renames, the hierarchical relations of those reserved CR4 bits is more clear. Just renames, no functional changes intended. Signed-off-by: Robert Hoo --- arch/x86/include/asm/kvm_host.h | 4 ++-- arch/x86/kvm/cpuid.c | 4 ++-- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/kvm/x86.c | 12 ++++++------ arch/x86/kvm/x86.h | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index f05ebaa26f0f..3c736e00b6b1 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -114,7 +114,7 @@ | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) -#define CR4_RESERVED_BITS \ +#define CR4_HOST_RESERVED_BITS \ (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ @@ -671,7 +671,7 @@ struct kvm_vcpu_arch { unsigned long cr3; unsigned long cr4; unsigned long cr4_guest_owned_bits; - unsigned long cr4_guest_rsvd_bits; + unsigned long cr4_host_rsvd_bits; unsigned long cr8; u32 host_pkru; u32 pkru; diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index c92c49a0b35b..01e2b93ef563 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -352,8 +352,8 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); kvm_pmu_refresh(vcpu); - vcpu->arch.cr4_guest_rsvd_bits = - __cr4_reserved_bits(guest_cpuid_has, vcpu); + vcpu->arch.cr4_host_rsvd_bits = + __cr4_calc_reserved_bits(guest_cpuid_has, vcpu); kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent)); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 63247c57c72c..cfa06c7c062e 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4250,7 +4250,7 @@ void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) struct kvm_vcpu *vcpu = &vmx->vcpu; vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS & - ~vcpu->arch.cr4_guest_rsvd_bits; + ~vcpu->arch.cr4_host_rsvd_bits; if (!enable_ept) { vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLBFLUSH_BITS; vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PDPTR_BITS; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 69227f77b201..eb1f2c20e19e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -108,7 +108,7 @@ u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); #endif -static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; +static u64 __read_mostly cr4_kvm_reserved_bits = CR4_HOST_RESERVED_BITS; #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) @@ -1102,10 +1102,10 @@ EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) { - if (cr4 & cr4_reserved_bits) + if (cr4 & cr4_kvm_reserved_bits) return false; - if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) + if (cr4 & vcpu->arch.cr4_host_rsvd_bits) return false; return true; @@ -12290,7 +12290,7 @@ int kvm_arch_hardware_setup(void *opaque) kvm_caps.supported_xss = 0; #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) - cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); + cr4_kvm_reserved_bits = __cr4_calc_reserved_bits(__kvm_cpu_cap_has, UNUSED_); #undef __kvm_cpu_cap_has if (kvm_caps.has_tsc_control) { @@ -12323,8 +12323,8 @@ int kvm_arch_check_processor_compat(void *opaque) WARN_ON(!irqs_disabled()); - if (__cr4_reserved_bits(cpu_has, c) != - __cr4_reserved_bits(cpu_has, &boot_cpu_data)) + if (__cr4_calc_reserved_bits(cpu_has, c) != + __cr4_calc_reserved_bits(cpu_has, &boot_cpu_data)) return -EIO; return ops->check_processor_compatibility(); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 829d3134c1eb..d92e580768e5 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -452,9 +452,9 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */ #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */ -#define __cr4_reserved_bits(__cpu_has, __c) \ +#define __cr4_calc_reserved_bits(__cpu_has, __c) \ ({ \ - u64 __reserved_bits = CR4_RESERVED_BITS; \ + u64 __reserved_bits = CR4_HOST_RESERVED_BITS; \ \ if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ __reserved_bits |= X86_CR4_OSXSAVE; \ From patchwork Fri Dec 9 04:45:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36950C4332F for ; Fri, 9 Dec 2022 04:46:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229674AbiLIEqP (ORCPT ); Thu, 8 Dec 2022 23:46:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229678AbiLIEqJ (ORCPT ); Thu, 8 Dec 2022 23:46:09 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA73B6591 for ; Thu, 8 Dec 2022 20:46:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561168; x=1702097168; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PtbatE5TlDJbQkm27ycDn3h5a8WrR0zrBrk/IVZSriA=; b=Wu7UBv96brNKh53wpmui0KMelxw1jkaybo1w7ph+/3xmRQWMw3yVZxaL pvocTu9fsdqUYXvfdQbpOPRO5NfjcuSneqK4RVdY8riUBPNqYXQXZkxFP 1vr0RGHhoTCcacY0LTO5UKrWW/uWNxQc0U3G8udTPCDvgETg4OkP4+1D+ Lj5ZMVU6mmvJq/lotSg2mbk5mcgDjegInQq2G6pYlhXm3ya/7JdZZ2GRX P1AYPoOlV7eDV4ygf1bGHbJ5avAmpK8JK+DfROvJHJ1kvXxPUgq9zbp++ MUBzagFxXOTQGIkqGOV9Drl1mE61Vk9K2b9ybkp5Ff+LrP/oB/slR9U+9 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530827" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530827" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524432" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524432" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:06 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo , Jingqi Liu Subject: [PATCH v3 2/9] KVM: x86: Add CR4.LAM_SUP in guest owned bits Date: Fri, 9 Dec 2022 12:45:50 +0800 Message-Id: <20221209044557.1496580-3-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If LAM enabled, CR4.LAM_SUP is owned by guest; otherwise, reserved. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/kvm/kvm_cache_regs.h | 3 ++- arch/x86/kvm/x86.h | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 3c736e00b6b1..275a6b2337b1 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -120,7 +120,8 @@ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ + | X86_CR4_LAM_SUP)) #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 3febc342360c..917f1b770839 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -7,7 +7,8 @@ #define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS #define KVM_POSSIBLE_CR4_GUEST_BITS \ (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ - | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE) + | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE \ + | X86_CR4_LAM_SUP) #define X86_CR0_PDPTR_BITS (X86_CR0_CD | X86_CR0_NW | X86_CR0_PG) #define X86_CR4_TLBFLUSH_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP) diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index d92e580768e5..6c1fbe27616f 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -474,6 +474,8 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); __reserved_bits |= X86_CR4_VMXE; \ if (!__cpu_has(__c, X86_FEATURE_PCID)) \ __reserved_bits |= X86_CR4_PCIDE; \ + if (!__cpu_has(__c, X86_FEATURE_LAM)) \ + __reserved_bits |= X86_CR4_LAM_SUP; \ __reserved_bits; \ }) From patchwork Fri Dec 9 04:45:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 913C4C4167B for ; Fri, 9 Dec 2022 04:46:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229710AbiLIEqR (ORCPT ); Thu, 8 Dec 2022 23:46:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbiLIEqL (ORCPT ); Thu, 8 Dec 2022 23:46:11 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 823C77B562 for ; Thu, 8 Dec 2022 20:46:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561170; x=1702097170; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EB3nfdcOjPnLvaEERG/skMDQ8/DbxeJZUBD07VgPrB8=; b=BRe1LgRN6zzlQerZuqxbw+zQJLKukfhDTRbJ4iTJmHrTfjYoNHG9BMTe RDBLeXTX+WPARi+jMZVOieqGIhHi9hZcdtIxI0dPApx60Ls/3U4O23uck mRKJCMlqYFmRTdenO0zBQ9DkgdC3iUWKX/ore1g2xjo/9XRjauXavg58Z 0eOcSLy7Fpms7PYMb2kotDWnsTbv/BNNVwiL5bs7nlFjoF+hPH2tYZ773 eNki1xF/Nriz2EeLbV8z1b9Y7EmcY6QT1VegO487qBCO9JR2qVe3z81sX VKDmgW3oXGhYjnue1UtbLooQSZl6NFlMmxOULxCki+yJh+ciY9LjHf8hC Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530835" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530835" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524438" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524438" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:08 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo , Jingqi Liu Subject: [PATCH v3 3/9] KVM: x86: MMU: Rename get_cr3() --> get_pgd() and clear high bits for pgd Date: Fri, 9 Dec 2022 12:45:51 +0800 Message-Id: <20221209044557.1496580-4-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The get_cr3() is the implementation of kvm_mmu::get_guest_pgd(), well, CR3 cannot be naturally equivalent to pgd, SDM says CR3 high bits are reserved, must be zero. And now, with LAM feature's introduction, bit 61 ~ 62 are used. So, rename get_cr3() --> get_pgd() to better indicate function purpose and in it, filtered out CR3 high bits. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/include/asm/processor-flags.h | 1 + arch/x86/kvm/mmu/mmu.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index d8cccadc83a6..bb0f8dd16956 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -38,6 +38,7 @@ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ #define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) +#define CR3_HIGH_RSVD_MASK GENMASK_ULL(63, 52) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index b6f96d47e596..d433c8923b18 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4488,9 +4488,13 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) } EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); -static unsigned long get_cr3(struct kvm_vcpu *vcpu) +static unsigned long get_pgd(struct kvm_vcpu *vcpu) { +#ifdef CONFIG_X86_64 + return kvm_read_cr3(vcpu) & ~CR3_HIGH_RSVD_MASK; +#else return kvm_read_cr3(vcpu); +#endif } static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, @@ -5043,7 +5047,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu, context->page_fault = kvm_tdp_page_fault; context->sync_page = nonpaging_sync_page; context->invlpg = NULL; - context->get_guest_pgd = get_cr3; + context->get_guest_pgd = get_pgd; context->get_pdptr = kvm_pdptr_read; context->inject_page_fault = kvm_inject_page_fault; @@ -5193,7 +5197,7 @@ static void init_kvm_softmmu(struct kvm_vcpu *vcpu, kvm_init_shadow_mmu(vcpu, cpu_role); - context->get_guest_pgd = get_cr3; + context->get_guest_pgd = get_pgd; context->get_pdptr = kvm_pdptr_read; context->inject_page_fault = kvm_inject_page_fault; } @@ -5207,7 +5211,7 @@ static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu, return; g_context->cpu_role.as_u64 = new_mode.as_u64; - g_context->get_guest_pgd = get_cr3; + g_context->get_guest_pgd = get_pgd; g_context->get_pdptr = kvm_pdptr_read; g_context->inject_page_fault = kvm_inject_page_fault; From patchwork Fri Dec 9 04:45:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB8DAC10F31 for ; Fri, 9 Dec 2022 04:46:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229773AbiLIEqS (ORCPT ); Thu, 8 Dec 2022 23:46:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbiLIEqP (ORCPT ); Thu, 8 Dec 2022 23:46:15 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E50D67D052 for ; Thu, 8 Dec 2022 20:46:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561171; x=1702097171; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cfcGuqjmJd9mFhP+Pvw2L6NRRFKtmKzaIwxt5GjI4O0=; b=SPnNYF7QW6rlBN1KxlBYcRGN3VeynaSijDOpcNA5jFt1GhJx8qrfGE8V rLOsaC+j7w7sAOS7c2FzUu2TiFD8AndK/g38U01OqB3aQBny4mG3dh2yv 2VfGeGWuedE7SxxAqa9t2Ruk68pgF7VLLKvypXyPPBk4iEbzfnN+CJ0n/ yomKOD61mebwGDSgCL2loXJogG+LJk7Bgt2zdtbjUzfRcLmPxAXVeg936 LaM2lRcvfNA/IVaLpjwr+S/5h9dpItu60DQNxzg+kqEf1ynLj/nG/+8bT FbHVVWPCYTQk7rQQwjHLixPNz2ddrpub2OiMg6hn0vmi0CPGqno9WIuBG A==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530842" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530842" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524442" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524442" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:10 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo Subject: [PATCH v3 4/9] KVM: x86: MMU: Commets update Date: Fri, 9 Dec 2022 12:45:52 +0800 Message-Id: <20221209044557.1496580-5-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_mmu_ensure_valid_pgd() is stale. Update the comments according to latest code. No function changes. P.S. Sean firstly noticed this in https://lore.kernel.org/kvm/Yg%2FguAXFLJBmDflh@google.com/. Signed-off-by: Robert Hoo --- arch/x86/kvm/mmu/mmu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index d433c8923b18..450500086932 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4452,8 +4452,12 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) struct kvm_mmu *mmu = vcpu->arch.mmu; union kvm_mmu_page_role new_role = mmu->root_role; + /* + * If no root is found in cache, current active root.hpa will be (set) + * INVALID_PAGE, a new root will be set up during vcpu_enter_guest() + * --> kvm_mmu_reload(). + */ if (!fast_pgd_switch(vcpu->kvm, mmu, new_pgd, new_role)) { - /* kvm_mmu_ensure_valid_pgd will set up a new root. */ return; } From patchwork Fri Dec 9 04:45:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20CA4C4167B for ; Fri, 9 Dec 2022 04:46:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229675AbiLIEqU (ORCPT ); Thu, 8 Dec 2022 23:46:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229524AbiLIEqR (ORCPT ); Thu, 8 Dec 2022 23:46:17 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D02D7D05D for ; Thu, 8 Dec 2022 20:46:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561173; x=1702097173; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uhiOuHLM0F8r6OVJk4a69yzS+slo/fvV8VfLB+cuWGk=; b=knIDucun3CDLkOEpVK20JKxYJyZXqbf4k5ZIYnuioX4jUYj1RJWLqVxs neYZSwytjhnHWBtja8ahwUh3xsdmyTOsUjwU+vv5g0HefHSfTMU7I6YEC 8SbCe1vVGTrh3U0c3EBaYBhPY909Vcdljidrx+d6Pu0ANR/4KluNSzIH0 KHlzvfcrXB2M3fUw8y6E5/MZoGbi8UT/nuKatY6TnWM5F4qoNca0GxxpH cIyZdnhmKkkWfKRm9DJXWb2v4tPativn7COTRiecnemLWZswx+iv1Ymaw mGBSwyENK+Wlzukt9kgi6mRnMD7OjCWebZgmxMBK/Z5K98Yo9yFssHfof A==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530851" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530851" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524455" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524455" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:11 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo , Jingqi Liu Subject: [PATCH v3 5/9] KVM: x86: MMU: Integrate LAM bits when build guest CR3 Date: Fri, 9 Dec 2022 12:45:53 +0800 Message-Id: <20221209044557.1496580-6-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When calc the new CR3 value, take LAM bits in. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/mmu.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 6bdaacb6faa0..866f2b7cb509 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -142,6 +142,11 @@ static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); } +static inline u64 kvm_get_active_lam(struct kvm_vcpu *vcpu) +{ + return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57); +} + static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) { u64 root_hpa = vcpu->arch.mmu->root.hpa; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index cfa06c7c062e..9985dbb63e7b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -3261,7 +3261,8 @@ static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa, update_guest_cr3 = false; vmx_ept_load_pdptrs(vcpu); } else { - guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu); + guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu) | + kvm_get_active_lam(vcpu); } if (update_guest_cr3) From patchwork Fri Dec 9 04:45:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28018C4332F for ; Fri, 9 Dec 2022 04:46:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229605AbiLIEqV (ORCPT ); Thu, 8 Dec 2022 23:46:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229750AbiLIEqR (ORCPT ); Thu, 8 Dec 2022 23:46:17 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A85D7B559 for ; Thu, 8 Dec 2022 20:46:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561175; x=1702097175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cKC8IXINwJ1ilcy4Kpzn6vcJdJOyTypmtAbBOvdtsO8=; b=OpAwftaPJgxD059/OVZxR0mRdQYz577lnzkfwOT2EEj9uQam3toS/jaY CpL9FjfJYznEYJiRRfJEqLKFoN310YEfKSB8CeKfPRnCCrskfnN8Nrwo5 Q0cfjOfm0to4gPmeIQmG67WSrCBGseiNKtXO7NzkNFf8ZWCHFUQajhCjd BZa/YZ9tOrxn0OMnj8QDpnReFrNs6sVvhf5VNHhNgP2hnUwXiR9dwz7mu yRD4w/58cnjIOmnrANbCRhygwJTK5awLRhJsMqKaGzIP2DQx1s1QUzsTL eN1+7773Yiuj/6/0vXZGk6mVVLqYo15jTIWDfM0sSKfVEyOsCHmEO30LD g==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530861" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530861" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524463" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524463" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:13 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo , Jingqi Liu Subject: [PATCH v3 6/9] KVM: x86: Untag LAM bits when applicable Date: Fri, 9 Dec 2022 12:45:54 +0800 Message-Id: <20221209044557.1496580-7-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Define kvm_untagged_addr() per LAM feature spec: Address high bits are sign extended, from highest effective address bit. Note that LAM_U48 and LA57 has some effective bits overlap. This patch gives a WARN() on that case. Now the only applicable possible case that addresses passed down from VM with LAM bits is those for MPX MSRs. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/vmx/vmx.c | 3 +++ arch/x86/kvm/x86.c | 5 +++++ arch/x86/kvm/x86.h | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 9985dbb63e7b..16ddd3fcd3cb 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2134,6 +2134,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) (!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) return 1; + + data = kvm_untagged_addr(data, vcpu); + if (is_noncanonical_address(data & PAGE_MASK, vcpu) || (data & MSR_IA32_BNDCFGS_RSVD)) return 1; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index eb1f2c20e19e..0a446b45e3d6 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1812,6 +1812,11 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, case MSR_KERNEL_GS_BASE: case MSR_CSTAR: case MSR_LSTAR: + /* + * LAM applies only addresses used for data accesses. + * Tagged address should never reach here. + * Strict canonical check still applies here. + */ if (is_noncanonical_address(data, vcpu)) return 1; break; diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 6c1fbe27616f..f5a2a15783c6 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -195,11 +195,48 @@ static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; } +static inline u64 get_canonical(u64 la, u8 vaddr_bits) +{ + return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); +} + static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) { return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); } +#ifdef CONFIG_X86_64 +/* untag addr for guest, according to vCPU CR3 and CR4 settings */ +static inline u64 kvm_untagged_addr(u64 addr, struct kvm_vcpu *vcpu) +{ + if (addr >> 63 == 0) { + /* User pointers */ + if (kvm_read_cr3(vcpu) & X86_CR3_LAM_U57) + addr = get_canonical(addr, 57); + else if (kvm_read_cr3(vcpu) & X86_CR3_LAM_U48) { + /* + * If guest enabled 5-level paging and LAM_U48, + * bit 47 should be 0, bit 48:56 contains meta data + * although bit 47:56 are valid 5-level address + * bits. + * If LAM_U48 and 4-level paging, bit47 is 0. + */ + WARN_ON(addr & _BITUL(47)); + addr = get_canonical(addr, 48); + } + } else if (kvm_read_cr4(vcpu) & X86_CR4_LAM_SUP) { /* Supervisor pointers */ + if (kvm_read_cr4(vcpu) & X86_CR4_LA57) + addr = get_canonical(addr, 57); + else + addr = get_canonical(addr, 48); + } + + return addr; +} +#else +#define kvm_untagged_addr(addr, vcpu) (addr) +#endif + static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, unsigned access) { From patchwork Fri Dec 9 04:45:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DE3EC4332F for ; Fri, 9 Dec 2022 04:46:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229636AbiLIEqW (ORCPT ); Thu, 8 Dec 2022 23:46:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229723AbiLIEqS (ORCPT ); Thu, 8 Dec 2022 23:46:18 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AD1E7B571 for ; Thu, 8 Dec 2022 20:46:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561177; x=1702097177; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8u4BXpnTVqMlHKPtiXBh9V+mtk3HxnkAKkRjdiyc09Q=; b=mKDZUfQdVGaA3f271TOcfkMrguXAdY5KER6jvc7jua+SixQtOSOPSk/H SpxwfCg/dLCp9iDRaSY/SCK+bUenbMiItswbpzRUStObUJGd4yET8P33X fivoh8PHcdQr5o7N+edXrsP/n3RWVbnsznwf7+1XeOzGA6tO87N3Kwl1D noKjk5+1TLibHoA389BH+xZ3SiYyWpvLkXX7z8gepmTs8daM2Jh5PZ09n Ndmak72lSt45hj+Vxq2EtsYSP8ykldEgDbQHCvOU0i1mCMJJaW4khHAwy opCnm8dznrvhsXsuRTzQYDiLvvowDGJlPj8/SUJJQA1f//msgFBdEvevS A==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530864" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530864" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524469" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524469" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:15 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo , Jingqi Liu Subject: [PATCH v3 7/9] KVM: x86: When judging setting CR3 valid or not, consider LAM bits Date: Fri, 9 Dec 2022 12:45:55 +0800 Message-Id: <20221209044557.1496580-8-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Before apply to kvm_vcpu_is_illegal_gpa(), clear LAM bits if it's valid. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/x86.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0a446b45e3d6..48a2ad1e4cd6 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1237,6 +1237,14 @@ static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); } +static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) +{ + if (guest_cpuid_has(vcpu, X86_FEATURE_LAM)) + cr3 &= ~(X86_CR3_LAM_U48 | X86_CR3_LAM_U57); + + return kvm_vcpu_is_legal_gpa(vcpu, cr3); +} + int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) { bool skip_tlb_flush = false; @@ -1260,7 +1268,7 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) * stuff CR3, e.g. for RSM emulation, and there is no guarantee that * the current vCPU mode is accurate. */ - if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) + if (!kvm_is_valid_cr3(vcpu, cr3)) return 1; if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) From patchwork Fri Dec 9 04:45:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0478C4332F for ; Fri, 9 Dec 2022 04:46:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbiLIEqY (ORCPT ); Thu, 8 Dec 2022 23:46:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229781AbiLIEqT (ORCPT ); Thu, 8 Dec 2022 23:46:19 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9985E7D061 for ; Thu, 8 Dec 2022 20:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561178; x=1702097178; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4xUO3zSqKlDiMlx0H9cA+3d/VE4hWH0/ryELl87I14E=; b=B5WDxtgKebtjRaAb+PzZ5HQtCE9Ad4GITbzabhOFtg5nf4R0/hkr5jsh Yz2CWxKsk4tVP4P8FbnEvyHAJTonpznpFyC3HaGnNn5ki6Hx1J3It8oZj vnk+08AggCXfKhuW6Hie7R8AWsv51s7+c3levLnoluX/h03+v52ww6MNp u6s+msPOs9E+VWjLL6m6vn+3P3uRyRPxdaL/fpj5GvHDFqbtzQuLBwf4g tdLiD9QnQ0szJWeKfSFUD2ANp2Kf4DTQspzuGUAQvYZGr4sBrXLzRHaf/ 08rSKnnlL11wgmyxAaL9xJwFEr/J7Qpvjpu+eDjZHxil9hC35YQr8KYpR w==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530868" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530868" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524470" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524470" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:16 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo Subject: [PATCH v3 8/9] KVM: x86: When guest set CR3, handle LAM bits semantics Date: Fri, 9 Dec 2022 12:45:56 +0800 Message-Id: <20221209044557.1496580-9-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When only changes LAM bits, ask next vcpu run to load mmu pgd, so that it will build new CR3 with LAM bits updates. No TLB flush needed on this case. When changes on effective addresses, no matter LAM bits changes or not, go through normal pgd update process. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/x86.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 48a2ad1e4cd6..6fbe8dd36b1e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1248,9 +1248,9 @@ static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) { bool skip_tlb_flush = false; - unsigned long pcid = 0; + unsigned long pcid = 0, old_cr3; #ifdef CONFIG_X86_64 - bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); + bool pcid_enabled = !!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); if (pcid_enabled) { skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; @@ -1263,6 +1263,10 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) goto handle_tlb_flush; + if (!guest_cpuid_has(vcpu, X86_FEATURE_LAM) && + (cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57))) + return 1; + /* * Do not condition the GPA check on long mode, this helper is used to * stuff CR3, e.g. for RSM emulation, and there is no guarantee that @@ -1274,8 +1278,20 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) return 1; - if (cr3 != kvm_read_cr3(vcpu)) - kvm_mmu_new_pgd(vcpu, cr3); + old_cr3 = kvm_read_cr3(vcpu); + if (cr3 != old_cr3) { + if ((cr3 ^ old_cr3) & CR3_ADDR_MASK) { + kvm_mmu_new_pgd(vcpu, cr3 & ~(X86_CR3_LAM_U48 | + X86_CR3_LAM_U57)); + } else { + /* + * Though effective addr no change, mark the + * request so that LAM bits will take effect + * when enter guest. + */ + kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); + } + } vcpu->arch.cr3 = cr3; kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); From patchwork Fri Dec 9 04:45:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13069229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED5CC4332F for ; Fri, 9 Dec 2022 04:46:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229755AbiLIEq1 (ORCPT ); Thu, 8 Dec 2022 23:46:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229810AbiLIEqV (ORCPT ); Thu, 8 Dec 2022 23:46:21 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5790D7D08B for ; Thu, 8 Dec 2022 20:46:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670561180; x=1702097180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IomsSGrJshpyZeGMJa1RixcPcuVZZpmDUTNciq4wUeg=; b=PwS07cjKScrPApUjzetWMsT1VQMcglT+ExiW1tfXSctM3dsnvCqsKs+P IgTkuzK7Z2pNznPQDHPdz5RsY1CN77NIVrESwkAR4WCSA+XOH9ayHbiSX IW7LFCF9j3NcGONdm5Z21jzsW9VKfqvxi/QlZa/tcsFDuzSLCwqq/um0k AaDQ1IUMQ8B8KdpqPaArUG1499JHNy50R6nTYedcT4sbBc837pWb07FDv IUz5/S4c+g3/qtgiVw93St7c5FRyLl4Dmna/OqHmiJoGNW4MNYs5Ee42p cMmsf1LrJVB0Lh3HsWRm6sh7pqeKJi4RrrQD58chXTAZlNqMQLXyUmxd8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318530875" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="318530875" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:46:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="892524491" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="892524491" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 08 Dec 2022 20:46:18 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com, kvm@vger.kernel.org Cc: Robert Hoo , Jingqi Liu Subject: [PATCH v3 9/9] KVM: x86: LAM: Expose LAM CPUID to user space VMM Date: Fri, 9 Dec 2022 12:45:57 +0800 Message-Id: <20221209044557.1496580-10-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221209044557.1496580-1-robert.hu@linux.intel.com> References: <20221209044557.1496580-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org LAM feature is enumerated by (EAX=07H, ECX=01H):EAX.LAM[bit26]. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 01e2b93ef563..1e7c7f9d756b 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -657,7 +657,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) + F(AVX_VNNI) | F(AVX512_BF16) | F(LAM) ); kvm_cpu_cap_mask(CPUID_D_1_EAX,