From patchwork Wed Dec 14 00:25:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 13072610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88376C4167B for ; Wed, 14 Dec 2022 00:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237445AbiLNA0D (ORCPT ); Tue, 13 Dec 2022 19:26:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237351AbiLNAZq (ORCPT ); Tue, 13 Dec 2022 19:25:46 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB096C771 for ; Tue, 13 Dec 2022 16:25:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670977543; x=1702513543; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m7jbLM0XghqsToxyKzyLdUFEETSZIgZS6zF4ttJpczw=; b=cZgclYGCRIuGarA3G/hgbA5tU9EPmmZWJKLborI79QQxCZeJeU0QUlSj ck5er689r5Z7WTW8FLkRqDAeN1uGvHR2Qe1XGGHhWq9SW5cx3eXHicQqS zfRhZ4KmffebgGcmLGAOwZf0ieq8QQj1jdxR01IF12/6+WTgygUJlucd2 XPmuInzb6qlaeGszuopPIgzYbxRy8Fc0+3UMiuQ1P/Lpt4BYEQd8nTOmq HkIryksNJvr30RNZFQAPN7MzV6t3ij63NAUAIGdrG+sEW3NwXUgBhDUqj n+b4BnaqNwHNgl0FLdLj7z0czNbcs0sJBReLOhoJHEQnVOJ4cllaDOqQf Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="404540184" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="404540184" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:42 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="823084723" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="823084723" Received: from mesplin-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.209.37.170]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:27 -0800 Subject: [ndctl PATCH 1/5] cxl/list: include --endpoints in -v listings From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Matthew Ho , Vishal Verma , vishal.l.verma@intel.com, patches@lists.linux.dev Date: Tue, 13 Dec 2022 16:25:27 -0800 Message-ID: <167097752718.1189953.16557353877320313731.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> References: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Vishal Verma The first level of -v (--verbose) for cxl-list is meant to include all topological details of the CXL hierarchy on a platform. The endpoints listing was missing from the first level, and also wasn't added at a higher verbosity level. Fix this omission by adding endpoints to the -v verbosity level. Fixes: 8b61e8e75443 ("cxl: Add list verbose option to the cxl command") Cc: Matthew Ho Cc: Dan Williams Signed-off-by: Vishal Verma --- cxl/list.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cxl/list.c b/cxl/list.c index 2f5e83d86578..e3ef1fb533c9 100644 --- a/cxl/list.c +++ b/cxl/list.c @@ -123,6 +123,7 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) case 1: param.buses = true; param.ports = true; + param.endpoints = true; param.decoders = true; param.targets = true; /*fallthrough*/ From patchwork Wed Dec 14 00:25:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 13072609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9146CC10F1B for ; Wed, 14 Dec 2022 00:26:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237157AbiLNA0C (ORCPT ); Tue, 13 Dec 2022 19:26:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237350AbiLNAZp (ORCPT ); Tue, 13 Dec 2022 19:25:45 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9F0BBF47 for ; Tue, 13 Dec 2022 16:25:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670977543; x=1702513543; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BIdIdZncQj9/eXDlCR2brzV8re22T11VTp7foz2HOk8=; b=CUgYingrDoYiUMToQtUgJOICplwAXnyJzWyS1Qk3LeoxIG5EPGUGEpFC f10AtHZ6QCq9apcmcVwkLu6Pz/q9U3tdNaRaQbjjjVv8lC9wd+Wb0ZONq Ehujw6q/N1YTL1WDdwOkqPQiZEJHQ/L9AEP10D82Q66IP2gVfYBXlCR+7 xU/ctz/IwXd4/Wh3vZzstb5acf3W37r4buDXCTst1ZtaPuwAaBlO4REuE 7nrNKrzo3MBndnrY8A9keYMDXjj6iIrWrcJ5n5PwGm9G+np33EM4J3Rqv YHA6hYcLz7MFHIzLiH2vIgCjYVOIj8Kj6xHiPlFGjqjmMjXOk0JwmNoPD A==; X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="404540182" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="404540182" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:42 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="823084742" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="823084742" Received: from mesplin-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.209.37.170]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:32 -0800 Subject: [ndctl PATCH 2/5] cxl/filter: enumerate endpoints and memdevs in an RCH From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Vishal Verma , vishal.l.verma@intel.com, patches@lists.linux.dev Date: Tue, 13 Dec 2022 16:25:32 -0800 Message-ID: <167097753265.1189953.11519741234147002252.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> References: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Vishal Verma An RCH (Restricted CXL Host) is a platform limited to a smaller subset of CXL functionality (formerly known as a CXL1.1 platform). Such a playform may still be able to host a CXL device with a higher spec level (section 9.11.8 CXL Devices Attached to an RCH in the CXL 3.0 specification). The caveat with such a configuration is that the endpoints will appear as 'Root Complex integrated Endpoints' (RCiEPs). In libcxl terms, the endpoint would be connected directly to the cxl_bus object. Until now, cxl-list and cxl_filter_walk() assume that endpoints must be under a cxl_port, which is true for CXL VH topologies. To account for endpoints in RCH topologies, change cxl_filter_walk() to also account for endpoints that may appear directly under a cxl_bus object. With this change, an example CXL RCH topology may enumerate as follows: # cxl list -v [ { "bus":"root0", "provider":"ACPI.CXL", "nr_dports":1, "dports":[ { "dport":"pci0000:38", "id":49 } ], "endpoints:root0":[ { "endpoint":"endpoint1", "host":"mem0", "depth":1, "memdev":{ "memdev":"mem0", "pmem_size":0, "ram_size":17179869184, "serial":0, "numa_node":0, "host":"0000:38:00.0" }, "decoders:endpoint1":[ { "decoder":"decoder1.0", "resource":36507222016, "size":17179869184, "interleave_ways":1 } ] } ] } ] [djbw: support mixed VH + RCH topologies (cxl_test)] Co-developed-by: Dan Williams Signed-off-by: Vishal Verma Signed-off-by: Dan Williams --- cxl/filter.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cxl/filter.c b/cxl/filter.c index 8499450ded01..90b13be79d9c 100644 --- a/cxl/filter.c +++ b/cxl/filter.c @@ -1168,6 +1168,14 @@ walk_children: walk_decoders(port, p, pick_array(jchilddecoders, jbusdecoders), pick_array(jchildregions, jregions), flags); + dbg(p, "walk rch endpoints\n"); + if (p->endpoints || p->memdevs || p->decoders) + walk_endpoints(port, p, + pick_array(jchildeps, jeps), + pick_array(jchilddevs, jdevs), + pick_array(jchilddecoders, jepdecoders), + flags); + dbg(p, "walk ports\n"); walk_child_ports(port, p, pick_array(jchildports, jports), pick_array(jchilddecoders, jportdecoders), From patchwork Wed Dec 14 00:25:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 13072608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EA46C4332F for ; Wed, 14 Dec 2022 00:26:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237132AbiLNA0B (ORCPT ); Tue, 13 Dec 2022 19:26:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237334AbiLNAZp (ORCPT ); Tue, 13 Dec 2022 19:25:45 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B256FBC83 for ; Tue, 13 Dec 2022 16:25:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670977542; x=1702513542; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+oFV1Wy9CftKO7nx/MXEO4skZVyVvCs49jK/ZpEDV2s=; b=KwYKEn6OrIz69ULDojAGAXyXsMIYeOlz7aMFGNNgyW3FzxsbBu4ICMZS lBI/pik8IXLuQib3nWwiQG2iRAtYX2lUgxg2hxefR3VcSNjQlsRb8ULzY UierFy55S67RRC1gnGWioYVGnuyxckqNQiQVSabB4OzoeFYdTQxMhwW+z uyDCG+Yk6PPavUuEnavkX2RfEjE78CiENtQDpo852LLDuuzM6YEPiLnpu an5uM3sSqRDp8O+85eAlaAQJDloF7k52BNjgtDdTySlhutvNxPeXZmPFa fgZPA0QikAQwGPr/4mH9jSzzIvIKhkGmIu17D4G0WOQnE6ItazyuBGv3B g==; X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="404540177" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="404540177" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:42 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="823084756" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="823084756" Received: from mesplin-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.209.37.170]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:38 -0800 Subject: [ndctl PATCH 3/5] cxl/lib: Add cxl_wait_probe() From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, vishal.l.verma@intel.com, patches@lists.linux.dev Date: Tue, 13 Dec 2022 16:25:38 -0800 Message-ID: <167097753806.1189953.10374103420436168237.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> References: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org In preparation for the kernel performing more bus actions asynchronously, arrange for all topolgy parsing to quiesce the cxl_bus_wq and the udev queue. This also obviates the need for 'udevadm settle' sprinkled throughout the test code. Signed-off-by: Dan Williams --- cxl/lib/libcxl.c | 91 +++++++++++++++++++++++++++++++++++---------- cxl/lib/meson.build | 1 cxl/lib/private.h | 1 test/cxl-create-region.sh | 2 - test/cxl-labels.sh | 1 test/cxl-region-sysfs.sh | 1 test/cxl-topology.sh | 1 7 files changed, 73 insertions(+), 25 deletions(-) diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index dd7161fee50e..abc73440e4a3 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -43,6 +43,9 @@ struct cxl_ctx { void *userdata; int memdevs_init; int buses_init; + unsigned long timeout; + struct udev *udev; + struct udev_queue *udev_queue; struct list_head memdevs; struct list_head buses; struct kmod_ctx *kmod_ctx; @@ -229,7 +232,9 @@ CXL_EXPORT void *cxl_get_private_data(struct cxl_ctx *ctx) */ CXL_EXPORT int cxl_new(struct cxl_ctx **ctx) { + struct udev_queue *udev_queue; struct kmod_ctx *kmod_ctx; + struct udev *udev; struct cxl_ctx *c; int rc = 0; @@ -240,7 +245,19 @@ CXL_EXPORT int cxl_new(struct cxl_ctx **ctx) kmod_ctx = kmod_new(NULL, NULL); if (check_kmod(kmod_ctx) != 0) { rc = -ENXIO; - goto out; + goto err_kmod; + } + + udev = udev_new(); + if (!udev) { + rc = -ENOMEM; + goto err_udev; + } + + udev_queue = udev_queue_new(udev); + if (!udev_queue) { + rc = -ENOMEM; + goto err_udev_queue; } c->refcount = 1; @@ -251,9 +268,17 @@ CXL_EXPORT int cxl_new(struct cxl_ctx **ctx) list_head_init(&c->memdevs); list_head_init(&c->buses); c->kmod_ctx = kmod_ctx; + c->udev = udev; + c->udev_queue = udev_queue; + c->timeout = 5000; return 0; -out: + +err_udev_queue: + udev_queue_unref(udev_queue); +err_udev: + kmod_unref(kmod_ctx); +err_kmod: free(c); return rc; } @@ -294,16 +319,13 @@ CXL_EXPORT void cxl_unref(struct cxl_ctx *ctx) list_for_each_safe(&ctx->buses, bus, _b, port.list) free_bus(bus, &ctx->buses); + udev_queue_unref(ctx->udev_queue); + udev_unref(ctx->udev); kmod_unref(ctx->kmod_ctx); info(ctx, "context %p released\n", ctx); free(ctx); } -static int cxl_flush(struct cxl_ctx *ctx) -{ - return sysfs_write_attr(ctx, "/sys/bus/cxl/flush", "1\n"); -} - /** * cxl_set_log_fn - override default log routine * @ctx: cxl library context @@ -565,6 +587,40 @@ err_path: return NULL; } +static int cxl_flush(struct cxl_ctx *ctx) +{ + return sysfs_write_attr(ctx, "/sys/bus/cxl/flush", "1\n"); +} + +static int cxl_wait_probe(struct cxl_ctx *ctx) +{ + unsigned long tmo = ctx->timeout; + int rc, sleep = 0; + + do { + rc = cxl_flush(ctx); + if (rc < 0) + break; + if (udev_queue_get_queue_is_empty(ctx->udev_queue)) + break; + sleep++; + usleep(1000); + } while (ctx->timeout == 0 || tmo-- != 0); + + if (sleep) + dbg(ctx, "waited %d millisecond%s...\n", sleep, + sleep == 1 ? "" : "s"); + + return rc < 0 ? -ENXIO : 0; +} + +static int device_parse(struct cxl_ctx *ctx, const char *base_path, + const char *dev_name, void *parent, add_dev_fn add_dev) +{ + cxl_wait_probe(ctx); + return sysfs_device_parse(ctx, base_path, dev_name, parent, add_dev); +} + static void cxl_regions_init(struct cxl_decoder *decoder) { struct cxl_port *port = cxl_decoder_get_port(decoder); @@ -579,8 +635,7 @@ static void cxl_regions_init(struct cxl_decoder *decoder) decoder->regions_init = 1; - sysfs_device_parse(ctx, decoder->dev_path, "region", decoder, - add_cxl_region); + device_parse(ctx, decoder->dev_path, "region", decoder, add_cxl_region); } CXL_EXPORT struct cxl_region *cxl_region_get_first(struct cxl_decoder *decoder) @@ -1157,7 +1212,7 @@ static void *add_cxl_memdev(void *parent, int id, const char *cxlmem_base) goto err_read; memdev->buf_len = strlen(cxlmem_base) + 50; - sysfs_device_parse(ctx, cxlmem_base, "pmem", memdev, add_cxl_pmem); + device_parse(ctx, cxlmem_base, "pmem", memdev, add_cxl_pmem); cxl_memdev_foreach(ctx, memdev_dup) if (memdev_dup->id == memdev->id) { @@ -1188,8 +1243,7 @@ static void cxl_memdevs_init(struct cxl_ctx *ctx) ctx->memdevs_init = 1; - sysfs_device_parse(ctx, "/sys/bus/cxl/devices", "mem", ctx, - add_cxl_memdev); + device_parse(ctx, "/sys/bus/cxl/devices", "mem", ctx, add_cxl_memdev); } CXL_EXPORT struct cxl_ctx *cxl_memdev_get_ctx(struct cxl_memdev *memdev) @@ -1559,8 +1613,7 @@ static void cxl_endpoints_init(struct cxl_port *port) port->endpoints_init = 1; - sysfs_device_parse(ctx, port->dev_path, "endpoint", port, - add_cxl_endpoint); + device_parse(ctx, port->dev_path, "endpoint", port, add_cxl_endpoint); } CXL_EXPORT struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint) @@ -1927,8 +1980,7 @@ static void cxl_decoders_init(struct cxl_port *port) port->decoders_init = 1; - sysfs_device_parse(ctx, port->dev_path, decoder_fmt, port, - add_cxl_decoder); + device_parse(ctx, port->dev_path, decoder_fmt, port, add_cxl_decoder); free(decoder_fmt); } @@ -2387,7 +2439,7 @@ static void cxl_ports_init(struct cxl_port *port) port->ports_init = 1; - sysfs_device_parse(ctx, port->dev_path, "port", port, add_cxl_port); + device_parse(ctx, port->dev_path, "port", port, add_cxl_port); } CXL_EXPORT struct cxl_ctx *cxl_port_get_ctx(struct cxl_port *port) @@ -2655,7 +2707,7 @@ static void cxl_dports_init(struct cxl_port *port) port->dports_init = 1; - sysfs_device_parse(ctx, port->dev_path, "dport", port, add_cxl_dport); + device_parse(ctx, port->dev_path, "dport", port, add_cxl_dport); } CXL_EXPORT int cxl_port_get_nr_dports(struct cxl_port *port) @@ -2771,8 +2823,7 @@ static void cxl_buses_init(struct cxl_ctx *ctx) ctx->buses_init = 1; - sysfs_device_parse(ctx, "/sys/bus/cxl/devices", "root", ctx, - add_cxl_bus); + device_parse(ctx, "/sys/bus/cxl/devices", "root", ctx, add_cxl_bus); } CXL_EXPORT struct cxl_bus *cxl_bus_get_first(struct cxl_ctx *ctx) diff --git a/cxl/lib/meson.build b/cxl/lib/meson.build index eba0ce7278e7..60b9de7e940d 100644 --- a/cxl/lib/meson.build +++ b/cxl/lib/meson.build @@ -15,6 +15,7 @@ cxl = library('cxl', dependencies : [ uuid, kmod, + libudev, ], version : libcxl_version, install : true, diff --git a/cxl/lib/private.h b/cxl/lib/private.h index 2d89241cd18d..81d6face263a 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -4,6 +4,7 @@ #define _LIBCXL_PRIVATE_H_ #include +#include #include #include #include diff --git a/test/cxl-create-region.sh b/test/cxl-create-region.sh index 47aed44848ab..02161661b28f 100644 --- a/test/cxl-create-region.sh +++ b/test/cxl-create-region.sh @@ -15,7 +15,6 @@ check_prereq "jq" modprobe -r cxl_test modprobe cxl_test rc=1 -udevadm settle destroy_regions() { @@ -97,7 +96,6 @@ create_subregions() echo "create sub-region failed for $decoder / $mem" err "$LINENO" fi - udevadm settle done echo "created $num_regions subregions:" diff --git a/test/cxl-labels.sh b/test/cxl-labels.sh index 3bf1e6e995b6..b38ca2f4693f 100644 --- a/test/cxl-labels.sh +++ b/test/cxl-labels.sh @@ -15,7 +15,6 @@ check_prereq "jq" modprobe -r cxl_test modprobe cxl_test rc=1 -udevadm settle test_label_ops() { diff --git a/test/cxl-region-sysfs.sh b/test/cxl-region-sysfs.sh index e128406cd8c8..863639271afa 100644 --- a/test/cxl-region-sysfs.sh +++ b/test/cxl-region-sysfs.sh @@ -15,7 +15,6 @@ check_prereq "jq" modprobe -r cxl_test modprobe cxl_test rc=1 -udevadm settle # THEORY OF OPERATION: Create a x8 interleave across the pmem capacity # of the 8 endpoints defined by cxl_test, commit the decoders (which diff --git a/test/cxl-topology.sh b/test/cxl-topology.sh index 362fffa6d539..fc3bbbe6b84a 100644 --- a/test/cxl-topology.sh +++ b/test/cxl-topology.sh @@ -15,7 +15,6 @@ check_prereq "jq" modprobe -r cxl_test modprobe cxl_test rc=1 -udevadm settle # THEORY OF OPERATION: Validate the hard coded assumptions of the # cxl_test.ko module that defines its topology in From patchwork Wed Dec 14 00:25:43 2022 Content-Type: text/plain; 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13 Dec 2022 16:25:43 -0800 Subject: [ndctl PATCH 4/5] cxl/test: Fix cxl-topology.sh expectations From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, vishal.l.verma@intel.com, patches@lists.linux.dev Date: Tue, 13 Dec 2022 16:25:43 -0800 Message-ID: <167097754348.1189953.15721727640159522971.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> References: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org When cxl_test includes an RCD there will be 4 host-bridge and 11 memdevs adjust the test expectations accodingly. Signed-off-by: Dan Williams --- test/cxl-topology.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/test/cxl-topology.sh b/test/cxl-topology.sh index fc3bbbe6b84a..89d01a89ccb1 100644 --- a/test/cxl-topology.sh +++ b/test/cxl-topology.sh @@ -117,7 +117,8 @@ fi # pmem size of 256M, or 1G json=$($CXL list -b cxl_test -M) count=$(jq "map(select(.pmem_size == $pmem_size)) | length" <<< $json) -((bridges == 2 && count == 8 || bridges == 3 && count == 10)) || err "$LINENO" +((bridges == 2 && count == 8 || bridges == 3 && count == 10 || + bridges == 4 && count == 11)) || err "$LINENO" # check that switch ports disappear after all of their memdevs have been From patchwork Wed Dec 14 00:25:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 13072612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 381B4C4332F for ; Wed, 14 Dec 2022 00:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237361AbiLNA0H (ORCPT ); Tue, 13 Dec 2022 19:26:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237365AbiLNAZ7 (ORCPT ); Tue, 13 Dec 2022 19:25:59 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2AA81402A for ; Tue, 13 Dec 2022 16:25:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670977549; x=1702513549; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mLXEzoSwM14S/kiHtmzzux6iUbcUUXezKFN/hACEsUg=; b=FdrAY2E6+6Os0f+pFu6cb6VPgRMhuwsr2xj3WW+CyLZRiEwyDKB+TuAc 4JjhiCN7CVuNDWwikqDSq1Hbqcnz3yZBtCtkQPYTXNzo/VxgVqslm5J1A jtNM6lM2wV2cqu7Ap2ZRHEX5bkSKYAXaNjZs5QMzZ8f4rkW4NwA9beWRx WLla27KiJKmHIOQYtgXv3wGWjlra3Yvt79WQDdFncpbwfuYmD6JUjOhA9 rDoX4yOOMZ+M6zYfCwcyTihyo8sWP7IUIrhPzdIe/eJPjwH61ePEuUCNY nG3BIAyZKyOKcXW8JvTxhMM61KsBepr0ZqzD5eFcdT6DH9Z34xOfIcAI+ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="404540216" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="404540216" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:49 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10560"; a="823084778" X-IronPort-AV: E=Sophos;i="5.96,242,1665471600"; d="scan'208";a="823084778" Received: from mesplin-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.209.37.170]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 16:25:49 -0800 Subject: [ndctl PATCH 5/5] cxl/test: More backtrace detection From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, vishal.l.verma@intel.com, patches@lists.linux.dev Date: Tue, 13 Dec 2022 16:25:49 -0800 Message-ID: <167097754909.1189953.2852545346689990149.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> References: <167097752151.1189953.3189708700022130101.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Make sure that backtraces are attributed to the expected test, and add more backtrace detection to other tests. Signed-off-by: Dan Williams --- test/common | 1 + test/cxl-create-region.sh | 2 ++ test/cxl-labels.sh | 2 ++ 3 files changed, 5 insertions(+) diff --git a/test/common b/test/common index 44cc352f6009..248ca3eaa485 100644 --- a/test/common +++ b/test/common @@ -138,6 +138,7 @@ json2var() check_dmesg() { # validate no WARN or lockdep report during the run + sleep 1 log=$(journalctl -r -k --since "-$((SECONDS+1))s") grep -q "Call Trace" <<< $log && err $1 true diff --git a/test/cxl-create-region.sh b/test/cxl-create-region.sh index 02161661b28f..658b9b8ff58a 100644 --- a/test/cxl-create-region.sh +++ b/test/cxl-create-region.sh @@ -149,4 +149,6 @@ for mem in ${mems[@]}; do create_subregions "$mem" done +check_dmesg "$LINENO" + modprobe -r cxl_test diff --git a/test/cxl-labels.sh b/test/cxl-labels.sh index b38ca2f4693f..36b0341c8039 100644 --- a/test/cxl-labels.sh +++ b/test/cxl-labels.sh @@ -66,4 +66,6 @@ for nmem in ${nmems[@]}; do test_label_ops "$nmem" done +check_dmesg "$LINENO" + modprobe -r cxl_test