From patchwork Thu Dec 15 19:32:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43324C25B04 for ; Thu, 15 Dec 2022 19:33:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463749.722011 (Exim 4.92) (envelope-from ) id 1p5tyX-0006aL-TJ; Thu, 15 Dec 2022 19:33:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463749.722011; Thu, 15 Dec 2022 19:33:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyX-0006aE-Q8; Thu, 15 Dec 2022 19:33:01 +0000 Received: by outflank-mailman (input) for mailman id 463749; Thu, 15 Dec 2022 19:33:00 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyW-0006TA-Ep for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:00 +0000 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2064.outbound.protection.outlook.com [40.107.95.64]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 47a32604-7caf-11ed-91b6-6bf2151ebd3b; Thu, 15 Dec 2022 20:32:59 +0100 (CET) Received: from DM6PR13CA0043.namprd13.prod.outlook.com (2603:10b6:5:134::20) by IA1PR12MB6258.namprd12.prod.outlook.com (2603:10b6:208:3e6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.11; Thu, 15 Dec 2022 19:32:56 +0000 Received: from DM6NAM11FT085.eop-nam11.prod.protection.outlook.com (2603:10b6:5:134:cafe::8d) by DM6PR13CA0043.outlook.office365.com (2603:10b6:5:134::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:32:56 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT085.mail.protection.outlook.com (10.13.172.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:32:55 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:32:54 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:32:53 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 47a32604-7caf-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MB72qYGX0z8zAK5BKc6lYzbOauNVyB4HLwaWHkrWI4sP5zQqYcAqrr2G6QpXdbCw8QQcK11+JLIYIVLht5S4qFvZXwcBT/LSKyHA7QYAIgJ/kH+4XTH4jLyC3KTgf59lkY6N9Xyt5d34XuKvzZw+olesWJN9pu1Agdt0w/HkFodzSDdQPLNeSjzi1Z5upIAlqVRu8nD3u7GG0cbHy7DsUehYyADngQWnI4qvd0am/T2rFY+wK8UVo4SqBzL+ASWCE0oF5AUR6VR/Fepqez0euPFSKm6hQUOWJJKHozIOgn88CubBlqXuwPfhO6kLgxnSve9hDLG+HEEZb+6MCVgIdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4lvaSkI20lY6fb8u8ypyUkJA8QI8c03TjbZy9rbq1Zw=; b=QONe4YKqJ7+hrRpLZMzQPWfo+MRnRZznHuDpf5WkD0fU8FyKPfVyxJyPMzpKSDg14lR0+ENY9c6JdJkYRoy4vnX15NdQbu5oLEQ3sP9z1cqSR7/LUgF355BQ9NRhAYWekCzz7pFZoRo9cd/nuffBq6xUfkoOGN8Bye+WW/7B6ENy1TpkbHqusvD1+SPo6Nrv7FwaQ6fVRfXDfttpL/B6bSR96OPaThVjFtatUwgRqVBJLwQynTxMPA1NTxxrFrTgOqsAnCVjaPDML0YVN9pzMhxD4enSYyuV81TnKXYHJ9+LYHhNTtNhO4gYPoLm3FkP7MiFRs31hBS3N7zMLKeRDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4lvaSkI20lY6fb8u8ypyUkJA8QI8c03TjbZy9rbq1Zw=; b=L5HIAnZKUfVXbdQYCV/mtmKY2rvwh78BMLD8fvgF1hkTcEGDNybue0xj9PQbbZ5SNFVwq87kaKxrGY+Lnmu5paUUM6DN9ZiuIoc+KON6Wye6duYW9mnn3Vkn75STTQM7xiJoqCengzym+2d3AEwgvUm/ECWLuseueyo+bqU1DFw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 1/9] xen/arm: Remove the extra assignment Date: Thu, 15 Dec 2022 19:32:37 +0000 Message-ID: <20221215193245.48314-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT085:EE_|IA1PR12MB6258:EE_ X-MS-Office365-Filtering-Correlation-Id: 5053bf64-eb79-47d8-e273-08daded32a45 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DR7h29BeJ/qnZ7MilG79gedhoFf4Y8+a/fEO5eeUtJGE40ZV6pHYJ5y+pcxgtwgzxsNz00d+Y7TVXRneaE8cGerjONSobpNzwxUSu9Sh/KhqTE7DAwfxltI0nB1z93jX0hvVGN73ujLpxiycfYWCZs2baKqu3eBWUc5IqxhT+AJsdY+SyCUlBNf2q7P5dW02JK2bQjv8VojBLIFfS3wMfi2tURrH8VP9Pwk3xVh4gA5r13BqOIZdRPIRbfBjvGYWW6MlNOloqzIKgzTFpuyRFPWFEtoJxp5dASykMyDl8pKzwvayl1iKhmbm7+iaKZJ95AeZZC2L8MJ5D7hBDAKu+RQOdEtl8/tqnC1gmqyCP2eEpPOhBQDxvuesVPCRAlBe1OKp0VyQYBmDjD99Ltwgf8pWrJKcxNR8bvhqdLpQ4yO75Dsk6M0fQZT9nn63yDaJTve73sMhp5QG8azI0Ix0kYkWjT+Ai2r7TwtCpw6P5kvBgnoQ8hBtd1wD4KWZLcJ/Ul65nmqKze7fKzsYq5wSGzvO49imJcYIssWT3bns2yrdqqLYZBEDLasYKUyIR1vUsE9D3Vcf7B70z07ZGtJrFKrBDsSHDqDg1+BFShNi8GMaDaYmqBtk5vGJshi1G0hzwHNPSOID+ZQEFvoUEY7uCuyzB8hEUOUmmk183EJBJNJYMuNSe9iE+z1ZAM//n5X8eYh8KH7cU/oOA8PoDOgWtfELga9fI/tV9n3qFarmpt8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(136003)(396003)(346002)(451199015)(36840700001)(46966006)(40470700004)(82310400005)(40460700003)(2906002)(356005)(316002)(103116003)(40480700001)(70206006)(83380400001)(36756003)(8676002)(2616005)(4326008)(82740400003)(6916009)(26005)(70586007)(1076003)(54906003)(186003)(81166007)(478600001)(426003)(8936002)(6666004)(86362001)(336012)(47076005)(41300700001)(5660300002)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:32:55.4254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5053bf64-eb79-47d8-e273-08daded32a45 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6258 As "io_size" and "uart->io_size" are both u64, so there will be no truncation. Thus, one can remove the ASSERT() and extra assignment. In an earlier commit (7c1de0038895), "ns16550.io_size" was u32 and "io_size" was u64. Thus, the ASSERT() was needed to check if the values are the same. However, in a later commit (c9f8e0aee507), "ns16550.io_size" was changed to u64. Thus, the ASSERT() became redundant. Signed-off-by: Ayan Kumar Halder Reviewed-by: Jan Beulich --- xen/drivers/char/ns16550.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 01a05c9aa8..58d0ccd889 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1747,7 +1747,6 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, struct ns16550 *uart; int res; u32 reg_shift, reg_width; - u64 io_size; uart = &ns16550_com[0]; @@ -1758,14 +1757,10 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &io_size); + res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); if ( res ) return res; - uart->io_size = io_size; - - ASSERT(uart->io_size == io_size); /* Detect truncation */ - res = dt_property_read_u32(dev, "reg-shift", ®_shift); if ( !res ) uart->reg_shift = 0; From patchwork Thu Dec 15 19:32:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27000C4332F for ; Thu, 15 Dec 2022 19:33:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463750.722021 (Exim 4.92) (envelope-from ) id 1p5tyb-0006s5-5u; Thu, 15 Dec 2022 19:33:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463750.722021; Thu, 15 Dec 2022 19:33:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyb-0006ry-2i; Thu, 15 Dec 2022 19:33:05 +0000 Received: by outflank-mailman (input) for mailman id 463750; Thu, 15 Dec 2022 19:33:03 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyZ-0006KU-Pr for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:03 +0000 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2083.outbound.protection.outlook.com [40.107.102.83]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 49ac883b-7caf-11ed-8fd3-01056ac49cbb; Thu, 15 Dec 2022 20:33:02 +0100 (CET) Received: from DM5PR07CA0092.namprd07.prod.outlook.com (2603:10b6:4:ae::21) by CH0PR12MB5091.namprd12.prod.outlook.com (2603:10b6:610:be::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12; Thu, 15 Dec 2022 19:32:59 +0000 Received: from DS1PEPF0000E644.namprd02.prod.outlook.com (2603:10b6:4:ae:cafe::25) by DM5PR07CA0092.outlook.office365.com (2603:10b6:4:ae::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:32:59 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E644.mail.protection.outlook.com (10.167.17.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.9 via Frontend Transport; Thu, 15 Dec 2022 19:32:59 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:32:57 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:32:57 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:32:56 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 49ac883b-7caf-11ed-8fd3-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Xg5o1zkItVJY2AOXu9KfQtYOrdnky6GjMIei7mexiv7lyHze1zAUGzeOBia+7SAxTMs5+SU6ImmDcGFTog0y/zjUt9bQQoRT6DDy7gG5W9HA/q+b1FMlKe2gy8khVKUfmANm3+e6mrRekCkiJg9kWxM7VlKw3OkiWACcxusXzpTO2YMNk+IIHDu6AyW0NuOfEhwte8urZJ+3f6JVCrKkuBd2MuCTbaO8EBC8GGbt+0rMrk7zkylBL/5YWmT2dfRzgmtM0UBgOVoIeWEQfZnZPbiqxbZNkupBIAhODJiegrKfpQwr9SoMkXfP9N3HGVTqkvCb670r57Bz8mqGLbY2/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nEcjDNJBIOdqWQvewngXlND3JwUSJKnAsyDlrtHgpXw=; b=AaPreCpbWE771yaxNRin2QU0dKV1I59WCpDW5rq/rIXO5Vytmfjkh7+wT5pQiKgUvcSHmVVyPb52SwRAqnnSV9urQJ4G/u3MQkC1l/4LHyLBvOVYseDENapBzwhGf17Fn307f1+BEPAXyVHtXghIRbd7pygTWkKBlZ3Tu8DyHknFycU05Eppum71LvmAi30bNyjqdwYstahv7IrfHb3D4hQj5Y+PPq4YZlGamm8PwWza6R2cHXSYmFgiMXKf+aiIZ6dsas+3UJWmKzVDEx0dgwsNEA6BOWw0qyFnMM21yqxrjqbJ//0eGjWCDm+urZFMAmYkYIHF+6+nEAYvYdqMDQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nEcjDNJBIOdqWQvewngXlND3JwUSJKnAsyDlrtHgpXw=; b=5J2gydSOAgEhPqmIPNSUUm8lGj0gf/GHPWe+7GXNfGaw7CxKVx09Wsd8dP1u10ROjyrYRrds6Qe0q/Oxl8O2Ug8YV3MIJAN9fXQxFTiCgQth74+ozzBhHnnimCObfNuQl3h3n2b3e41z9C1flGNx0lPmI7CFPJLtLwEUCvD9BGY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 2/9] xen/arm: Define translate_dt_address_size() for the translation between u64 and paddr_t Date: Thu, 15 Dec 2022 19:32:38 +0000 Message-ID: <20221215193245.48314-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E644:EE_|CH0PR12MB5091:EE_ X-MS-Office365-Filtering-Correlation-Id: 36cf6f67-9b36-408f-4299-08daded32c91 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tx/by94KrXnIowkCbGkaM8I6FrKN8u/SwUsT2V9SKXaROwIFh/RR7rxJHaybZBk6hFw939WHtTZ7pSPw/944UxDWCfxC/LOHPTaOboH4XxRvG0i4e3qAftS6bLrCXeXaqgLmvSsxR9q8SSJmgd9oUkgeyvov/I9dLdIjx3U2+QdPepxTxQoMJG8tplwTA21u0RjdzKKtwgnq5qEOSSo7v7GqqRSoNHO9MDG0gDI9VC4GB+d84d6wR/1ucHi4U43AceFeRAYwneKWAiPQEpWGyuCSOiMTfJYXIpjzkZ9wOVFZzueesI+yALNmfkDH52+VQ8NYqvYo18k6GzKXSVn914W+RUhrv/VaQBpkKfGbDeazbLvWBswnLzQXTd3aEb+Hkzij8IlrWzB9UDfzkcHj7CRPvVqmD01nCma1tALGWRZJ4wEz+4xyrCqzEcoQ6WZIkW7gWO7T3arl7R7Ai/pSC4GirMNCOKdCvmHnreyEi25hBePeMN9Zyj+PXMWwbKfvYq9ReyTeIIC2U4JrEzMA9gCSGYPjVdsm4JjkjsXlREebJLHz1bffYp6Jlog7OyCIUuyU0SO1wNlIkAYJeyCIcF3o2aq19RfkV9Okcg5YbROKiHffThlXmABLzcUaXBqywwZmaO6w7lK7vYaLQ0JPHWCe2XQ2VpIG1vwczUDnMUqhUscOjSM1ycY189r2c4R8scl1h5QCa4XKFkxC0N0aau1PYUa01LO32tPrHWgIcu4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(5660300002)(8676002)(4326008)(8936002)(70586007)(70206006)(41300700001)(103116003)(6916009)(356005)(54906003)(478600001)(316002)(2906002)(36756003)(40460700003)(86362001)(186003)(6666004)(26005)(2616005)(336012)(1076003)(47076005)(40480700001)(426003)(81166007)(82740400003)(82310400005)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:32:59.2748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36cf6f67-9b36-408f-4299-08daded32c91 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E644.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5091 paddr_t may be u64 or u32 depending of the type of architecture. Thus, while translating between u64 and paddr_t, one should check that the truncated bits are 0. If not, then raise an appropriate error. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/platform.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/xen/arch/arm/include/asm/platform.h b/xen/arch/arm/include/asm/platform.h index 997eb25216..6be1549f09 100644 --- a/xen/arch/arm/include/asm/platform.h +++ b/xen/arch/arm/include/asm/platform.h @@ -42,6 +42,32 @@ struct platform_desc { unsigned int dma_bitsize; }; +static inline int translate_dt_address_size(u64 *dt_addr, u64 *dt_size, + paddr_t *addr, paddr_t *size) +{ +#ifdef CONFIG_ARM_PA_32 + if ( dt_addr && (*dt_addr >> PADDR_SHIFT) ) + { + dprintk(XENLOG_ERR, "Error in DT. Invalid address\n"); + return -ENXIO; + } + + if ( dt_size && (*dt_size >> PADDR_SHIFT) ) + { + dprintk(XENLOG_ERR, "Error in DT. Invalid size\n"); + return -ENXIO; + } +#endif + + if ( dt_addr && addr ) + *addr = (paddr_t) (*dt_addr); + + if ( dt_size && size ) + *size = (paddr_t) (*dt_size); + + return 0; +} + /* * Quirk for platforms where device tree incorrectly reports 4K GICC * size, but actually the two GICC register ranges are placed at 64K From patchwork Thu Dec 15 19:32:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA5F5C4332F for ; Thu, 15 Dec 2022 19:33:16 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463751.722033 (Exim 4.92) (envelope-from ) id 1p5tyc-000793-Gn; Thu, 15 Dec 2022 19:33:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463751.722033; Thu, 15 Dec 2022 19:33:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyc-00078s-DE; Thu, 15 Dec 2022 19:33:06 +0000 Received: by outflank-mailman (input) for mailman id 463751; Thu, 15 Dec 2022 19:33:04 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tya-0006TA-B1 for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:04 +0000 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2045.outbound.protection.outlook.com [40.107.93.45]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 49f0abdf-7caf-11ed-91b6-6bf2151ebd3b; Thu, 15 Dec 2022 20:33:03 +0100 (CET) Received: from DM5PR07CA0111.namprd07.prod.outlook.com (2603:10b6:4:ae::40) by SJ2PR12MB7893.namprd12.prod.outlook.com (2603:10b6:a03:4c6::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.19; Thu, 15 Dec 2022 19:33:00 +0000 Received: from DS1PEPF0000E644.namprd02.prod.outlook.com (2603:10b6:4:ae:cafe::ab) by DM5PR07CA0111.outlook.office365.com (2603:10b6:4:ae::40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:00 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E644.mail.protection.outlook.com (10.167.17.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.9 via Frontend Transport; Thu, 15 Dec 2022 19:33:00 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:32:59 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:32:58 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 49f0abdf-7caf-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N8cMj1zz7OisxFhuPTmOm/1+DxK6mXC2Jg8h8XeqstiKiOUUuy/UbnxwTQesfEUbs31AP0FuPHRwxdI9preq15JBh1/wjNtXHnE0RSVYWj8NAfDk9L3K7cHvoDzgdsYpxK4oWI2APK/OoH6BqChfEM5oosUR/eYAzYkPGwP/mdCYm502Syp45t4Y0Wu7M3xH22L52s58ZJwdysF0oZete2BWrorvKCzYXUInVe+Pytui7tMLbgol9Xl9qdruBQDpDTrYgsa3M91ndyIrx/safCGt1bfY9SHl/cqGBOk/42WQ+LQAdbDyjn3EBkPBZQ+H2TTh5J/k69jHbxT6WLFjMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=G9kys79lyCmih9CHzEt5PZyku/GqRCHvt0SFfV6NNkY=; b=aKx43f6OivfE50jtorpyR9cZbEScWFQy6veA11tE18Ldr6tDFjVVYjGAbCT/ewNnYuj6+lG4xGjQ5PGXO3Jkv5Q+XzTQZ8qF8OMQj6oewc6wEzZn05tkC1Y2OCy9mKtWRGlbUk0D0/E8tanwkqcb/wEeh0OiGtoC/0EYaWac+fAL8tH2U4yNNik9l8hLnfYa+lEcaiN377a9kW5fzesLYEqmYsZ5nLkeODlES9axfgs9hNsC5q+8XvZ1BlDOsdHmNxebYTzFdHZaP+SsGTxRVUh5U3K1Rb4eWip+lT7gF7UbFB8NVdp0WDZhmqEXb3lUFFaTm0dhi4v0z4PE7CKm/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G9kys79lyCmih9CHzEt5PZyku/GqRCHvt0SFfV6NNkY=; b=h5SQxK/NhHFzUcYIgQhKOC7kSnsHjfdMgSxbr21ipeNPXqPRHSFpoLjK8K08DgR/UmOdYy1EsxeLmzpmIUwygLsZa1Un4J0NYGrgEsFm27yZQ5TYDbm2vWgN4GR8lCG0DnwOvSIr835kwF3u2d25gtKin5A4HF7v2TZhNQdxHSk= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 3/9] xen/arm: Always use 'u64' instead of 'paddr_t' for address and size in DT Date: Thu, 15 Dec 2022 19:32:39 +0000 Message-ID: <20221215193245.48314-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E644:EE_|SJ2PR12MB7893:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ec4004c-3db7-466a-8af6-08daded32d1b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uHxLCLMBpxmE3Lmi/Mp2gcDc3qV89S31kjMujfC9gZfGb28PamSI4JBN3tRPgeA3IS9LHrFEEHkR61Ey2e3qEZSWUlrYqOMjwnj7+9MmNuNQBOVUvtU0CIT0UXfd9mzaBRPPuBRusdNUFLm07TYqeo61Ggg4OQBhC8rwkG+0kZaIyyIf1HB6/3VGu8WTEz2iB3S4fwBZ3l2WMmBXC/0/ljrjYGdENclJyvi6NRnYSSPUhN6GsX5DCwR2Qub9VkZ2sWETzxIrAe7k82UY8Dkw2ZSqE0HkskjQOLv0iqM8X27hX28uR5FBX1kfmobNEpPdNMoMwngS/zrPouAkWQSUGuTCflHoalJ5AgQYHoj2EFfWSe/d9neWrIuTO/KCD6dkL6XqN9+tIabEM4K2bD/TusCwl/46yEwlhsZjhQvXTG0YEBQtdkGDZe1XaPJ3eXfLyk+w9xT0MbWsmWt2SQG8HgEPMSMyDLjuWi2YMa6xrbJZSdSH+j/fzgtL1eaKSYKb+u5tzwnKVI5/9LTcXKiBsUytK9VNev7beEl4AovWTPj2v8U8NScfXNTKrVmdm2lcvPpNzNdpH+H+kxk/j8+S0BrKCQE9GQ3yniOfY+dozpPS0xzb968NN0YYUDNIpY0CQgEcAPkyU9J/A8AkUxagU5vdnhwutc73wo6f5zzGyWvuUKaYeKQUSg2DFbNacLAZpGgSI0tGCwwdfzfUYcjKqb7x6kQ94x6joL7OSEs6YMg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199015)(36840700001)(40470700004)(46966006)(5660300002)(86362001)(316002)(54906003)(6916009)(8936002)(36860700001)(8676002)(70206006)(82310400005)(41300700001)(36756003)(4326008)(70586007)(6666004)(186003)(47076005)(40460700003)(103116003)(1076003)(2616005)(478600001)(426003)(336012)(83380400001)(2906002)(40480700001)(26005)(356005)(81166007)(82740400003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:00.1810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ec4004c-3db7-466a-8af6-08daded32d1b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E644.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7893 device_tree_get_reg(), dt_next_cell() uses u64 for address and size. Thus, the caller needs to be fixed to pass u64 values and then invoke translate_dt_address_size() to do the translation between u64 and paddr_t. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/bootfdt.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/bootfdt.c b/xen/arch/arm/bootfdt.c index 0085c28d74..835bb5feb9 100644 --- a/xen/arch/arm/bootfdt.c +++ b/xen/arch/arm/bootfdt.c @@ -14,6 +14,7 @@ #include #include #include +#include #include static bool __init device_tree_node_matches(const void *fdt, int node, @@ -68,7 +69,7 @@ static int __init device_tree_get_meminfo(const void *fdt, int node, unsigned int i, banks; const __be32 *cell; u32 reg_cells = address_cells + size_cells; - paddr_t start, size; + u64 start, size; struct meminfo *mem = data; if ( address_cells < 1 || size_cells < 1 ) @@ -219,7 +220,7 @@ static void __init process_multiboot_node(const void *fdt, int node, const struct fdt_property *prop; const __be32 *cell; bootmodule_kind kind; - paddr_t start, size; + u64 start, size; int len; /* sizeof("/chosen/") + DT_MAX_NAME + '/' + DT_MAX_NAME + '/0' => 92 */ char path[92]; @@ -379,7 +380,8 @@ static int __init process_shm_node(const void *fdt, int node, { const struct fdt_property *prop, *prop_id, *prop_role; const __be32 *cell; - paddr_t paddr, gaddr, size; + paddr_t paddr = 0, gaddr = 0, size = 0; + u64 dt_paddr, dt_gaddr, dt_size; struct meminfo *mem = &bootinfo.reserved_mem; unsigned int i; int len; @@ -443,10 +445,14 @@ static int __init process_shm_node(const void *fdt, int node, } cell = (const __be32 *)prop->data; - device_tree_get_reg(&cell, address_cells, address_cells, &paddr, &gaddr); - size = dt_next_cell(size_cells, &cell); + device_tree_get_reg(&cell, address_cells, address_cells, &dt_paddr, + &dt_gaddr); + translate_dt_address_size(&dt_paddr, &dt_gaddr, &paddr, &gaddr); - if ( !size ) + dt_size = dt_next_cell(size_cells, &cell); + translate_dt_address_size(NULL, &dt_size, NULL, &size); + + if ( !dt_size ) { printk("fdt: the size for static shared memory region can not be zero\n"); return -EINVAL; @@ -593,12 +599,12 @@ static void __init early_print_info(void) nr_rsvd = fdt_num_mem_rsv(device_tree_flattened); for ( i = 0; i < nr_rsvd; i++ ) { - paddr_t s, e; + u64 s, e; if ( fdt_get_mem_rsv(device_tree_flattened, i, &s, &e) < 0 ) continue; /* fdt_get_mem_rsv returns length */ e += s; - printk(" RESVD[%u]: %"PRIpaddr" - %"PRIpaddr"\n", i, s, e); + printk(" RESVD[%u]: %"PRIx64" - %"PRIx64"\n", i, s, e); } for ( j = 0; j < mem_resv->nr_banks; j++, i++ ) { From patchwork Thu Dec 15 19:32:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2EEB3C4332F for ; Thu, 15 Dec 2022 19:33:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463759.722060 (Exim 4.92) (envelope-from ) id 1p5tyl-0007xF-MV; Thu, 15 Dec 2022 19:33:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463759.722060; Thu, 15 Dec 2022 19:33:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyl-0007w9-GA; Thu, 15 Dec 2022 19:33:15 +0000 Received: by outflank-mailman (input) for mailman id 463759; Thu, 15 Dec 2022 19:33:13 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyj-0006TA-B8 for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:13 +0000 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4f119a06-7caf-11ed-91b6-6bf2151ebd3b; Thu, 15 Dec 2022 20:33:11 +0100 (CET) Received: from DS7PR07CA0002.namprd07.prod.outlook.com (2603:10b6:5:3af::8) by PH7PR12MB7114.namprd12.prod.outlook.com (2603:10b6:510:1ed::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.19; Thu, 15 Dec 2022 19:33:03 +0000 Received: from DS1PEPF0000E643.namprd02.prod.outlook.com (2603:10b6:5:3af:cafe::47) by DS7PR07CA0002.outlook.office365.com (2603:10b6:5:3af::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:03 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E643.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.9 via Frontend Transport; Thu, 15 Dec 2022 19:33:02 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:02 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:33:00 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4f119a06-7caf-11ed-91b6-6bf2151ebd3b ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CPdZ4UkMmYS5sUcEaqXlQcnWyo/WJ+0ZzaN0WO9gqEGPKO0y3QBuwME47DRLbl9JAbVnRUaPTpCsnIQUhOgd6x+uUw1NT4Iclh7oNJhn7Vm4LO++XnFtls8ur3ReFGLI5Z1clP6Rmc1t9eWP4UtDg3cRV6GbUZmG9d86lKNyA5pzPCpEEWYXos1bT5fC9r74WbWNHhgghPMeI0DZkerhJNwA6h7bR0N6F4yQo1nzU6iMOFbD4w22zlN4Xkv4UbFh2gAzodtBih3cxSA15W9/5DlPORQ13iUlcBiB60WBSM9k06c4UAQJE1Wi9gN7AujIj0Ccu5pAy9iuVTJmMpXGAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oaXeNokVYikPWQ+48atbArgrq9FL4V+lmPnnn5AbXy4=; b=EpspYiZ+6ozUYdzav38A6pEuDR29mAaZ1Ft0Vw+62jidCSxW9vwDcXkO4g0Y27YTv3wUsHu3St4pNzsjfGYo05tb8HspZZuPsCxxirGSWh2hw1xBjjzU/dkn2QKulaZOYr5Arn0QGr8W6lwsGJWNER6Kbyw6vx3wXLmXl1VNqXHIb6oD6NT/oKjAybn5pb+VhDXzKilLneR7/AGULBfyyIditfT52+tlZRjDdsEJ04YXsClL9pwbnYHeDL0cU2jOUbS4DGsz18VoRKMiO3/jjBEJP3yfMx27aMmGCpeqvltaJr8SIubrwz72zsC5SFiV8+nqMeyFYjhBbRnb2zpPzA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oaXeNokVYikPWQ+48atbArgrq9FL4V+lmPnnn5AbXy4=; b=xIZniVUfXSF8680cz9rS6cN6UrBNK40EZgsgUNAb3+PAw5gxMOuqyl44z9h4ALnwC5eTHbLTyfP2N8MHqtEKpShknjAtuAlf4//Ap4oZb6muYuPt42WX1C65Wgf7mZPAkiXvTlo9hILHDlGXNqT0n+R4ncvbIMPyoNVJ3bwPt20= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 4/9] xen/arm: Use translate_dt_address_size() to translate between device tree addr/size and paddr_t Date: Thu, 15 Dec 2022 19:32:40 +0000 Message-ID: <20221215193245.48314-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E643:EE_|PH7PR12MB7114:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e8fdf33-8414-48f0-6447-08daded32eb4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +F+nbp6sTV/fr5/bbqSHB4CnBXdsMrXrUG3FtwoOiicVx5FIG/ro5XJAhQxE1YEB5vnOFB82UgB0rUniKuPVoBVQwiiJ9WyPNRplNKylPkKgkfDvWQw59uEjfqb1/9DtbMtcRV1yJVeOb5phUoPUH80RjzR9YZz9YbOrQaxYSKJraAfVKhAyjVuAdw0prmNXKkdof91jjGg4sTIZuY3JU4eB0VA1+5Vq1h+1hIcD0THJ2C99Kumwgrr7fySgHpkD+qS2e4qzarVqIEVGui5nTk+9U7NiYM+3ifs+1laMNiRaxiV0+QwtZwMCrhzqG/Qif/Ra8zByCAk86CVBbOh6XHM9qLLjezoKj+kVd6vfKIwOePUNU80mXT54fOChpGyHvCahh5DeapwTTWXtJKLqcnMKjOkEnJv+c3lRhT3UA4XuOjRtVuzvd3aZ6hC6eMRGM5sjE2ls9l54uDubCJG7i+tOhnk/QsxaAqpegclIaiGaDa6BLuMcihXO20SwjfLpKKvcCDeL1rUhGjTjZyhgmNfzKbTq7/Xoy4GHeW0c4fXwk+pWsDY4xVCTrBWDq3E+YgcDT4gF1JVcJMSzO4SpMElnxi/ZD7cGBDHrnnf+pW0qT8lvHt0A44RLUZ35vYyWFjtWMhpdEfTK8v1OHnpd/ijC4RzZeJq9OSnK1suR5pwlzUm6UVin3VcojbS0FyiCl28WoT1ObbvxEvoV66dYD0TJiUeylbtHHzZLwfRzo2o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199015)(40470700004)(36840700001)(46966006)(82310400005)(478600001)(8936002)(30864003)(2616005)(83380400001)(81166007)(41300700001)(70206006)(8676002)(86362001)(70586007)(1076003)(26005)(426003)(5660300002)(36756003)(47076005)(82740400003)(4326008)(356005)(186003)(40460700003)(336012)(36860700001)(6666004)(40480700001)(6916009)(316002)(103116003)(2906002)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:02.8605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e8fdf33-8414-48f0-6447-08daded32eb4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E643.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7114 dt_device_get_address() will return address and size which are always 'u64'. One should use translate_dt_address_size() to translate address and size to 'paddr_t'. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/domain_build.c | 53 +++++++++++++++++++++++------- xen/arch/arm/gic-v2.c | 39 +++++++++++++++++----- xen/arch/arm/gic-v3.c | 33 ++++++++++++++++--- xen/arch/arm/platforms/brcm.c | 9 +++-- xen/arch/arm/platforms/exynos5.c | 48 ++++++++++++++++++--------- xen/arch/arm/platforms/sunxi.c | 11 ++++++- xen/arch/arm/setup.c | 18 ++++++++-- xen/drivers/char/exynos4210-uart.c | 10 ++++-- xen/drivers/char/ns16550.c | 13 ++++++-- xen/drivers/char/omap-uart.c | 10 ++++-- xen/drivers/char/pl011.c | 10 ++++-- xen/drivers/char/scif-uart.c | 10 ++++-- xen/drivers/passthrough/arm/smmu.c | 13 +++++--- xen/include/xen/serial.h | 2 +- 14 files changed, 218 insertions(+), 61 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index bef5e905a7..1bb97cd337 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -537,8 +537,11 @@ static mfn_t __init acquire_static_memory_bank(struct domain *d, { mfn_t smfn; int res; + u64 dt_pbase, dt_psize; + + device_tree_get_reg(cell, addr_cells, size_cells, &dt_pbase, &dt_psize); + res = translate_dt_address_size(&dt_pbase, &dt_psize, pbase, psize); - device_tree_get_reg(cell, addr_cells, size_cells, pbase, psize); ASSERT(IS_ALIGNED(*pbase, PAGE_SIZE) && IS_ALIGNED(*psize, PAGE_SIZE)); if ( PFN_DOWN(*psize) > UINT_MAX ) { @@ -929,7 +932,8 @@ static int __init process_shm(struct domain *d, struct kernel_info *kinfo, const struct dt_property *prop; const __be32 *cells; uint32_t addr_cells, size_cells; - paddr_t gbase, pbase, psize; + u64 dt_gbase = 0, dt_pbase = 0, dt_psize = 0; + paddr_t gbase = 0, pbase = 0, psize = 0; int ret = 0; unsigned int i; const char *role_str; @@ -948,8 +952,14 @@ static int __init process_shm(struct domain *d, struct kernel_info *kinfo, prop = dt_find_property(shm_node, "xen,shared-mem", NULL); BUG_ON(!prop); cells = (const __be32 *)prop->value; - device_tree_get_reg(&cells, addr_cells, addr_cells, &pbase, &gbase); - psize = dt_read_number(cells, size_cells); + device_tree_get_reg(&cells, addr_cells, addr_cells, &dt_pbase, &dt_gbase); + ret = translate_dt_address_size(&dt_pbase, &dt_gbase, &pbase, &gbase); + if ( ret ) + return ret; + + dt_psize = dt_read_number(cells, size_cells); + ret = translate_dt_address_size(NULL, &dt_psize, NULL, &psize); + if ( !IS_ALIGNED(pbase, PAGE_SIZE) || !IS_ALIGNED(gbase, PAGE_SIZE) ) { printk("%pd: physical address 0x%"PRIpaddr", or guest address 0x%"PRIpaddr" is not suitably aligned.\n", @@ -1666,13 +1676,14 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, dt_for_each_device_node( dt_host, np ) { unsigned int naddr; - u64 addr, size; + paddr_t addr, size; + u64 dt_addr, dt_size; naddr = dt_number_of_address(np); for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(np, i, &addr, &size); + res = dt_device_get_address(np, i, &dt_addr, &dt_size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -1680,6 +1691,10 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, goto out; } + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) + return res; + start = addr & PAGE_MASK; end = PAGE_ALIGN(addr + size); res = rangeset_remove_range(mem_holes, start, end - 1); @@ -2445,7 +2460,8 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, unsigned int naddr; unsigned int i; int res; - u64 addr, size; + paddr_t addr, size; + u64 dt_addr, dt_size; bool own_device = !dt_device_for_passthrough(dev); /* * We want to avoid mapping the MMIO in dom0 for the following cases: @@ -2500,7 +2516,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, /* Give permission and map MMIOs */ for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(dev, i, &addr, &size); + res = dt_device_get_address(dev, i, &dt_addr, &dt_size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2508,6 +2524,10 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, return res; } + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) + return res; + res = map_range_to_domain(dev, addr, size, &mr_data); if ( res ) return res; @@ -2917,6 +2937,7 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, struct dt_device_node *node; int res; paddr_t mstart, size, gstart; + u64 dt_mstart, dt_size, dt_gstart; /* xen,reg specifies where to map the MMIO region */ cell = (const __be32 *)xen_reg->data; @@ -2926,8 +2947,15 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, for ( i = 0; i < len; i++ ) { device_tree_get_reg(&cell, address_cells, size_cells, - &mstart, &size); - gstart = dt_next_cell(address_cells, &cell); + &dt_mstart, &dt_size); + res = translate_dt_address_size(&dt_mstart, &dt_size, &mstart, &size); + if ( res ) + return res; + + dt_gstart = dt_next_cell(address_cells, &cell); + res = translate_dt_address_size(&dt_gstart, NULL, &gstart, NULL); + if ( res ) + return res; if ( gstart & ~PAGE_MASK || mstart & ~PAGE_MASK || size & ~PAGE_MASK ) { @@ -2941,9 +2969,10 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, if ( res ) { printk(XENLOG_ERR "Unable to permit to dom%d access to" - " 0x%"PRIx64" - 0x%"PRIx64"\n", + " 0x%"PRIpaddr" - 0x%"PRIpaddr"\n", kinfo->d->domain_id, - mstart & PAGE_MASK, PAGE_ALIGN(mstart + size) - 1); + (paddr_t) (mstart & PAGE_MASK), + (paddr_t) (PAGE_ALIGN(mstart + size) - 1)); return res; } diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 61802839cb..72de0707ed 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -979,6 +979,7 @@ static void gicv2_add_v2m_frame_to_list(paddr_t addr, paddr_t size, static void gicv2_extension_dt_init(const struct dt_device_node *node) { const struct dt_device_node *v2m = NULL; + int res; /* * Check whether this GIC implements the v2m extension. If so, @@ -987,13 +988,18 @@ static void gicv2_extension_dt_init(const struct dt_device_node *node) dt_for_each_child_node(node, v2m) { u32 spi_start = 0, nr_spis = 0; + u64 dt_addr, dt_size; paddr_t addr, size; if ( !dt_device_is_compatible(v2m, "arm,gic-v2m-frame") ) continue; /* Get register frame resource from DT. */ - if ( dt_device_get_address(v2m, 0, &addr, &size) ) + if ( dt_device_get_address(v2m, 0, &dt_addr, &dt_size) ) + panic("GICv2: Cannot find a valid v2m frame address\n"); + + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) panic("GICv2: Cannot find a valid v2m frame address\n"); /* @@ -1017,20 +1023,37 @@ static void __init gicv2_dt_init(void) int res; paddr_t vsize; const struct dt_device_node *node = gicv2_info.node; + u64 dt_hbase, dt_dbase, dt_cbase, dt_csize, dt_vbase, dt_vsize; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_address(node, 0, &dt_dbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the distributor\n"); - res = dt_device_get_address(node, 1, &cbase, &csize); + res = translate_dt_address_size(&dt_dbase, NULL, &dbase, NULL); + if ( res ) + panic("GICv2: Cannot find a valid address for the distributor\n"); + + res = dt_device_get_address(node, 1, &dt_cbase, &dt_csize); + if ( res ) + panic("GICv2: Cannot find a valid address for the CPU\n"); + + res = translate_dt_address_size(&dt_cbase, &dt_csize, &cbase, &csize); if ( res ) panic("GICv2: Cannot find a valid address for the CPU\n"); - res = dt_device_get_address(node, 2, &hbase, NULL); + res = dt_device_get_address(node, 2, &dt_hbase, NULL); + if ( res ) + panic("GICv2: Cannot find a valid address for the hypervisor\n"); + + res = translate_dt_address_size(&dt_hbase, NULL, &hbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the hypervisor\n"); - res = dt_device_get_address(node, 3, &vbase, &vsize); + res = dt_device_get_address(node, 3, &dt_vbase, &dt_vsize); + if ( res ) + panic("GICv2: Cannot find a valid address for the virtual CPU\n"); + + res = translate_dt_address_size(&dt_vbase, &dt_vsize, &vbase, &vsize); if ( res ) panic("GICv2: Cannot find a valid address for the virtual CPU\n"); @@ -1049,7 +1072,7 @@ static void __init gicv2_dt_init(void) if ( csize < SZ_8K ) { printk(XENLOG_WARNING "GICv2: WARNING: " - "The GICC size is too small: %#"PRIx64" expected %#x\n", + "The GICC size is too small: %#"PRIpaddr" expected %#x\n", csize, SZ_8K); if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) ) { @@ -1280,11 +1303,11 @@ static int __init gicv2_init(void) gicv2.map_cbase += aliased_offset; printk(XENLOG_WARNING - "GICv2: Adjusting CPU interface base to %#"PRIx64"\n", + "GICv2: Adjusting CPU interface base to %#"PRIpaddr"\n", cbase + aliased_offset); } else if ( csize == SZ_128K ) printk(XENLOG_WARNING - "GICv2: GICC size=%#"PRIx64" but not aliased\n", + "GICv2: GICC size=%#"PRIpaddr" but not aliased\n", csize); gicv2.map_hbase = ioremap_nocache(hbase, PAGE_SIZE); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bb59ea94cd..db64009483 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -33,6 +33,7 @@ #include #include #include +#include #include /* Global state */ @@ -1376,8 +1377,14 @@ static void __init gicv3_dt_init(void) struct rdist_region *rdist_regs; int res, i; const struct dt_device_node *node = gicv3_info.node; + u64 dt_dbase, dt_rdist_base, dt_rdist_size, dt_cbase, dt_csize, dt_vbase, + dt_vsize; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_address(node, 0, &dt_dbase, NULL); + if ( res ) + panic("GICv3: Cannot find a valid distributor address\n"); + + res = translate_dt_address_size(&dt_dbase, NULL, &dbase, NULL); if ( res ) panic("GICv3: Cannot find a valid distributor address\n"); @@ -1393,9 +1400,15 @@ static void __init gicv3_dt_init(void) for ( i = 0; i < gicv3.rdist_count; i++ ) { - uint64_t rdist_base, rdist_size; + paddr_t rdist_base, rdist_size; + + res = dt_device_get_address(node, 1 + i, &dt_rdist_base, + &dt_rdist_size); + if ( res ) + panic("GICv3: No rdist base found for region %d\n", i); - res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size); + res = translate_dt_address_size(&dt_rdist_base, &dt_rdist_size, + &rdist_base, &rdist_size); if ( res ) panic("GICv3: No rdist base found for region %d\n", i); @@ -1418,10 +1431,20 @@ static void __init gicv3_dt_init(void) * provided. */ res = dt_device_get_address(node, 1 + gicv3.rdist_count, - &cbase, &csize); + &dt_cbase, &dt_csize); if ( !res ) + { dt_device_get_address(node, 1 + gicv3.rdist_count + 2, - &vbase, &vsize); + &dt_vbase, &dt_vsize); + + res = translate_dt_address_size(&dt_vbase, &dt_vsize, &vbase, &vsize); + if ( res ) + panic("GICv3: Invalid vbase/vsize provided\n"); + } + + res = translate_dt_address_size(&dt_cbase, &dt_csize, &cbase, &csize); + if ( res ) + panic("GICv3: Invalid cbase / csize provided\n"); } static int gicv3_iomem_deny_access(struct domain *d) diff --git a/xen/arch/arm/platforms/brcm.c b/xen/arch/arm/platforms/brcm.c index d481b2c60f..3e208a060d 100644 --- a/xen/arch/arm/platforms/brcm.c +++ b/xen/arch/arm/platforms/brcm.c @@ -40,7 +40,8 @@ static __init int brcm_get_dt_node(char *compat_str, u32 *reg_base) { const struct dt_device_node *node; - u64 reg_base_64; + paddr_t reg_base_64; + u64 dt_reg_base_64; int rc; node = dt_find_compatible_node(NULL, NULL, compat_str); @@ -50,13 +51,17 @@ static __init int brcm_get_dt_node(char *compat_str, return -ENOENT; } - rc = dt_device_get_address(node, 0, ®_base_64, NULL); + rc = dt_device_get_address(node, 0, &dt_reg_base_64, NULL); if ( rc ) { dprintk(XENLOG_ERR, "%s: missing \"reg\" prop\n", __func__); return rc; } + rc = translate_dt_address_size(&dt_reg_base_64, NULL, ®_base_64, NULL); + if ( rc ) + return rc; + if ( dn ) *dn = node; diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index 6560507092..a3fcab92ac 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -42,8 +42,9 @@ static int exynos5_init_time(void) void __iomem *mct; int rc; struct dt_device_node *node; - u64 mct_base_addr; - u64 size; + paddr_t mct_base_addr; + paddr_t size; + u64 dt_mct_base_addr, dt_size; node = dt_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct"); if ( !node ) @@ -52,14 +53,19 @@ static int exynos5_init_time(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &mct_base_addr, &size); + rc = dt_device_get_address(node, 0, &dt_mct_base_addr, &dt_size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos4210-mct\"\n"); return -ENXIO; } - dprintk(XENLOG_INFO, "mct_base_addr: %016llx size: %016llx\n", + rc = translate_dt_address_size(&dt_mct_base_addr, &dt_size, &mct_base_addr, + &size); + if ( rc ) + return rc; + + dprintk(XENLOG_INFO, "mct_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", mct_base_addr, size); mct = ioremap_nocache(mct_base_addr, size); @@ -97,8 +103,9 @@ static int __init exynos5_smp_init(void) struct dt_device_node *node; void __iomem *sysram; char *compatible; - u64 sysram_addr; - u64 size; + u64 dt_sysram_addr, dt_size; + paddr_t sysram_addr; + paddr_t size; u64 sysram_offset; int rc; @@ -125,13 +132,18 @@ static int __init exynos5_smp_init(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &sysram_addr, &size); + rc = dt_device_get_address(node, 0, &dt_sysram_addr, &dt_size); if ( rc ) { dprintk(XENLOG_ERR, "Error in %s\n", compatible); return -ENXIO; } - dprintk(XENLOG_INFO, "sysram_addr: %016llx size: %016llx offset: %016llx\n", + + rc = translate_dt_address_size(&dt_sysram_addr, &dt_size, &sysram_addr, &size); + if ( rc ) + return rc; + + dprintk(XENLOG_INFO, "sysram_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr" offset: %016llx\n", sysram_addr, size, sysram_offset); sysram = ioremap_nocache(sysram_addr, size); @@ -189,10 +201,11 @@ static int exynos5_cpu_power_up(void __iomem *power, int cpu) return 0; } -static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) +static int exynos5_get_pmu_baseandsize(paddr_t *power_base_addr, paddr_t *size) { struct dt_device_node *node; int rc; + u64 dt_power_base_addr, dt_size; static const struct dt_device_match exynos_dt_pmu_matches[] = { DT_MATCH_COMPATIBLE("samsung,exynos5250-pmu"), @@ -208,14 +221,19 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) return -ENXIO; } - rc = dt_device_get_address(node, 0, power_base_addr, size); + rc = dt_device_get_address(node, 0, &dt_power_base_addr, &dt_size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos5XXX-pmu\"\n"); return -ENXIO; } - dprintk(XENLOG_DEBUG, "power_base_addr: %016llx size: %016llx\n", + rc = translate_dt_address_size(&dt_power_base_addr, &dt_size, + power_base_addr, size); + if ( rc ) + return rc; + + dprintk(XENLOG_DEBUG, "power_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", *power_base_addr, *size); return 0; @@ -223,8 +241,8 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) static int exynos5_cpu_up(int cpu) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *power; int rc; @@ -256,8 +274,8 @@ static int exynos5_cpu_up(int cpu) static void exynos5_reset(void) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *pmu; int rc; diff --git a/xen/arch/arm/platforms/sunxi.c b/xen/arch/arm/platforms/sunxi.c index e8e4d88bef..7027170b68 100644 --- a/xen/arch/arm/platforms/sunxi.c +++ b/xen/arch/arm/platforms/sunxi.c @@ -34,6 +34,7 @@ static void __iomem *sunxi_map_watchdog(bool *new_wdt) { void __iomem *wdt; struct dt_device_node *node; + u64 dt_wdt_start, dt_wdt_len; paddr_t wdt_start, wdt_len; bool _new_wdt = false; int ret; @@ -50,7 +51,15 @@ static void __iomem *sunxi_map_watchdog(bool *new_wdt) return NULL; } - ret = dt_device_get_address(node, 0, &wdt_start, &wdt_len); + ret = dt_device_get_address(node, 0, &dt_wdt_start, &dt_wdt_len); + if ( ret ) + { + dprintk(XENLOG_ERR, "Cannot read watchdog register address\n"); + return NULL; + } + + ret = translate_dt_address_size(&dt_wdt_start, &dt_wdt_len, &wdt_start, + &wdt_len); if ( ret ) { dprintk(XENLOG_ERR, "Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 1f26f67b90..da64aeec88 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -220,12 +220,19 @@ static void __init dt_unreserved_regions(paddr_t s, paddr_t e, for ( i = first; i < nr ; i++ ) { + u64 dt_r_s, dt_r_e; paddr_t r_s, r_e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &r_s, &r_e ) < 0 ) + if ( fdt_get_mem_rsv(device_tree_flattened, i, &dt_r_s, &dt_r_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; + else + { + if ( translate_dt_address_size(&dt_r_s, &dt_r_e, &r_s, &r_e) ) + panic("Invalid address or size provided\n"); + } + r_e += r_s; /* fdt_get_mem_rsv returns length */ if ( s < r_e && r_s < e ) @@ -500,14 +507,21 @@ static paddr_t __init consider_modules(paddr_t s, paddr_t e, for ( ; i < mi->nr_mods + nr; i++ ) { + u64 dt_mod_s, dt_mod_e; paddr_t mod_s, mod_e; if ( fdt_get_mem_rsv(device_tree_flattened, i - mi->nr_mods, - &mod_s, &mod_e ) < 0 ) + &dt_mod_s, &dt_mod_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; + else + { + if ( translate_dt_address_size(&dt_mod_s, &dt_mod_e, &mod_s, &mod_e) ) + panic("Invalid address or size provided\n"); + } + /* fdt_get_mem_rsv returns length */ mod_e += mod_s; diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c index 43aaf02e18..38cc19410f 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -26,6 +26,7 @@ #include #include #include +#include static struct exynos4210_uart { unsigned int baud, clock_hz, data_bits, parity, stop_bits; @@ -303,7 +304,8 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, const char *config = data; struct exynos4210_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; + u64 dt_addr, dt_size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -316,7 +318,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, uart->parity = PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_address(dev, 0, &dt_addr, &dt_size); if ( res ) { printk("exynos4210: Unable to retrieve the base" @@ -324,6 +326,10 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, return res; } + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) + return res; + res = platform_get_irq(dev, 0); if ( res < 0 ) { diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 58d0ccd889..e62362db2f 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -35,6 +35,7 @@ #include #ifdef CONFIG_HAS_DEVICE_TREE #include +#include #endif #ifdef CONFIG_X86 #include @@ -42,8 +43,8 @@ static struct ns16550 { int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq; - u64 io_base; /* I/O port or memory-mapped I/O address. */ - u64 io_size; + paddr_t io_base; /* I/O port or memory-mapped I/O address. */ + paddr_t io_size; int reg_shift; /* Bits to shift register offset by */ int reg_width; /* Size of access to use, the registers * themselves are still bytes */ @@ -1747,6 +1748,7 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, struct ns16550 *uart; int res; u32 reg_shift, reg_width; + u64 dt_io_base, dt_io_size; uart = &ns16550_com[0]; @@ -1757,7 +1759,12 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); + res = dt_device_get_address(dev, 0, &dt_io_base, &dt_io_size); + if ( res ) + return res; + + res = translate_dt_address_size(&dt_io_base, &dt_io_size, &uart->io_base, + &uart->io_size); if ( res ) return res; diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c index d6a5d59aa2..e606c3ef1e 100644 --- a/xen/drivers/char/omap-uart.c +++ b/xen/drivers/char/omap-uart.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -324,7 +325,8 @@ static int __init omap_uart_init(struct dt_device_node *dev, struct omap_uart *uart; u32 clkspec; int res; - u64 addr, size; + u64 dt_addr, dt_size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -344,7 +346,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_address(dev, 0, &dt_addr, &dt_size); if ( res ) { printk("omap-uart: Unable to retrieve the base" @@ -352,6 +354,10 @@ static int __init omap_uart_init(struct dt_device_node *dev, return res; } + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) + return res; + res = platform_get_irq(dev, 0); if ( res < 0 ) { diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index be67242bc0..23037405e1 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -258,14 +259,15 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev, { const char *config = data; int res; - u64 addr, size; + paddr_t addr, size; + u64 dt_addr, dt_size; if ( strcmp(config, "") ) { printk("WARNING: UART configuration is not supported\n"); } - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_address(dev, 0, &dt_addr, &dt_size); if ( res ) { printk("pl011: Unable to retrieve the base" @@ -273,6 +275,10 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev, return res; } + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) + return res; + res = platform_get_irq(dev, 0); if ( res < 0 ) { diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 2fccafe340..c16cac836a 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -28,6 +28,7 @@ #include #include #include +#include #define scif_readb(uart, off) readb((uart)->regs + (off)) #define scif_writeb(uart, off, val) writeb((val), (uart)->regs + (off)) @@ -311,14 +312,15 @@ static int __init scif_uart_init(struct dt_device_node *dev, const char *config = data; struct scif_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; + u64 dt_addr, dt_size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &scif_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_address(dev, 0, &dt_addr, &dt_size); if ( res ) { printk("scif-uart: Unable to retrieve the base" @@ -326,6 +328,10 @@ static int __init scif_uart_init(struct dt_device_node *dev, return res; } + res = translate_dt_address_size(&dt_addr, &dt_size, &addr, &size); + if ( res ) + return res; + res = platform_get_irq(dev, 0); if ( res < 0 ) { diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 0a514821b3..5ae180a4cc 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -73,8 +73,8 @@ /* Xen: Helpers to get device MMIO and IRQs */ struct resource { - u64 addr; - u64 size; + paddr_t addr; + paddr_t size; unsigned int type; }; @@ -96,12 +96,17 @@ static struct resource *platform_get_resource(struct platform_device *pdev, */ static struct resource res; int ret = 0; + u64 dt_addr, dt_size; res.type = type; switch (type) { case IORESOURCE_MEM: - ret = dt_device_get_address(pdev, num, &res.addr, &res.size); + ret = dt_device_get_address(pdev, num, &dt_addr, &dt_size); + + if ( !ret ) + ret = translate_dt_address_size(&dt_addr, &dt_size, &res.addr, + &res.size); return ((ret) ? NULL : &res); @@ -169,7 +174,7 @@ static void __iomem *devm_ioremap_resource(struct device *dev, ptr = ioremap_nocache(res->addr, res->size); if (!ptr) { dev_err(dev, - "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n", + "ioremap failed (addr 0x%"PRIpaddr" size 0x%"PRIpaddr")\n", res->addr, res->size); return ERR_PTR(-ENOMEM); } diff --git a/xen/include/xen/serial.h b/xen/include/xen/serial.h index f0aff7ea76..0b326e22fd 100644 --- a/xen/include/xen/serial.h +++ b/xen/include/xen/serial.h @@ -34,7 +34,7 @@ enum serial_port_state { struct vuart_info { paddr_t base_addr; /* Base address of the UART */ - unsigned long size; /* Size of the memory region */ + paddr_t size; /* Size of the memory region */ unsigned long data_off; /* Data register offset */ unsigned long status_off; /* Status register offset */ unsigned long status; /* Ready status value */ From patchwork Thu Dec 15 19:32:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F54FC4332F for ; Thu, 15 Dec 2022 19:33:21 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463755.722044 (Exim 4.92) (envelope-from ) id 1p5tyh-0007XK-W3; Thu, 15 Dec 2022 19:33:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463755.722044; Thu, 15 Dec 2022 19:33:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyh-0007X9-Ry; Thu, 15 Dec 2022 19:33:11 +0000 Received: by outflank-mailman (input) for mailman id 463755; Thu, 15 Dec 2022 19:33:10 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyg-0006KU-IG for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:10 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2080.outbound.protection.outlook.com [40.107.92.80]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 4dc8bd46-7caf-11ed-8fd3-01056ac49cbb; Thu, 15 Dec 2022 20:33:09 +0100 (CET) Received: from DM6PR13CA0068.namprd13.prod.outlook.com (2603:10b6:5:134::45) by CH0PR12MB5300.namprd12.prod.outlook.com (2603:10b6:610:d7::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.11; Thu, 15 Dec 2022 19:33:06 +0000 Received: from DS1PEPF0000E645.namprd02.prod.outlook.com (2603:10b6:5:134:cafe::2) by DM6PR13CA0068.outlook.office365.com (2603:10b6:5:134::45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:06 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E645.mail.protection.outlook.com (10.167.17.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.8 via Frontend Transport; Thu, 15 Dec 2022 19:33:05 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:05 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:33:03 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4dc8bd46-7caf-11ed-8fd3-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nlM4cxQLfveT1rLygMd3K8Sj3cPltpuN/HPlMjnpts0qqsFkBmBt0Yp+23bh0c8qoP6vey2d7n7a166dOIwC1LkRS1Ly39IHc8fiXDQx+AP4r4XP1135TeinWZ1KeTGBxgKmG46Uv8063CeWB3+ASZfSZxqeWI38XaWKvSm2H/3xI2bmWGQZlKauvo1b6wyUbp4MGSIvSGMD2st5xTYbHa2O0HfKXX0x2H3L4R85bgz5rZr5LJ6acP+fOwCBbBb/ghQV18OMHetEHS0j8DEW3oOlal1RejEpH+m9rp9XkeV2kIj26xRjWKWrO7lXW6qUkv2HfHJRFE01rtWJ0Gjj+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sXUF4c1Lukzt7sJNL7fbo/yzZzcxYKrF0RRegx1oLLY=; b=ZwkfA+h49DaLDMWYOlMqzy7whUxpkO2wfK/N04dyYbmyPSmJ/2YzK2Ni6SpO/VTqJky+ZwroJKVRLeGNxX5eSzU+HqtxTs4RKQrR32tWqsg+EetRMe3wCK41FxxhTc14PqIX6f+98y/ZfmU8iY3fzJlta2tqbV/yLMQy4RNgmnmtEbUala9fuHJUdwotjcBxx9AOuSOCTwRL+Hy4Ukn+2AJYRlJ7YvTQ11842rr5v0DChfKGfb5Ntw77Vo0tnd1k1jYkZGrSZavzQ3kGMx7dLNF4g2sC8wnpEa94XFaEgl8yR8W1dFYNhM5YsoJywA4+fFBoSYPoXyL9EWYckJavDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sXUF4c1Lukzt7sJNL7fbo/yzZzcxYKrF0RRegx1oLLY=; b=g2ELtZu8gIv2LPXFqAE7F/RPfdjAjDzdzh9XSe/iD9zxxvCsJAXIHqQ49/8HnudsA0gg1dlZqTiwnzfPkXoC0Mqx9GrBx4gRuaH0pK0Ugn2JDvdUMghZdsh0numbeq08k7I24+/Op+nV0n0NG8ZMxcLpUHwcIHqQExSSDcajbsE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 5/9] xen/arm: Use 'PRIpaddr' to display 'paddr_t' variable Date: Thu, 15 Dec 2022 19:32:41 +0000 Message-ID: <20221215193245.48314-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E645:EE_|CH0PR12MB5300:EE_ X-MS-Office365-Filtering-Correlation-Id: eb2d1935-5f7d-4a7c-9f4a-08daded33067 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PsCFjAqXsuhOr2cOdhzmxp2ZqI/Zsx0AD7tYk2OldYxnfdff5JmtThzxAS+yMwnYV9zczCkhLDJ5uMivhvEw20hmwVY/BpASKhMef90vY5zTLiW4hjAqTF3ytvPVDEz94XnuPm7OxwwyONCuhmEM7KDGZetUHlwjfKPTlbnIACu/MUobp/H9pxSpWpp3Kao2QGjh14kepN+FJMPDmqDrOwcXWiWGL1NZnGGqBtVdZx8PTrDPxMZp8YjfnJEBFsXIydfm5ujVaGxjF5Lq9YhUPyZiCWyCW5ak7kjGUT52MqDj4IbjSqyU9NxnrUVfV3BM4ZYK+njxkohvDTlGRmGdgBX1fCx1vS3DISF1we4TWIdvr+gBS3UcguRdOgvt6PBVxtGjGQjjaMeu/lt2F1YaxGNFLTwdLZl3OQqIWASHYuCEnfIvoqnZEWsPslAAG4ftCNPBw6JGVMlPirqjizCj1b8973SRWgOZLDihoNHgbsuV4faS7or9iiLk75ASe7SLnhTxCe8SzYYY6nC3sGidVrC+CZybomU/DcW3uDmfa3k8PfsJhNNiBQ9LsPRfzgQoda0nA7zOSrI55dWaGjQ5m9vRV7h5e40SMdjwixBSWvHdPIDD92MRXaJ2OJ8j6aUPHuiHt2hk3ODmlfsaiA0z5uumWsa9RUrxKyYHpOyg8V/0Dw7nd+9OPU3e0eYcixj708gRJmxGdyAwtsb2q4P4CsAJHvRJyyZCZe1kTTRfBtM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(46966006)(40470700004)(36840700001)(36756003)(82310400005)(8676002)(86362001)(2906002)(26005)(336012)(186003)(40480700001)(478600001)(41300700001)(2616005)(4326008)(70586007)(1076003)(103116003)(5660300002)(426003)(47076005)(8936002)(83380400001)(40460700003)(70206006)(6916009)(6666004)(54906003)(316002)(81166007)(82740400003)(36860700001)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:05.7128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb2d1935-5f7d-4a7c-9f4a-08daded33067 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E645.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5300 One should use 'PRIpaddr' to display 'paddr_t' variables. This may either be PRIx32 or PRIx64 depending of the type of architecture. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/domain_build.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 1bb97cd337..c537514a52 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1325,7 +1325,7 @@ static int __init make_memory_node(const struct domain *d, dt_dprintk("Create memory node\n"); /* ePAPR 3.4 */ - snprintf(buf, sizeof(buf), "memory@%"PRIx64, mem->bank[i].start); + snprintf(buf, sizeof(buf), "memory@%"PRIpaddr, mem->bank[i].start); res = fdt_begin_node(fdt, buf); if ( res ) return res; @@ -1393,7 +1393,7 @@ static int __init make_shm_memory_node(const struct domain *d, __be32 *cells; unsigned int len = (addrcells + sizecells) * sizeof(__be32); - snprintf(buf, sizeof(buf), "xen-shmem@%"PRIx64, mem->bank[i].start); + snprintf(buf, sizeof(buf), "xen-shmem@%"PRIpaddr, mem->bank[i].start); res = fdt_begin_node(fdt, buf); if ( res ) return res; @@ -2739,7 +2739,7 @@ static int __init make_gicv2_domU_node(struct kernel_info *kinfo) /* Placeholder for interrupt-controller@ + a 64-bit number + \0 */ char buf[38]; - snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, + snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIpaddr, vgic_dist_base(&d->arch.vgic)); res = fdt_begin_node(fdt, buf); if ( res ) @@ -2795,7 +2795,7 @@ static int __init make_gicv3_domU_node(struct kernel_info *kinfo) char buf[38]; unsigned int i, len = 0; - snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, + snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIpaddr, vgic_dist_base(&d->arch.vgic)); res = fdt_begin_node(fdt, buf); @@ -2881,7 +2881,7 @@ static int __init make_vpl011_uart_node(struct kernel_info *kinfo) /* Placeholder for sbsa-uart@ + a 64-bit number + \0 */ char buf[27]; - snprintf(buf, sizeof(buf), "sbsa-uart@%"PRIx64, d->arch.vpl011.base_addr); + snprintf(buf, sizeof(buf), "sbsa-uart@%"PRIpaddr, d->arch.vpl011.base_addr); res = fdt_begin_node(fdt, buf); if ( res ) return res; From patchwork Thu Dec 15 19:32:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7C4FC4332F for ; Thu, 15 Dec 2022 19:33:23 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463757.722054 (Exim 4.92) (envelope-from ) id 1p5tyl-0007sh-6N; Thu, 15 Dec 2022 19:33:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463757.722054; Thu, 15 Dec 2022 19:33:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyl-0007sY-3D; Thu, 15 Dec 2022 19:33:15 +0000 Received: by outflank-mailman (input) for mailman id 463757; Thu, 15 Dec 2022 19:33:13 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyj-0006KU-Dg for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:13 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2088.outbound.protection.outlook.com [40.107.244.88]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 4f6c91e9-7caf-11ed-8fd3-01056ac49cbb; Thu, 15 Dec 2022 20:33:12 +0100 (CET) Received: from DM6PR06CA0089.namprd06.prod.outlook.com (2603:10b6:5:336::22) by IA0PR12MB7700.namprd12.prod.outlook.com (2603:10b6:208:430::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.11; Thu, 15 Dec 2022 19:33:08 +0000 Received: from DM6NAM11FT115.eop-nam11.prod.protection.outlook.com (2603:10b6:5:336:cafe::c6) by DM6PR06CA0089.outlook.office365.com (2603:10b6:5:336::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:08 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT115.mail.protection.outlook.com (10.13.173.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:08 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:08 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 11:33:07 -0800 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:33:06 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4f6c91e9-7caf-11ed-8fd3-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l2CbNcTkHHroQ412Y+DjHJ6ZfeiaVQOwgLAwOX4xgS8Dmfmu8/Q1M21nbRu/s6iDO4b96LFspdflhc5esq0G4Nl1XMZqb2lrH1G9chlxf0bVM7gO/7CUJAl5Rb7HvopnK5b4jVCboKv7vWSpRhac+D24FAtc5Tyjr/AqESll6zDtJQJDftPYDHpTon0Sw5ouC77y/SjVTVGRE2KWTuoN9sfxxsbFyAy9YPIJsFkLle20qEayJp63dsaClaDODI67zJpmLx/bKoJlkNDhn0sXU2nMPjkhERoY0+9RxGDFoOPWYpsa4xhUBUhetFb3bTM8UoPxw1II+EOctub6WaySrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0qkW8svLr8Mc6M3M8zGUIB1kFr46uVAUu0xQ2OTvK9k=; b=BAg95cLIQ9esNbRE1aG3NPfzeI4g73hP6A1yyjAYq3QgoJrYJHQjb4BuOL1IMNlOUdmnvkCSbb28VCUYtBjryfoNFRknvvXVwulgw3FnbBzSSg/5RXhT15kEr5TqqMuyW8zoDxQjTYMhaO7J2hsCQzg3ZhjJGSVzUBW0rrQnw1lAPUes+vRnt6VdpX4LdO0PvgwPWi2uLg49vuCqXGmyNYYAcWQe+c1y9WnwysOt8UWVxUod8gw4w58fghVIJk4iKnM7koYWRQkQfTeMJObSV2Fq5ZEa7qbJpTX8d2AV2cy5fS4SCrOH4zC8i5YwMuQKgEMrHeOIMl0mDTQ2AMFyzQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0qkW8svLr8Mc6M3M8zGUIB1kFr46uVAUu0xQ2OTvK9k=; b=Aj12EsXrQGmXuWjeBblO/d2GGA0yHwyHwFyDyXHwVZQU2v+jApo9kUGOCwAJWTMQRxZp+BG5vEAY+5uLchYzK4I5fYtcfncUVzVDFQt5cyAUkDG4sD0OEfGDjyNTC0EPH38iGwX2bS99eLueTiGDFo5m91bG0uGcfh3bNWhIVnI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 6/9] xen/arm: Use 'u64' to represent 'unsigned long long' Date: Thu, 15 Dec 2022 19:32:42 +0000 Message-ID: <20221215193245.48314-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT115:EE_|IA0PR12MB7700:EE_ X-MS-Office365-Filtering-Correlation-Id: b9dc1ff5-ce67-438d-fa59-08daded33216 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hcI8wzITBlIYSsQbueLKolg6oqmYV27f0+Sr74em5i1+1P5cKtAOmjznWtO1EftXHZxKq/FiXce7TLTdaDCiPpaM+AVf+iubHSV6mO5j9f/O3OgpHwT/zmXpPN/YHzci0S+mRu1prf7WyEf2Hh0MK+ARpcVfSz5CMb5aEzvPsiY5K7C+ADHxyCC0V/boFIBX6nFnPiJZ1ZLa6rMsLd7BzcDvgY9RJn6JGMRbLJ5ZtCETcwxjD7TM5FiiJk5UXBCdU2svo+Q6dhCpqRK4De3rJf3fcalhrCzYNQ07ZdmTbR53AEL4tJ6D3DC6cazlk+SAekY6LUVj4xZo1ZmE+EYqFVTdwqPwtCEZRJIc4B435C0Ea17U5qqIGI7vumbVPHS22PHWIVudPqu9yULKXXPu702MyZypOR08TBpL10+zFPjF0LcX4yxDG04gSFlT3Wij/+a4yDe63VY+B6Jq50p3t4uEcPqHDBaEKzjdJCgWuM39xu8r6jSBgN+bCilEcph6YXciSPnz6iVTnj6hE2O+fUBLCSdWirx6SkHU+s92SHEYxWrB8FTewFnPbDEtjcrsjoIty9UcWRvZatJajKuQVWsNb9O0ozZBBi/n1YiBabUefJE7ax58/PwMYl0mQ+kEM0PNmy5A/mQ51PBDa/0V1JAhe/0aS67Xr+c41hnltNxytOLm1iRtCM0gU8/5hBVIVvqZ+6OteQ/x7xYHR12lIXLeVFBISVkFw0/2xqA/nmvNU6J0iGzDfdI6YEDCb7HjzWDelFgwKGpPoxYAuPv+7Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(39860400002)(376002)(346002)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(36756003)(2906002)(26005)(8676002)(70586007)(186003)(40480700001)(70206006)(41300700001)(478600001)(336012)(2616005)(86362001)(1076003)(103116003)(4326008)(47076005)(426003)(8936002)(83380400001)(40460700003)(5660300002)(4744005)(6666004)(6916009)(54906003)(316002)(36860700001)(82740400003)(81166007)(356005)(223183001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:08.5397 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9dc1ff5-ce67-438d-fa59-08daded33216 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7700 bankbase, banksize and bankend are used to hold values of type 'unsigned long long'. Thus, one should use 'u64' instead of 'paddr_t' (which may be either u64 or u32 depending on the architecture). Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/domain_build.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index c537514a52..e968b9812d 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1741,9 +1741,9 @@ static int __init find_domU_holes(const struct kernel_info *kinfo, struct meminfo *ext_regions) { unsigned int i; - paddr_t bankend; - const paddr_t bankbase[] = GUEST_RAM_BANK_BASES; - const paddr_t banksize[] = GUEST_RAM_BANK_SIZES; + uint64_t bankend; + const uint64_t bankbase[] = GUEST_RAM_BANK_BASES; + const uint64_t banksize[] = GUEST_RAM_BANK_SIZES; int res = -ENOENT; for ( i = 0; i < GUEST_RAM_BANKS; i++ ) From patchwork Thu Dec 15 19:32:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7134C4167B for ; Thu, 15 Dec 2022 19:33:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463765.722077 (Exim 4.92) (envelope-from ) id 1p5tyq-0000QU-CP; Thu, 15 Dec 2022 19:33:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463765.722077; Thu, 15 Dec 2022 19:33:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyq-0000QE-71; Thu, 15 Dec 2022 19:33:20 +0000 Received: by outflank-mailman (input) for mailman id 463765; Thu, 15 Dec 2022 19:33:19 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyo-0006KU-Tk for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:19 +0000 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2045.outbound.protection.outlook.com [40.107.220.45]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 52b2f647-7caf-11ed-8fd3-01056ac49cbb; Thu, 15 Dec 2022 20:33:18 +0100 (CET) Received: from DS7PR07CA0017.namprd07.prod.outlook.com (2603:10b6:5:3af::14) by DS7PR12MB6264.namprd12.prod.outlook.com (2603:10b6:8:94::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12; Thu, 15 Dec 2022 19:33:12 +0000 Received: from DS1PEPF0000E643.namprd02.prod.outlook.com (2603:10b6:5:3af:cafe::6f) by DS7PR07CA0017.outlook.office365.com (2603:10b6:5:3af::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.13 via Frontend Transport; Thu, 15 Dec 2022 19:33:11 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E643.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.9 via Frontend Transport; Thu, 15 Dec 2022 19:33:11 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:10 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 11:33:10 -0800 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:33:09 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 52b2f647-7caf-11ed-8fd3-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dqUfJaGLBhYdgVd71pA74NpcmBICD0/sol8EoHZkdTt8WwltGKmf3j4tFZ4IBhAD02a4M/8LDfozJU+2bCUMl+mR8DrRSw2sLplTnEuNtQOTq9+fGjjwCcG0NHGPVGX8Mwk9gN8Zt7rJXe95N90alxAqUtkXP9gya7dW4xZC0rT4TaoyNv3jewoJXQEieXR1KRyeGU4JpERAcK0sV2OWSn7OXjAItcKQDbDgqSE4Zol4XDGF3TWmUR1LnajKYFFbDq4ehK+d9ohJ7FG2atBr+RylLNRgfrFjEPXD9mVsChOyLpYEvYZNkX3b2WaUiKKmn834nRsbohHJDO2sHGyNuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Z5+olvGyXYR/FH3N6U5mKGmd6Dy3PG3BDHmi9oMXULE=; b=N+GHsaFKPeXrFU99lw1lcl2dYbKoga//yfaH/nHSOYNicsfTTazahN2f/7Gy+KxKokom8zboF31bw4LFYz2dTHRy2Q58hULPLCDTdNU3SKAqrmUZyCIlMPtWePkOJSIjcdxUl2GZkwNRgl9rMofzmQIlmlKJSEZEh3/KbQgRKh1EiyQDXpCqPgo88uIttgylcwpRtzAgSAHfmIV6tWwJex2gKA8JfRH9/ABtw3HysPhJmsIAfmUYXoO2JW4IhWQA4BiTRIwo76HdQsDCibsj2WqpMpVInYnX9BJNv1PTZyVWgcJix/GehaXzM2sTJ0h8oCIS911E+6GzqvFQA/AECQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Z5+olvGyXYR/FH3N6U5mKGmd6Dy3PG3BDHmi9oMXULE=; b=DGLCxaJGqU5PM+ILngrxnd2Ow6RIpQWzBUn39oRXOqo+r/NF0MzXFjLz8vtoLFQ79ix2alP7bfzY4MC71ijapKIJnbqMnuanolTTGYk5p3+2hFCOQteqotAegZL5x9pfuWhpWeMeeShO0U755U9Zzl7kMDziOT2WoVqNc643sTs= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 7/9] xen/arm: Restrict zeroeth_table_offset for ARM_64 Date: Thu, 15 Dec 2022 19:32:43 +0000 Message-ID: <20221215193245.48314-8-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E643:EE_|DS7PR12MB6264:EE_ X-MS-Office365-Filtering-Correlation-Id: a8b3080f-6fda-40ec-c39a-08daded333e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lcZ6K2t9pLv3ohU+b+89CbGpj85HyW1ynD3jSgcPbwiOCYry+86Yd1scvXlWc7fovuEgcKA4K5GBSo+vSS4fhdBRZcmZeYvbw3Pi039W/SM9gRpTPw/ZCpcUd6VROeg0fzp32xKPJ3T57F9Hd0+oBtvq/iKWwRQwmnsuUF3tAENtFjn+GcQEL/sO/2pJBpfMdEWPBUe/VRX6kKYyuK5WOUwkVAoPEHLXVpS7J+B1lJTdPW9SaqSF1a/k4slCm/mP486F4QuXxQYzUWL5XclS+E3IkabHmLGjin2PJBuw6XfCNUSGFrqU9V7/ShS6oHsKRefaEXIk9ijbw4GAD/rFe4OPZQVIP4BbKr4J8egURg9uA4x654NznJFNQ/2J6wc3RcFSxN8TRY29dW3ydsQKt2kv4sOA/c5wf0H/ismKjbQGJb4R7qfuXPrX2r2iLqulwJ1VmbaEOvL2RQZoiHf2K/5YRnmLhRGnO6WI+bvHW9bbyeLudEwRQ93sP2Hc7iliC5uoYeeRkjjmVw+1AhN4CK1UpaacPuOkVUxbJB625Z3gpYrLkxFbc1e90ssPUmaZ1WNdEx+7ouCtY9VR++G/zPADPb90zq01OaYRS6PLJJCpkRXhomyh2coH1SYZ/HJmbM1q3NzPVrb6CmyqgVB2W33317sz0+9urTvUHh699ga1xvOZ6OAmPiftgkbdrCmWFD+i8Je7cT9TitUL0XmQp1SKeLmHm8+Jhw5bTk13Lvk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(83380400001)(36860700001)(426003)(47076005)(40460700003)(86362001)(81166007)(356005)(40480700001)(2906002)(5660300002)(8936002)(41300700001)(82310400005)(4326008)(6666004)(186003)(26005)(1076003)(2616005)(336012)(8676002)(316002)(70586007)(70206006)(54906003)(6916009)(478600001)(82740400003)(36756003)(103116003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:11.5792 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8b3080f-6fda-40ec-c39a-08daded333e6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E643.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6264 zeroeth_table_offset is not accessed for ARM_32. This is a left over of the following commit " commit 5fa6e9abfb11 Author: Ian Campbell Date: Thu Sep 18 01:09:48 2014 +0100 xen: arm: Implement variable levels in dump_pt_walk " Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/lpae.h | 10 ++++++++++ xen/arch/arm/mm.c | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpae.h index 3fdd5d0de2..35769debf9 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -161,6 +161,7 @@ static inline bool lpae_is_superpage(lpae_t pte, unsigned int level) #define lpae_set_mfn(pte, mfn) ((pte).walk.base = mfn_x(mfn)) /* Generate an array @var containing the offset for each level from @addr */ +#ifdef CONFIG_ARM_64 #define DECLARE_OFFSETS(var, addr) \ const unsigned int var[4] = { \ zeroeth_table_offset(addr), \ @@ -168,6 +169,15 @@ static inline bool lpae_is_superpage(lpae_t pte, unsigned int level) second_table_offset(addr), \ third_table_offset(addr) \ } +#else +#define DECLARE_OFFSETS(var, addr) \ + const unsigned int var[4] = { \ + 0, \ + first_table_offset(addr), \ + second_table_offset(addr), \ + third_table_offset(addr) \ + } +#endif /* * Standard entry type that we'll use to build Xen's own pagetables. diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 630175276f..be939fb106 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -184,7 +184,11 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, static const char *level_strs[4] = { "0TH", "1ST", "2ND", "3RD" }; const mfn_t root_mfn = maddr_to_mfn(ttbr); const unsigned int offsets[4] = { +#ifdef CONFIG_ARM_64 zeroeth_table_offset(addr), +#else + 0, +#endif first_table_offset(addr), second_table_offset(addr), third_table_offset(addr) From patchwork Thu Dec 15 19:32:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99F2FC3DA71 for ; Thu, 15 Dec 2022 19:33:30 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463766.722088 (Exim 4.92) (envelope-from ) id 1p5tyr-0000lW-Pk; Thu, 15 Dec 2022 19:33:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463766.722088; Thu, 15 Dec 2022 19:33:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyr-0000jy-IO; Thu, 15 Dec 2022 19:33:21 +0000 Received: by outflank-mailman (input) for mailman id 463766; Thu, 15 Dec 2022 19:33:20 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5typ-0006KU-Ts for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:20 +0000 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2077.outbound.protection.outlook.com [40.107.223.77]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 52d228ff-7caf-11ed-8fd3-01056ac49cbb; Thu, 15 Dec 2022 20:33:18 +0100 (CET) Received: from DM6PR13CA0057.namprd13.prod.outlook.com (2603:10b6:5:134::34) by MW4PR12MB6973.namprd12.prod.outlook.com (2603:10b6:303:20a::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.11; Thu, 15 Dec 2022 19:33:14 +0000 Received: from DM6NAM11FT085.eop-nam11.prod.protection.outlook.com (2603:10b6:5:134:cafe::4b) by DM6PR13CA0057.outlook.office365.com (2603:10b6:5:134::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:14 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT085.mail.protection.outlook.com (10.13.172.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:14 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:13 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:12 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:33:11 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 52d228ff-7caf-11ed-8fd3-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hP+x/fYpbSTGDzsUcpUpZlflZK+0iY5GOFu5hE37TGRwF8c2H/RgJrl9Th+selTDn6M9B6vi37bBeQXUAl9jC/fqsKjhS8p6XRZ4N5QSWB+OHjLrJiRL76bxMjmP3KrVY4dIi8WkcuR2xbIPbMsTTBAPXAprHR8tuDjBh7WG/ckk2gMHfbq5tZ3NK8L8veT4vCxXhPkqMxD2d+3+Mu6lZbH1yEsVS2g0OFTSgCkahu+wUXBkzqIzMXjZTWm3xvGTT0t87LL2WSleg1abZ7LbBbkJJ698NUmH5LH/tew+HrlM3QDRuPonA7ZpH6MrLEutLYFy/L5Z95fX03o3XLpuag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=eQPLuzeCeyz59DG1ehsn+YnT+/R316b2RCY1GeYq6m8=; b=KMsZL5WAxrpIPNivju+arLv7IxKAPtrW7WFPN9dlB3AbpGbZLJdiQGI4avGLwvd1BXaqh5gU0chYwBQtHs9m+6n+3insLq8b/L/11kQ/zfz/ZY3lKyCEdjSAEElGEGP/sKcKtftY4dk+q2Xe5nsZLd18ftTJgXxU4PbdLMQgQh8FM5EEsU/h7SOjNyf1hqoUUXXnf2E3NPIBC/a3vaGBjc6RjjnQkgaq4KiKac1LPyQ01NBNGY3ldmVac8DJD/f0oWQfMK8j8UQQdl4O12gC+z3Y2mZkr2v3BA7Gfn1LFwfP7J5zv1wdkBUL5splbaN8hf30R2mDkskt9cLyLEn1oQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eQPLuzeCeyz59DG1ehsn+YnT+/R316b2RCY1GeYq6m8=; b=sjb1r1t0l0Cpvx6v8KqNAFIeRXWMb+O8eugDyKWlC11upBL28ma+y3WOhifcB6k9j1w7IehnEbhPz6MMCnictaQA2jWMnGk3RL5tmpUMHZSXVWxjjeAVH8Zm8d1mLhDBa5K8Yq+MaWzo8Fz+nUIX/Eiw7ytGi247z7KFgNMEM2M= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr Date: Thu, 15 Dec 2022 19:32:44 +0000 Message-ID: <20221215193245.48314-9-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT085:EE_|MW4PR12MB6973:EE_ X-MS-Office365-Filtering-Correlation-Id: a056e9f1-c7dc-48d5-0034-08daded33581 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S0mUW6MG+5wZbROgtqtvMYcKi+zTiyjkojlyJ0rky6Ua4nxIR33VzC/uktuWMYPCrX+O0nLOaRxdLzAwrzTkpQwPedLkGfUMW9Wd+W7w19IdE+DwPGPsI+ndQzrArU+A2yzLyReTveDba6pwSpDg3piNEsNNeoPwFwbdWAtqvNkP9KnCl+QR+bDr3x54Bi0GwbX75K2fU19icj8+1hCx6sqoi0TyGhbTjaliUSbt2yiS1Yf7qn04MLcjl1AQxg0/qhP7UTL3IH0r/gHGsNfRuvOqbme8ZpCwm+TYVBH08gMM+O9TccXKh8mVgDWETONuh8f4PIoXXR8VKoKAINbaQUI6d6gtnCcWLR3UH6jHzXvBiG535Z41WwLgRrJcfDUs4APONOLN4R29IfWJsiS5sKR62fIn1CR401UqplT1hM61nWBVrOYo2XEPorMl8r1tKzt3dAVSNJ/I5rQ1PpqOWt28YvEHnndStkoyybAAEvjA0Fyjggg3Ql5z067nuLSSUQqCx7LxyAhsuzoJwr2LPX544XrZE3AmXqtj5L//WutNPZnnDv53wkPjATXNBV8kTtTtqNdAtYRM3FxfpzZNNIkQke/2r4GgCprNvX6icmZS8TucPEoelfndb4vSgO6JTaWRD0mnPg1IkHlIIqpPqJyR2NURyBWJUY224s0rmj0sxl+HEMAcxUcRWyug7Qs+Jt7IsXKFOsp0IKxH7PKEhiZTFW9z2k8ucdzihOLQDT4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199015)(40470700004)(36840700001)(46966006)(40460700003)(81166007)(356005)(36756003)(82740400003)(40480700001)(86362001)(103116003)(82310400005)(6666004)(316002)(70586007)(478600001)(186003)(26005)(2616005)(6916009)(54906003)(36860700001)(2906002)(47076005)(41300700001)(336012)(70206006)(4326008)(8676002)(8936002)(1076003)(5660300002)(426003)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:14.2677 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a056e9f1-c7dc-48d5-0034-08daded33581 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6973 1. Supersections are supported only for paddr greater than 32 bits. 2. Use 0 wherever physical addresses are right shifted for 32 bits. 3. Use PRIx64 to print u64 Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/guest_walk.c | 2 ++ xen/arch/arm/mm.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..4384068285 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -149,6 +149,7 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SECTION_SHIFT) - 1; *ipa = ((paddr_t)pte.sec.base << L1DESC_SECTION_SHIFT) | (gva & mask); } +#ifndef CONFIG_ARM_PA_32 else /* Supersection */ { mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; @@ -157,6 +158,7 @@ static bool guest_walk_sd(const struct vcpu *v, *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; } +#endif /* Set permissions so that the caller can check the flags by herself. */ if ( !pte.sec.ro ) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index be939fb106..3bc9894008 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -229,7 +229,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, pte = mapping[offsets[level]]; - printk("%s[0x%03x] = 0x%"PRIpaddr"\n", + printk("%s[0x%03x] = 0x%"PRIx64"\n", level_strs[level], offsets[level], pte.bits); if ( level == 3 || !pte.walk.valid || !pte.walk.table ) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 5ae180a4cc..522a478ccf 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -1184,7 +1184,12 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg = (p2maddr & ((1ULL << 32) - 1)); writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); + +#ifndef CONFIG_ARM_PA_32 reg = (p2maddr >> 32); +#else + reg = 0; +#endif if (stage1) reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); From patchwork Thu Dec 15 19:32:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13074504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B70E6C4332F for ; Thu, 15 Dec 2022 19:33:32 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.463772.722096 (Exim 4.92) (envelope-from ) id 1p5tyt-00017j-5Y; Thu, 15 Dec 2022 19:33:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 463772.722096; Thu, 15 Dec 2022 19:33:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyt-00016m-1N; Thu, 15 Dec 2022 19:33:23 +0000 Received: by outflank-mailman (input) for mailman id 463772; Thu, 15 Dec 2022 19:33:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p5tyr-0006KU-Tw for xen-devel@lists.xenproject.org; Thu, 15 Dec 2022 19:33:22 +0000 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5433116f-7caf-11ed-8fd3-01056ac49cbb; Thu, 15 Dec 2022 20:33:20 +0100 (CET) Received: from DM6PR13CA0070.namprd13.prod.outlook.com (2603:10b6:5:134::47) by MN2PR12MB4375.namprd12.prod.outlook.com (2603:10b6:208:24f::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12; Thu, 15 Dec 2022 19:33:17 +0000 Received: from DM6NAM11FT085.eop-nam11.prod.protection.outlook.com (2603:10b6:5:134:cafe::e2) by DM6PR13CA0070.outlook.office365.com (2603:10b6:5:134::47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.14 via Frontend Transport; Thu, 15 Dec 2022 19:33:17 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT085.mail.protection.outlook.com (10.13.172.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 19:33:17 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:16 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 13:33:15 -0600 Received: from xcbayankuma41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 13:33:14 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5433116f-7caf-11ed-8fd3-01056ac49cbb ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VO2Jz4urcfcPoETJvbY7uxfQc7XoTDgHMGVaN6fvrWIEjE//iVFsj2BGtoup6YpHFtDOmuF8g6Zy47ffmaRJnUqP8BeEx3OGQaA0msjVmXFJmPJfow7ZOalhKtpMAQVXlFc9IO2XsQuwpATzkBBh7SotRYOfzVwCuv7PM1tpNmUJ2am2//3PNfi0nzbio95FaK2CT9hHboKIxGUg1U31bkS1F7yIjHrghhv9R4lo8B+l0S6MUUVHcJR5QqbqT+vaqDs5Ol3mx2b9SP9gCyph+sDQxSdk/4E9HyqQSL3URxKs+GtB1m92RJXrFhrph/bAC5zIu4x6BIamXunj0ASc6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=q3BqTHje9hBwSDwZvyLDpmFskXeeCNNsKZktZznSD4Y=; b=F1WVlpnaJuODN/YZZK/ix9R5mEFShw5NZN21h5rSxHNsEbh77rEhjG6Pu7NAl2BSqzzSLrEcVoT1rigKdtHg9fFIng+ZuQ3tu3t7Vn6MxpusxoZ6HxwKR5cdH5fw3xdd9d9lA+kDwI1ZC7TpX9OPg4E4vKb3rUOH0enO7WnlyAZ5XIaZdaBDKIVN+zKl/S+uVcoG9yDqfnj/utRw+jH47uAaXAz4V6ld6GRQC/ji8k2YxknAZnISmWeuAUBbgvcl6dUCo5zI5DWB4RYsllf6qN4vdEzlRNqqh5jolZG/8059yqgG0H+W5LQXePP6EYrFPwokKBhSbdD3UIbDFHDAnw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q3BqTHje9hBwSDwZvyLDpmFskXeeCNNsKZktZznSD4Y=; b=49L99oWmO4asKf1o374DBqdOnvqDVT1Tvw5Z9ZQdZS9LpL5OPF9BqeEMz+UxIAx3ERUQIQivAwUC1xNA7VO1V2herdvW9UTtNS1pbHmrTe470nDwXtCq2hGlOE0QAcg2zTtNDGaYoOccyomVbCC3jIosuR0jxVVVmvqWB2ghSFE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 9/9] xen/arm: Introduce ARM_PA_32 to support 32 bit physical address Date: Thu, 15 Dec 2022 19:32:45 +0000 Message-ID: <20221215193245.48314-10-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT085:EE_|MN2PR12MB4375:EE_ X-MS-Office365-Filtering-Correlation-Id: def075e1-9b99-4987-1f62-08daded3372e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fs6f+1wUO93V5W1aAvxJBPIvS0u+5XT6xQE57/Z7Iya8/T46mETqO09cXWusAI6x2w7/Uirgy8x5WHJWZ+230IPxOIMcAvkmatQErzpXlgZxL+d/AFFCtLfLGApGb4DW2cEqTAksMo5Cjw345io7V3g21Xk+EzyT0ZrWjPT7ustE2y0IF5Ag3UD3oAg2rgj2qDDrAAVQF5m0n3g5MrDTRu2K5+UCUklP6LB6UYPU+s55xoQycobIf69wyQ1XVQBvp4X0ADJyxpFXbnPwTsTxu/x/9MGkKU8MRXzhgJn2l6w2bbxjN7U4BlvKYXVbDit0yK7BdAgzVPyXITfFGjNk8pcWREINxJ2wCcw3v1/g47M/htJ+jEjGYYLTg1nwYZ+lIAnpfo9hVmHe6yRolAo3Cn5KFdpSMH6HIQ/4oi4HqiamEgy34bTjdou4/PYaETN9J55L0xWwdMO58qiEORP2EuHqi4Bk0Et7XDiaYJ5O635EB3ePMreowiOqTwumvSnLdGI61vEtg1yteqm+WkCB9QTG8qDhPHp4+XoBN2/O6znC7kEvFhO5r1tndaSCsvJYT4EGvLIExgV4d8dkJ6wcoObshHDmUDPYg4U6FrMoLfqS2tpf++KtyeqVa8WIvDtAEkmfH01KLhp+vopcJoFdYqK/PoC6cYCy9CbiHMZ2QiZLQ/VmBV1KEfzAGSPVpN4evc8DnqvMA3Bxa2MYZaWERRausFdN/XfH/BZ0ezsCbto= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199015)(46966006)(40470700004)(36840700001)(36756003)(103116003)(356005)(2906002)(82740400003)(81166007)(40480700001)(82310400005)(8936002)(5660300002)(41300700001)(6916009)(40460700003)(47076005)(36860700001)(426003)(83380400001)(86362001)(478600001)(54906003)(4326008)(6666004)(1076003)(316002)(70586007)(2616005)(8676002)(26005)(186003)(336012)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 19:33:17.0800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: def075e1-9b99-4987-1f62-08daded3372e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4375 We have introduced a new config option to support 32 bit physical address. By default, it is disabled. ARM_PA_32 cannot be enabled on ARM_64 as the memory management unit works on 48bit physical addresses. On ARM_32, it can be used on systems where large page address extension is not supported. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Kconfig | 9 +++++++++ xen/arch/arm/include/asm/page-bits.h | 2 ++ xen/arch/arm/include/asm/types.h | 7 +++++++ 3 files changed, 18 insertions(+) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 239d3aed3c..aeb0f7252e 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -39,6 +39,15 @@ config ACPI config ARM_EFI bool +config ARM_PA_32 + bool "32 bit Physical Address" + depends on ARM_32 + default n + ---help--- + + Support 32 bit physical addresses. + If unsure, say N + config GICV3 bool "GICv3 driver" depends on !NEW_VGIC diff --git a/xen/arch/arm/include/asm/page-bits.h b/xen/arch/arm/include/asm/page-bits.h index 5d6477e599..8f4dcebcfd 100644 --- a/xen/arch/arm/include/asm/page-bits.h +++ b/xen/arch/arm/include/asm/page-bits.h @@ -5,6 +5,8 @@ #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 +#elif CONFIG_ARM_PA_32 +#define PADDR_BITS 32 #else #define PADDR_BITS 40 #endif diff --git a/xen/arch/arm/include/asm/types.h b/xen/arch/arm/include/asm/types.h index 083acbd151..f9595b9098 100644 --- a/xen/arch/arm/include/asm/types.h +++ b/xen/arch/arm/include/asm/types.h @@ -37,9 +37,16 @@ typedef signed long long s64; typedef unsigned long long u64; typedef u32 vaddr_t; #define PRIvaddr PRIx32 +#if defined(CONFIG_ARM_PA_32) +typedef u32 paddr_t; +#define INVALID_PADDR (~0UL) +#define PADDR_SHIFT BITS_PER_LONG +#define PRIpaddr PRIx32 +#else typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" +#endif typedef u32 register_t; #define PRIregister "08x" #elif defined (CONFIG_ARM_64)