From patchwork Sun Dec 18 05:14:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3D48C4332F for ; Sun, 18 Dec 2022 05:16:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XSVaGeD7j/DV4SAG0st5Qlm5YSVNUoepyqWAehxPzWs=; b=JjAL5ClfhEljbp 7uH+zibwJAvKPRMAFIrmfds5Ys6u+jn0jyA7UTYzJ/qcpPB0sCoRyqxCTSTHf9n4UE2XmsuqwOvrc 2PGwywRq2RMasQLF2CRT3YkVgU5Zmp+OzEeuqak1Ap9/yHVh0DdRe57t662XfR+OEVPRTVeI6Kt40 SAiJV1FZPodkW8EBj1hi68BVCfnhhIOAw29dpyszVLP0cqQO2C8ZKinqKYNVSfyo/zBnUorI0bDgJ H/GpXI/wLxiCjq9uILe4ZsbC3VcuFFrsErihkfTy8zz61WuiMP/r6in1paUIFpZBk5WhywJ6+EpGv h+0P60HA1HaBGVpV2d/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1W-00FuUy-Dw; Sun, 18 Dec 2022 05:15:42 +0000 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1J-00FuKU-PD for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:32 +0000 Received: by mail-pj1-x102a.google.com with SMTP id fa4-20020a17090af0c400b002198d1328a0so11674130pjb.0 for ; Sat, 17 Dec 2022 21:15:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fSSvNarkcX8fxYBT0hcpDCN4tMu56rqMEzf7f5+m+DY=; b=iLqdfLkStRaxHz+T3WwGYnUjZRwjQLDIM6smk/z9ggwXePajQv6m0ooG9QKQ0GWRTA wqdAAu0KvXiBq/eKd+yVFjDuOUwe+wF+VD0VTuWUEasfwUtJtRw5ySEbZg7q74TrfE6u MZTYLlVYskcnskHNAw1baY8qVMmQOP3ZU4bmyuRcOtD2UWIC/3lVpWyYigGECtFjYxAA 4CsfHveHyc6NYMba0olefWZFBbCxIl8BjdNDhdpoPfnEtcH1NOAn96086MnE1pOtjZ+n 89ChjXUU7yurmLWae+JylmBuTNf1ZGfFjVRK1xNYBkoPA4KWHOMd3fZEZ+bYF3tYsQeg y1yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fSSvNarkcX8fxYBT0hcpDCN4tMu56rqMEzf7f5+m+DY=; b=Y/yb9dUAWHhNr8Eb6Rm2B8xoCyO8NOt5VTAcjc2optegTv1rVDbcSYub8NY0Cu4SS3 FVBcYgyoAbL2rgaX+0xq6AwmjhmtXkngkDHx2vy1BRrS0OG32xS5AtIp9JdqNvZTvlaq jyebLk1Qg0BY146jLPemk19riDeb+aqWPaxVy2F5em4TID+kqBzchp36YeRUhMvNOQXs klK69DrvGEsJKLckWFVM3vf8aDlg0gck/DfxEtyvdmvvPTI0oQ4hq8ChPOdH2fj2L255 ImpYalDVFSwFEnUFz7PM3ljmU5P6JE00XJJDSk47Oe7PPAMgqlHFlPLS4IDayTlql95H wHeg== X-Gm-Message-State: ANoB5pnJ10DPugIaBPwlbbWeCiO7NT52JoFhJ+ynGgXFyK7IAAC2gvsE JFLJvvnr20dfO+vdWyCtqLy5kw== X-Google-Smtp-Source: AA0mqf7vb6+GyWqLL5OnXKgkL1qGpIo5stbUWTmlKYousX0ZRaRgIzvlA59WnLDwjmcjYLYidZRXJA== X-Received: by 2002:a17:90a:b891:b0:21d:5e73:d562 with SMTP id o17-20020a17090ab89100b0021d5e73d562mr37465528pjr.27.1671340528507; Sat, 17 Dec 2022 21:15:28 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:28 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 1/7] arm64/sysreg: Convert CCSIDR_EL1 to automatic generation Date: Sun, 18 Dec 2022 14:14:06 +0900 Message-Id: <20221218051412.384657-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211529_923767_6A09F1FD X-CRM114-Status: GOOD ( 10.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert CCSIDR_EL1 to automatic generation as per DDI0487I.a. The field definition is for case when FEAT_CCIDX is not implemented. Fields WT, WB, RA and WA are defined as per A.j since they are now reserved and may have UNKNOWN values in I.a, which the file format cannot represent. Signed-off-by: Akihiko Odaki Signed-off-by: Marc Zyngier Reviewed-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7d301700d1a9..910e960661d3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -425,7 +425,6 @@ #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) -#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..acc79b5ccf92 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -871,6 +871,17 @@ Sysreg SCXTNUM_EL1 3 0 13 0 7 Field 63:0 SoftwareContextNumber EndSysreg +Sysreg CCSIDR_EL1 3 1 0 0 0 +Res0 63:32 +Field 31:31 WT +Field 30:30 WB +Field 29:29 RA +Field 28:28 WA +Field 27:13 NumSets +Field 12:3 Associavity +Field 2:0 LineSize +EndSysreg + Sysreg CLIDR_EL1 3 1 0 0 1 Res0 63:47 Field 46:33 Ttypen From patchwork Sun Dec 18 05:14:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF13FC10F1E for ; Sun, 18 Dec 2022 05:16:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7OK1nLAZ2EALc9wMlY9e3/h4ZAHfXE56uDI/2DOZXXs=; b=baMqz23NKOsvTH gn59K53n0ZJQeJ6KuntDFGiIiyP/Fxjuo0d/Y0hoqEJMQlDhs/udZrnUbIR3btzA4ytdw/apsmiT/ 8tH6PzgbBpYCWpL1XBTLNRFaZntNRWptIDSbaPyfK2A7pZ1C3wO+LAvQjfSVcIuumk3uuThT+FlBM o5vhg2pcxw09/XNUB0fhO/LOmuOpMSbo1Ae+J4tprFbBQXGwUAxlyHvWXCOWAUK95KikYNOHbx+uc slOrvRI8EegZkn/zcmd4yQf54h4D5NBJcvXGgFwKXQBWSgLbIzCpP3fxdMZckVsH1/seSCmsHvTku Ig8P60j8PsNokgoyJxrg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1f-00FucF-Sa; Sun, 18 Dec 2022 05:15:52 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1N-00FuO1-SH for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:35 +0000 Received: by mail-pj1-x1029.google.com with SMTP id b13-20020a17090a5a0d00b0021906102d05so6056464pjd.5 for ; Sat, 17 Dec 2022 21:15:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fOI4ejQZZiODftrBSHrXI1yj065pP5UP36eyaXzR3dw=; b=5vOoY2ROQYHTbYM3+RnIE9hlmPwzzQgFUeowIh+C/4V9gTf+l5bnTa2QzkNUnqQwxr 3GgkF6GUjCXw9MZFqkdBaBeMYIL59Cc0WtqAI9/oj1HmwjGy3flLLlS8WOMO6Pbob/Gx jfGlhJe3VFYnBiWMGf8du0YwYHYTQB0gnZUmWqLr2GwB9S6eTRGdZdtbF+a+mxGQ8lVb 8Mj1VU5avG7zyE24Rk/OHZnHGBhit9avvW+NyeY4DKssVug5N7YvvKNSYQPL3FBzsHI8 0DgZwsBfWfirRYsZFPZKwCAEOdbAIL0GAH+UYx221RmJDoHsYlz8pxB7RMqDMZ1rho4b 1x3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fOI4ejQZZiODftrBSHrXI1yj065pP5UP36eyaXzR3dw=; b=j4E+BLHTogRYrfC0/6ByyKP/oXtbaEQSoDRdQTBAhnghEdbTB2RTlEAm2FWAZm2qcw UtsYGI+cdjq1jP/6evxh77noD0/d5qSUzWC45zkFu7FW2zeDxlmfqBJzU1q57St85esw Q92hj/t5/iYmQ+PwkiNg5D/eyAp3+R+I9uA0g4PK7vnccZTcVuIg+95Y9kX+7Lly1Hr8 zqj3dkPDwMhJqZN1npgo2FM0RF0pI0GLOPSFTs+LOGFOUOTmVP+zn7QnufOJ1kL7ziZG EJm/KczTwP+UyGgkzPfQ9tAn7xhObvml+U8yT6KUuvj30ZLxr1LE1YLXWdWAtZqSaGp4 rBwQ== X-Gm-Message-State: ANoB5pl/rmXnMw3WCQ7ABBsHPGnl+Hvr1R5wcjshRr1wrdU1jNjlWjNJ 6L52+oywP1zOo5WxfL8Lx5UuLA== X-Google-Smtp-Source: AA0mqf40ve5metyNeR9pqP85whi8pYrughaxn166zWUj52zuKSORgShjFuv3JDhVbBqfLRVYmrDThQ== X-Received: by 2002:a17:90a:f681:b0:219:6bf0:9861 with SMTP id cl1-20020a17090af68100b002196bf09861mr39034573pjb.10.1671340532431; Sat, 17 Dec 2022 21:15:32 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:32 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 2/7] arm64/sysreg: Add CCSIDR2_EL1 Date: Sun, 18 Dec 2022 14:14:07 +0900 Message-Id: <20221218051412.384657-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211533_940295_CC3C3BD9 X-CRM114-Status: UNSURE ( 7.58 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CCSIDR2_EL1 was added with FEAT_CCIDX. Signed-off-by: Akihiko Odaki Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index acc79b5ccf92..0a302b4e6d7a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -898,6 +898,11 @@ Field 5:3 Ctype2 Field 2:0 Ctype1 EndSysreg +Sysreg CCSIDR2_EL1 3 1 0 0 2 +Res0 63:24 +Field 23:0 NumSets +EndSysreg + Sysreg GMID_EL1 3 1 0 0 4 Res0 63:4 Field 3:0 BS From patchwork Sun Dec 18 05:14:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE6A6C4332F for ; Sun, 18 Dec 2022 05:17:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BWHOGZTXS4UkXS5kxGhT6SaJu71aQ83VHOWi6HGNh/E=; b=DLVmz+7tdtqbkC C9Tc0RJF+OmDpQ4gKBsq0dn6kHYME4D5CoWN2vB38/xSYTegjMoo58/LEJ5T61C8GyvM3u/r0rLlv LSJ0nS9j2JbI9BrgJZOwcCMAALP9DwOSvYJRmtn2KH4aR2DNKZ4+R+goXiAGR2vsOkIz6MQcp36Lv ++PFbYJGjA+0V0SvsZO81iS238G3fRkuo7aoLs4+pDJFrAcBK2nQFCvrBaa4/gbR6fgAkW0bcDfir bUiqSx7x6HM/z2kyI3NfbdOWfWrXaDv6wYGbz+8q7WlXg/SFRtvMJJ1PWZTWF/Z1ci6w6Sc5aiwvj o8oKuXmCZ5hh0E7jRx1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1x-00Fugy-UB; Sun, 18 Dec 2022 05:16:10 +0000 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1R-00FuOt-3y for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:38 +0000 Received: by mail-pl1-x62a.google.com with SMTP id a9so6075596pld.7 for ; Sat, 17 Dec 2022 21:15:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=20KqTZ7p9hZYfryC+Vfixvt3usjH4QB21HhVNGKbyBUuo9FRcdt5pDtUHZ0C4OB00k Pxkb4TBy4j5Ucx4LvEqYvxz/DBSczM93egGac/fvIai58XcwYxQmzbaOaTH5tfndBTxj JRi/iiyrq7N9LEDYbMOd0d/shMofzgLH7ExucYoWaDUQvs4RFnTKTKgOLHcox3BCkcz/ qlDlCjh4+wKxwbqjTtDSlSaAePBt7ceu4mPvnka+GHbiTPbBdhbiA/SQ5rGpvs+PtiGm YBbNd2hkCWttAqwAgUDSjtnqR+YIhmIQXXDUneGSDReHXU81LIFM9OiZ2/6KYcqPMIQp yPwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=b5HNvdvr888PM3Y0l1lp7u3HcrvsXsCX2Rsv60PtFsAyt/jAD8lOhl7ZFHxYb5XZWl 2hdAMY5JhNygkbiU5+WA63bPSaXLCTxGB552Y2zDEDniUHphxkkd7l1+I7ir9eK7od72 Hg3KMX0X+0JJuedBXi9Ie8JqmTeIo0H4iwwKkmaKgVTviZGXaeOeMF9U62AKFcgtOMiA t6mTNAvUrM5CHLZYtQSQDN5/L/WA2fxPvdou7hW9i1VKBq0PkaMYmhEADmYB1NlICacr XFkkdLi1pGbEedaLIaNFxSrxO1LRr75nK3h+V6uP6pviBbJeyscb2H+RvliLOh76wXNw 3ZGA== X-Gm-Message-State: AFqh2koRIGHyBy75pJFMMZ5k4U1hMHSo4iyjlcj17DP4pZpVBKxuAD+k RpkSoT33VfLlOtKazq3kRJj5Qw== X-Google-Smtp-Source: AMrXdXtRnhfNE+X0n0H526OoGg60rNUh3zsQ7HI3r0L3dVAMmDfmA+k1y46jlVAC89lTx/mkAJPjBw== X-Received: by 2002:a17:90a:2eca:b0:223:b920:28df with SMTP id h10-20020a17090a2eca00b00223b92028dfmr1736781pjs.29.1671340536313; Sat, 17 Dec 2022 21:15:36 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:35 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 3/7] arm64/cache: Move CLIDR macro definitions Date: Sun, 18 Dec 2022 14:14:08 +0900 Message-Id: <20221218051412.384657-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211537_197305_DD158531 X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The macros are useful for KVM which needs to manage how CLIDR is exposed to vcpu so move them to include/asm/cache.h, which KVM can refer to. Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 6 ++++++ arch/arm64/kernel/cacheinfo.c | 5 ----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index c0b178d1bb4f..ab7133654a72 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -16,6 +16,12 @@ #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 97c42be71338..daa7b3f55997 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -11,11 +11,6 @@ #include #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ -#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) -#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) -#define CLIDR_CTYPE(clidr, level) \ - (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) int cache_line_size(void) { From patchwork Sun Dec 18 05:14:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F5A1C4332F for ; Sun, 18 Dec 2022 05:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8NqHD0h1MGIQe5w33+jsy+brzN4LRbFZyy94RDfu8xM=; b=FYjuQny8W205T3 0iKETorrr/7OtwDz/gUhU141TshLp10sui7AKsLd3SLmHjrVyKQuZhNunS0gphZdQg0roKOQiFLBJ BtyfoGrf7gpDqXF5XyLQ6XbF0I4uQorLNW/w5CIjyUupPeOtw4U+ZAXsogDdViwYAwHiBUMV+T+s5 X2hb2mStKR1NmBcRKdmloVZA4or4S/8EP/pXqQoHN9VMM51EL4L1TMEpHdFxaI91fNYWt6LuHg4xx YVyLtfZg6aE32CniyZ5mKb2UAaxiIXcw5nI90xUglI4cC7CStnjsFRMM9G5aKyWp+aGOd4ARPt0AO DYlAa0IcR/sBplyZS+Ow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m28-00Fuos-Sr; Sun, 18 Dec 2022 05:16:21 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1V-00FuUg-Ma for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:43 +0000 Received: by mail-pl1-x630.google.com with SMTP id t2so6107131ply.2 for ; Sat, 17 Dec 2022 21:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=n0GNyffens8/NKaM1FOU4yqHmtgfe1jSd3RsgG9MqBZ4bhFCl8Qx1XifAXmB8kh5dr ir4ZJBpQjcWXbOHjpA+GWcfjFbxEtA5YNbUFIClPc/pAzRUEc1ejows4Flh7FDBZRjGn oyhY76hXzL3BJwpyjLJNK3sg/kEp+PNxsSee5TJItKcQDTUo7JBlOCnOFbLkSAbP3uJT I5jy/EFuFIs+VrEm0qR0GbvwFE4R+Sfbd5UmuDfnKbQm+4criyedNgrtnnMUkV+/PFLi 3UGnehmrTIF0IGjWvFieIsPhig2MUn0U6izUTJSD+hZYu3KwiUC18vOHJYWgQUyt6hZV tung== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=vqd4klZN8fZzPmjbQetmnpMOncnLQaHQogQsFJZSueSZDR+04N6MJ9H+WxwrhBH8tG d0HdLkTB45PHE5qFZTtw5WLJxryz/CeouTrylsXBqJ3mKopp6GNKtFhUE3HBMcsa9xbh uyMso3GIt9O0+COX0lEMJenzt9ZOOCKs1p9/gtD/piGhbbJvwwA7W89a71huMASmkqtg c+zq6NhEN10a6rru2NzAuv3BhFXIhwOS71UOZ1jzK1Y00nPDVBkCptXFnxPz07Ha7gtt Y2/DMa3gMlCMfM5w3Y+bmRzTYrYNkswU+mgP1hT1qfDmE/N3A8uvAaUQSBZ5xfz9kZyh FkWg== X-Gm-Message-State: AFqh2krs3q93OHh9hvFlQK5I0la2rnPbCXbciamGE6EAKqf/4BKw5I2b l9BJOoAx8dqQ6xhMU1iOkp3UVw== X-Google-Smtp-Source: AMrXdXuNVbYLh7TKzoAhPuPhm0MMGvfsIawvYs2+VupqLnEWB3SzvYdF3oVJnrGFYn4tSZQWIed1ng== X-Received: by 2002:a17:90a:840f:b0:223:aa36:9580 with SMTP id j15-20020a17090a840f00b00223aa369580mr4212952pjn.25.1671340540199; Sat, 17 Dec 2022 21:15:40 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:39 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 4/7] KVM: arm64: Always set HCR_TID2 Date: Sun, 18 Dec 2022 14:14:09 +0900 Message-Id: <20221218051412.384657-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211541_808080_4F906887 X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Always set HCR_TID2 to trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1. This saves a few lines of code and allows to employ their access trap handlers for more purposes anticipated by the old condition for setting HCR_TID2. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_emulate.h | 4 ---- arch/arm64/include/asm/kvm_host.h | 2 -- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 -- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 8aa8492dafc0..44be46c280c1 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -81,11 +81,12 @@ * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory * TID3: Trap EL1 reads of group 3 ID registers + * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 9bdba47f7e14..30c4598d643b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -88,10 +88,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 &= ~HCR_RW; - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || - vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |= HCR_TID2; - if (kvm_has_mte(vcpu->kvm)) vcpu->arch.hcr_el2 |= HCR_ATA; } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 45e2136322ba..cc2ede0eaed4 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -621,7 +621,6 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) return false; switch (reg) { - case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; @@ -666,7 +665,6 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) return false; switch (reg) { - case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h index baa5b9b3dde5..147cb4c846c6 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -39,7 +39,6 @@ static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { - ctxt_sys_reg(ctxt, CSSELR_EL1) = read_sysreg(csselr_el1); ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR); ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR); ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0); @@ -95,7 +94,6 @@ static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt) static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); - write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1); if (has_vhe() || !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { From patchwork Sun Dec 18 05:14:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9497BC4332F for ; Sun, 18 Dec 2022 05:17:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YZVP19JMZydSjxhUQqbX91dEl4EsgnoLTXB/+j0xgV4=; b=V7p7t1LbnJ8q5X eiKAIV1CKtjtQTvNtjVtRznzrxp2KZtje202zrHqUYch9PK8/8qoVt+bKeB62JUxKR859gcrDxqIK JSbtAVFMIWoJUfSsFhneCYBguHiqZZtgNpjyYvF1qBPaJUnJW9Taozkhx9iMO0FIVmcvgwnmQDUJ7 BGVRsYXataE9nJlSYAswIr8l3Ab5Luk9yWSPczwdVeyW8kqlxZeYJNhEToHIKiCVIGoE3SsLQeb0W pqMotGl88ZmYfwuoTnuZgu6BBKubm/5c6DD3vWQqcwlE873cIi9UEODMcooEuFlBwqyeoAB5mXI3c Nqj87R/OXQheBgwivDOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m2N-00Fuxz-GJ; Sun, 18 Dec 2022 05:16:35 +0000 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1Z-00FuVV-6r for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:46 +0000 Received: by mail-pj1-x1031.google.com with SMTP id o12so6129325pjo.4 for ; Sat, 17 Dec 2022 21:15:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vbku2iGSL/iRdowGqnTtMdWjwk//SMim4nWmdRDxnMs=; b=123/KLCj3LYyn7rqztkvM6x2AeqkXLK9bCMFJRafssVwqlH+yC/0Sec+Z9u5yN86hV E9SHypw+xwWcprb2R7QAMbw8bNosbbo653zRWRSkrKWkmNzlbElAXrX6qOUnflJ+cHDW v+aOruOljFuRajGzX90eIbOg9g6ZYWFP+2+dF7G6VOvkAf6UBT0nU532pY3Ye366bWBF CHemz3sLKDVpy6JltRaNfIYvf/INHt6prddtEpMHz1eywXgnqQCUTA6Gc8eoe63aOEZI pwEncdhARLzxG5coAckvqDxpWoMzyhk0H9t+vVV5aCqN2aqYqTBYbS+0HC6oK+RAkVfX Hu7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vbku2iGSL/iRdowGqnTtMdWjwk//SMim4nWmdRDxnMs=; b=0y+L0jKCeVysnRHPLQNrm++88JgczLe/LkR7Q5I3GuZ71RgwUVQJlmz4ex+kRWEFwb CPyuMsIVju10criE0SfMJh0R2rE23i7H5mm4iruM7JCnprciZoTdtLCZozPU32eDLmSc EE4PVPzOTHDyk2NEMYDzyFGkx+FTZjOCD2FXBs/ORTwVwBpWT+cPZMEE0nkfjAciBAoA nYWGTYF5XHmmgzOME1SNlj3xzaYQrJnq4AgQ3CHeij4bLRUEZYmWGO1FR47pPMt/H6m6 PA7Zg7qD1rc3cqy/mktgUDYC7FVyPUi+vhXI4SWw6FmkJdE2wTtPPk9W3S8mriAeMAVN VBRA== X-Gm-Message-State: ANoB5pn+TXzVbiFupSKM0mMeVI4ZrCtMN2bFugmPClqhQrmfgBz0OadW sp+MC7BkS3OWeJvEhc2Gq0clog== X-Google-Smtp-Source: AA0mqf47GW9wCDSTklj2Bvuc8AJ8IgjIZXIJkwM9/dZgQRSZQMCLTY55T8L/SnveaWRUwRQn4MdOPg== X-Received: by 2002:a17:90a:a04:b0:219:bd62:f048 with SMTP id o4-20020a17090a0a0400b00219bd62f048mr38770743pjo.4.1671340544122; Sat, 17 Dec 2022 21:15:44 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:43 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 5/7] KVM: arm64: Allow user to set CCSIDR_EL1 Date: Sun, 18 Dec 2022 14:14:10 +0900 Message-Id: <20221218051412.384657-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211545_283706_2B88C1E5 X-CRM114-Status: GOOD ( 19.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow the userspace to set CCSIDR_EL1 so that if the kernel changes the default values of CCSIDR_EL1, the userspace can restore the old values from an old saved VM context. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_host.h | 3 + arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 116 ++++++++++++++++++++---------- 3 files changed, 83 insertions(+), 37 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index cc2ede0eaed4..cfc6930efe1b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -417,6 +417,9 @@ struct kvm_vcpu_arch { u64 last_steal; gpa_t base; } steal; + + /* Per-vcpu CCSIDR override or NULL */ + u32 *ccsidr; }; /* diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 5ae18472205a..7980983dbad7 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -157,6 +157,7 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) if (sve_state) kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); kfree(sve_state); + kfree(vcpu->arch.ccsidr); } static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f4a7c5abcbca..f48a3cc38d24 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -87,11 +87,27 @@ static u32 cache_levels; /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 +static u8 get_min_cache_line_size(u32 csselr) +{ + u64 ctr_el0; + int field; + + ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); + field = csselr & CSSELR_EL1_InD ? CTR_EL0_IminLine_SHIFT : CTR_EL0_DminLine_SHIFT; + + return cpuid_feature_extract_unsigned_field(ctr_el0, field) - 2; +} + /* Which cache CCSIDR represents depends on CSSELR value. */ -static u32 get_ccsidr(u32 csselr) +static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) { + u32 ccsidr_index = csselr & (CSSELR_EL1_Level | CSSELR_EL1_InD); u32 ccsidr; + if (vcpu->arch.ccsidr && is_valid_cache(ccsidr_index) && + !(kvm_has_mte(vcpu->kvm) && (csselr & CSSELR_EL1_TnD))) + return vcpu->arch.ccsidr[ccsidr_index]; + /* Make sure noone else changes CSSELR during this! */ local_irq_disable(); write_sysreg(csselr, csselr_el1); @@ -102,6 +118,61 @@ static u32 get_ccsidr(u32 csselr) return ccsidr; } +static bool is_valid_cache(u32 val) +{ + u32 level, ctype; + + if (val >= CSSELR_MAX) + return false; + + /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ + level = (val >> 1); + ctype = (cache_levels >> (level * 3)) & 7; + + switch (ctype) { + case 0: /* No cache */ + return false; + case 1: /* Instruction cache only */ + return (val & 1); + case 2: /* Data cache only */ + case 4: /* Unified cache */ + return !(val & 1); + case 3: /* Separate instruction and data caches */ + return true; + default: /* Reserved: we can't know instruction or data. */ + return false; + } +} + +static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) +{ + u8 line_size = (val & CCSIDR_EL1_LineSize) >> CCSIDR_EL1_LineSize_SHIFT; + u32 *ccsidr = vcpu->arch.ccsidr; + u32 i; + + if ((val & CCSIDR_EL1_RES0) || line_size < get_min_cache_line_size(csselr)) + return -EINVAL; + + if (!ccsidr) { + if (val == get_ccsidr(vcpu, csselr)) + return 0; + + ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL); + if (!ccsidr) + return -ENOMEM; + + for (i = 0; i < CSSELR_MAX; i++) + if (is_valid_cache(i)) + ccsidr[i] = get_ccsidr(vcpu, i); + + vcpu->arch.ccsidr = ccsidr; + } + + ccsidr[csselr] = val; + + return 0; +} + /* * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). */ @@ -1300,7 +1371,7 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return write_to_read_only(vcpu, p, r); csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); - p->regval = get_ccsidr(csselr); + p->regval = get_ccsidr(vcpu, csselr); /* * Guests should not be doing cache operations by set/way at all, and @@ -2660,33 +2731,7 @@ static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) return 0; } -static bool is_valid_cache(u32 val) -{ - u32 level, ctype; - - if (val >= CSSELR_MAX) - return false; - - /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level = (val >> 1); - ctype = (cache_levels >> (level * 3)) & 7; - - switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ - return true; - default: /* Reserved: we can't know instruction or data. */ - return false; - } -} - -static int demux_c15_get(u64 id, void __user *uaddr) +static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val; u32 __user *uval = uaddr; @@ -2705,13 +2750,13 @@ static int demux_c15_get(u64 id, void __user *uaddr) if (!is_valid_cache(val)) return -ENOENT; - return put_user(get_ccsidr(val), uval); + return put_user(get_ccsidr(vcpu, val), uval); default: return -ENOENT; } } -static int demux_c15_set(u64 id, void __user *uaddr) +static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val, newval; u32 __user *uval = uaddr; @@ -2733,10 +2778,7 @@ static int demux_c15_set(u64 id, void __user *uaddr) if (get_user(newval, uval)) return -EFAULT; - /* This is also invariant: you can't change it. */ - if (newval != get_ccsidr(val)) - return -EINVAL; - return 0; + return set_ccsidr(vcpu, val, newval); default: return -ENOENT; } @@ -2773,7 +2815,7 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg int err; if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) - return demux_c15_get(reg->id, uaddr); + return demux_c15_get(vcpu, reg->id, uaddr); err = get_invariant_sys_reg(reg->id, uaddr); if (err != -ENOENT) @@ -2817,7 +2859,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg int err; if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) - return demux_c15_set(reg->id, uaddr); + return demux_c15_set(vcpu, reg->id, uaddr); err = set_invariant_sys_reg(reg->id, uaddr); if (err != -ENOENT) From patchwork Sun Dec 18 05:14:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 790D4C4332F for ; Sun, 18 Dec 2022 05:17:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ocWPpyshRfUF2l207Mzqp3luQRnRjSRQzInbWK27Zhc=; b=OZrRlUK3fJyZ6a yq6reTm7URdkgBrbER0rNCIzzZf6x1wNTRttqKwYyVPVAXOEyrfwFA/DRY71NLXspBJtXMObhJB+d dwndGTVZVmyOVri1K/harp4Jn7F1Fz/lJbJWLHY0ivncz1M/jZXWIBLIc6LBqfo6QV/SYnT0jUsq7 bkB7mUC9W+74v/l1Yvv/ge24L1/rLKEr+XbUdtJYIe/2R4AEiYP7WvnWUN9JG3Vm633wSPYsqCEN9 Rz4jOsPykloUsP0yfpQ0WcwuxW/ItZXBx+h80iaqomQE+25fR3sIyveiMnXfyW1UZwFTVb58+Cdn6 X1HOaQdBlcgAJDh6xE3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m2e-00FvCm-2N; Sun, 18 Dec 2022 05:16:52 +0000 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1d-00FubK-Ni for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:50 +0000 Received: by mail-pj1-x1036.google.com with SMTP id fy4so6190955pjb.0 for ; Sat, 17 Dec 2022 21:15:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QbwMfys3+9WZoYtA5YRufReD7fZRc1BEVtWsfBO6EFw=; b=o5urDT3PQQZ9b78JxurBz0P876mpfVVMU9PTg5Iv9tcINeCNgkvc+u33ksU8NQLWG3 hXcDR+BX3XsEf5TRJmVO/Ks+pZZ2QtcUo1RKxEcafRKktF5onby8aDQZeYDB4R/XWzWC mIn8LBypGMXEaO/FrSu3AVnyBBfyhzeBfx2IRKTG6InEMIL1QMqbI5NMy2JnY1Wn8imv 9gmVkG+BM25iUzCCwyGClYiUpo9zHzIv2q1+qadhjzgYJkd0F45/w/Qx/xud54MqKX8a DA4I6x//NnfDgXDGBZOzypKIRiaaW7hPRB6p8K8ssDpIRV6e2gLNpUe2e02dh1KnQa+U 5ARg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QbwMfys3+9WZoYtA5YRufReD7fZRc1BEVtWsfBO6EFw=; b=RfVVw2wA7dmP9nYFtZirW06OdB4eIV8dfYnHfUiPT96F9TlVZdPS08FuLN8yBKO010 EZXXydDmFXVA602kOn6w0sRpQ4xRQaEqNsYwGFeT9ugyl9Y/pJEHLj3EXa4U8wyBVUGP +3Kz6319/QeAcq+oxJaS6/EYfWqWvroeXNnA2ZxAMiRgvw3VPTgtBMv2+s94ywuQXE2M xr/dHBgOW3iCg2MySaE4zSw4Wfm25NFz/vjKlJ/WExUzvq1TxoHaZ6iFmu+Lcx+me6l/ rYSJfEip0oHHimmptEibylgGsr3OwafZ0BMNxpb6z2TFVBQOj+51aKbJ+VRXWUz9TKlf sCXg== X-Gm-Message-State: ANoB5pldCRWD+A2BGPdAS2bmgE2GETHqB9B+QCKjiPxWxe2ac3EqhnP0 XmwEZcspf597s1OVx6UiWdKbsw== X-Google-Smtp-Source: AA0mqf7QCiGl5d9+spTzOyPlO6TcWemQOa/HV6d8IE9CviRM8bqJlTDV9iNJCKFfiTU6HuKnpIEFLA== X-Received: by 2002:a17:90b:253:b0:223:1e7d:67e7 with SMTP id fz19-20020a17090b025300b002231e7d67e7mr20682580pjb.21.1671340548041; Sat, 17 Dec 2022 21:15:48 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:47 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 6/7] KVM: arm64: Mask FEAT_CCIDX Date: Sun, 18 Dec 2022 14:14:11 +0900 Message-Id: <20221218051412.384657-7-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211549_790210_A04EDD24 X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CCSIDR access handler masks the associativity bits according to the bit layout for processors without FEAT_CCIDX. KVM also assumes CCSIDR is 32-bit where it will be 64-bit if FEAT_CCIDX is enabled. Mask FEAT_CCIDX so that these assumptions hold. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f48a3cc38d24..a7199f34e321 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1195,6 +1195,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r ID_DFR0_PERFMON_SHIFT, kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); break; + case SYS_ID_AA64MMFR2_EL1: + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + break; + case SYS_ID_MMFR4_EL1: + val &= ~ARM64_FEATURE_MASK(ID_MMFR4_CCIDX); + break; } return val; @@ -1676,6 +1682,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, @@ -2177,6 +2184,10 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, + + /* CCSIDR2 */ + { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, + { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, }; From patchwork Sun Dec 18 05:14:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13075979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AAE2C4332F for ; Sun, 18 Dec 2022 05:18:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EpK+60DmD8XdSGF2SVwb7eViOoLlBaFCmPNWwZVMOGY=; b=tVcw1CLIZlGuNK ag/IrJRSIMuikIq11gg6z7NbOf8Kxb9S2riYaX+6MQrGDcCk5oRR2BBrqtSieRY9zE5oC1nUgOxU3 CqoIPU7lz6MgsE7CvwoMlByj0291Hg3ttUl6x52HYUNnf63aqExOjEkHpOYKXUUkVINUZhQUTxJPM MVBvCdpIzFl+LFufqldZbK8KMkva++m7QIvE1sfjAGoaDYhX+65benPxKtGjYJfMG8iwApp8pONdb LUqXRZGv6j4iAE4OmeijcbuvXJit0zFqp5o/YQgMJbLRJ+MTb8ob7VYzja8vWI4j9L0HXovi95NKU etya1ER/PVb1UtDgrxGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m32-00FvPJ-L7; Sun, 18 Dec 2022 05:17:16 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p6m1g-00FuUg-Dn for linux-arm-kernel@lists.infradead.org; Sun, 18 Dec 2022 05:15:54 +0000 Received: by mail-pl1-x630.google.com with SMTP id t2so6107327ply.2 for ; Sat, 17 Dec 2022 21:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJmzgqWbYjXHayt1fVUjbpZdSQg9mlJmebSHfVtOk/w=; b=slrgCkBu4hD5xxrdTty9DB5h0GOnqA6WFBWTs+nuJEmU57fuUCTwWCunetECMIaccs Bvq1JsRDiqX/GAki+Hyvv4/xotRwAKB7Ldb3nL9TT5S9gRI620O+s7OH1gnJUGr3z5dG 1jGY8MpaLCm/x6f52w+ze4oJFZVT6dfqYbTWnO05Li6GrtBVrCCow+A2tXae5yhCxMl1 ybOwwhNTrsq1szvHo7kagpV+MtIvULI8qMf+wLU1zBLe6FlJb/HfxU1e01jyr5AMiBEs cfz04wmEfOjiUXByOIRHAC26OaZJlQzfrZfLT+ZmrA428iX96jPS1h8mMX15uALgbUa2 xV3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJmzgqWbYjXHayt1fVUjbpZdSQg9mlJmebSHfVtOk/w=; b=styZUcHFEW8mXSplSie2jjo6nsCls4Aejnl6ZtpN+0kgnGQA22RVujoy3sgqbo3TAx MRQ404ZXYzQpA5LOKFXLjRWEgrmTx/4MygjaN5s4YYPhm6QYliBYqtOnnZy83YlUUro4 TbukR3qwUt7Qzf+8ZUAFbVmNuafmXPI5f+nCyJq15FClnBS62v+q7uN6h79sGSLP52H+ X+W2T1bPYuk5F1uzAhxiIR7JzcCUCrptHypPCnJ9alogc0NQUpJRERfSelo1ZVmNLEa1 SDkaf/r6gcRVYaF1DBT7/B2AJfWo3M75Uqm+3+bZWQm7drIdV39Tz8pKY2Gt7V37AjZ+ ofXA== X-Gm-Message-State: ANoB5pnv/nqLWKNYgrghgQ+ozB5MHMcJ7dcaS9XuVNj+y8IIL5Is5hMr VTGSpzk0v2kV4dwlK/AgBKbxTA== X-Google-Smtp-Source: AA0mqf4E49x4lUAbvX6a61HO3fXfHcqIeoGOvrf+PT79bhPCUz7EMHic4yOOVOM2Of91ArtZ1uqEPA== X-Received: by 2002:a17:90a:ac07:b0:219:aa58:77ba with SMTP id o7-20020a17090aac0700b00219aa5877bamr39470299pjq.25.1671340551960; Sat, 17 Dec 2022 21:15:51 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:51 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 7/7] KVM: arm64: Normalize cache configuration Date: Sun, 18 Dec 2022 14:14:12 +0900 Message-Id: <20221218051412.384657-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221217_211552_502997_6E5ECC9C X-CRM114-Status: GOOD ( 31.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. CLIDR_EL1 is now writable from the userspace so that the VMM can restore the values saved with the old kernel. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 3 + arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/sys_regs.c | 183 +++++++++++++++--------------- 3 files changed, 96 insertions(+), 91 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index ab7133654a72..a51e6e8f3171 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -22,6 +22,9 @@ #define CLIDR_CTYPE(clidr, level) \ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) +/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */ +#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index cfc6930efe1b..27abf81c6910 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -178,6 +178,7 @@ struct kvm_vcpu_fault_info { enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ + CLIDR_EL1, /* Cache Level ID Register */ CSSELR_EL1, /* Cache Size Selection Register */ SCTLR_EL1, /* System Control Register */ ACTLR_EL1, /* Auxiliary Control Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a7199f34e321..9fd0b28e29bd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -81,9 +82,6 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) __vcpu_sys_reg(vcpu, reg) = val; } -/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ -static u32 cache_levels; - /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 @@ -101,47 +99,36 @@ static u8 get_min_cache_line_size(u32 csselr) /* Which cache CCSIDR represents depends on CSSELR value. */ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) { - u32 ccsidr_index = csselr & (CSSELR_EL1_Level | CSSELR_EL1_InD); - u32 ccsidr; - - if (vcpu->arch.ccsidr && is_valid_cache(ccsidr_index) && - !(kvm_has_mte(vcpu->kvm) && (csselr & CSSELR_EL1_TnD))) - return vcpu->arch.ccsidr[ccsidr_index]; - - /* Make sure noone else changes CSSELR during this! */ - local_irq_disable(); - write_sysreg(csselr, csselr_el1); - isb(); - ccsidr = read_sysreg(ccsidr_el1); - local_irq_enable(); - - return ccsidr; -} - -static bool is_valid_cache(u32 val) -{ - u32 level, ctype; + u64 ctr_el0; + int field; - if (val >= CSSELR_MAX) - return false; + if (vcpu->arch.ccsidr) + return vcpu->arch.ccsidr[csselr]; - /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level = (val >> 1); - ctype = (cache_levels >> (level * 3)) & 7; + ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); + field = csselr & CSSELR_EL1_InD ? CTR_EL0_IminLine_SHIFT : CTR_EL0_DminLine_SHIFT; - switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ - return true; - default: /* Reserved: we can't know instruction or data. */ - return false; - } + /* + * Fabricate a CCSIDR value as the overriding value does not exist. + * The real CCSIDR value will not be used as it can vary by the + * physical CPU which the vcpu currently resides in. + * + * The line size is determined with arm64_ftr_reg_ctrel0.sys_val, which + * should be valid for all CPUs even if they have different cache + * configuration. + * + * The associativity bits are cleared, meaning the geometry of all data + * and unified caches (which are guaranteed to be PIPT and thus + * non-aliasing) are 1 set and 1 way. + * Guests should not be doing cache operations by set/way at all, and + * for this reason, we trap them and attempt to infer the intent, so + * that we can flush the entire guest's address space at the appropriate + * time. The exposed geometry minimizes the number of the traps. + * [If guests should attempt to infer aliasing properties from the + * geometry (which is not permitted by the architecture), they would + * only do so for virtually indexed caches.] + */ + return get_min_cache_line_size(csselr) << CCSIDR_EL1_LineSize_SHIFT; } static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) @@ -162,8 +149,7 @@ static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) return -ENOMEM; for (i = 0; i < CSSELR_MAX; i++) - if (is_valid_cache(i)) - ccsidr[i] = get_ccsidr(vcpu, i); + ccsidr[i] = get_ccsidr(vcpu, i); vcpu->arch.ccsidr = ccsidr; } @@ -1352,10 +1338,64 @@ static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, if (p->is_write) return write_to_read_only(vcpu, p, r); - p->regval = read_sysreg(clidr_el1); + p->regval = __vcpu_sys_reg(vcpu, r->reg); return true; } +/* + * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary + * by the physical CPU which the vcpu currently resides in. + */ +static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); + u64 clidr; + u8 loc; + + if ((ctr_el0 & CTR_EL0_IDC) || cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { + /* + * Data cache clean to the PoU is not required so LoUU and LoUIS + * will not be set and a unified cache, which will be marked as + * LoC, will be added. + * + * If not DIC, let the unified cache L2 so that an instruction + * cache can be added as L1 later. + */ + loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; + clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); + } else { + /* + * Data cache clean to the PoU is required so let L1 have a data + * cache and mark it as LoUU and LoUIS. As L1 has a data cache, + * it can be marked as LoC too. + */ + loc = 1; + clidr = 1 << CLIDR_LOUU_SHIFT; + clidr |= 1 << CLIDR_LOUIS_SHIFT; + clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); + } + + /* + * Instruction cache invalidation to the PoU is required so let L1 have + * an instruction cache. If L1 already has a data cache, it will be + * CACHE_TYPE_SEPARATE. + */ + if (!(ctr_el0 & CTR_EL0_DIC)) + clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); + + clidr |= loc << CLIDR_LOC_SHIFT; + + /* + * Add tag cache unified to data cache. Allocation tags and data are + * unified in a cache line so that it looks valid even if there is only + * one cache line. + */ + if (kvm_has_mte(vcpu->kvm)) + clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); + + __vcpu_sys_reg(vcpu, r->reg) = clidr; +} + static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1377,22 +1417,12 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return write_to_read_only(vcpu, p, r); csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); + csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; + if (csselr >= CSSELR_MAX) + return undef_access(vcpu, p, r); + p->regval = get_ccsidr(vcpu, csselr); - /* - * Guests should not be doing cache operations by set/way at all, and - * for this reason, we trap them and attempt to infer the intent, so - * that we can flush the entire guest's address space at the appropriate - * time. - * To prevent this trapping from causing performance problems, let's - * expose the geometry of all data and unified caches (which are - * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. - * [If guests should attempt to infer aliasing properties from the - * geometry (which is not permitted by the architecture), they would - * only do so for virtually indexed caches.] - */ - if (!(csselr & 1)) // data or unified cache - p->regval &= ~GENMASK(27, 3); return true; } @@ -1681,7 +1711,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, - { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1 }, { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, @@ -2693,7 +2723,6 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, FUNCTION_INVARIANT(midr_el1) FUNCTION_INVARIANT(revidr_el1) -FUNCTION_INVARIANT(clidr_el1) FUNCTION_INVARIANT(aidr_el1) static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) @@ -2705,7 +2734,6 @@ static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) static struct sys_reg_desc invariant_sys_regs[] = { { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, - { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, }; @@ -2758,7 +2786,7 @@ static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) return -ENOENT; val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >= CSSELR_MAX) return -ENOENT; return put_user(get_ccsidr(vcpu, val), uval); @@ -2783,7 +2811,7 @@ static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) return -ENOENT; val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >= CSSELR_MAX) return -ENOENT; if (get_user(newval, uval)) @@ -2882,13 +2910,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg static unsigned int num_demux_regs(void) { - unsigned int i, count = 0; - - for (i = 0; i < CSSELR_MAX; i++) - if (is_valid_cache(i)) - count++; - - return count; + return CSSELR_MAX; } static int write_demux_regids(u64 __user *uindices) @@ -2898,8 +2920,6 @@ static int write_demux_regids(u64 __user *uindices) val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; for (i = 0; i < CSSELR_MAX; i++) { - if (!is_valid_cache(i)) - continue; if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -3001,7 +3021,6 @@ int kvm_sys_reg_table_init(void) { bool valid = true; unsigned int i; - struct sys_reg_desc clidr; /* Make sure tables are unique and in order. */ valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); @@ -3018,23 +3037,5 @@ int kvm_sys_reg_table_init(void) for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); - /* - * CLIDR format is awkward, so clean it up. See ARM B4.1.20: - * - * If software reads the Cache Type fields from Ctype1 - * upwards, once it has seen a value of 0b000, no caches - * exist at further-out levels of the hierarchy. So, for - * example, if Ctype3 is the first Cache Type field with a - * value of 0b000, the values of Ctype4 to Ctype7 must be - * ignored. - */ - get_clidr_el1(NULL, &clidr); /* Ugly... */ - cache_levels = clidr.val; - for (i = 0; i < 7; i++) - if (((cache_levels >> (i*3)) & 7) == 0) - break; - /* Clear all higher bits. */ - cache_levels &= (1 << (i*3))-1; - return 0; }