From patchwork Wed Dec 21 18:22:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFAB5C4167B for ; Wed, 21 Dec 2022 18:24:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kX-00084i-2G; Wed, 21 Dec 2022 13:23:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kO-0007zL-TB for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:20 -0500 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kM-0007pB-PZ for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:20 -0500 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1433ef3b61fso20093556fac.10 for ; Wed, 21 Dec 2022 10:23:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wAX2+OwNFeeUZjBeEsjIZKrfL1qZu8pl6CTdHwneZDo=; b=lmVNY9jigG2n8XdPsnYOei82O3CSSAvM2aMj7tMAkdRR7JOc2FFEfdRu/zzzzZKe4y Opzq05q+1qYOM1ZfAIzrF2V0+fCPvpNJqVQTLsDJBuOemf4iAjOud/f/xAeOzJ3QTPLZ GbY3AEfePHJgrMCz5rmALLeakfUml9j9ik/0GfP8cBOE9Ew23UduZkskz82ZH4w/eNoe v0fLfzWuLfiBxpPiC4tt1EYzD2SJ5NWrbvBn8IPBfgsXZ+gohXi4NvZXafh1Ykd2Hybr nviipxGuNRn8CjdNfpFkcsCQVrEi8QM+ZvPnaAQIY7Ns1w/TjdXJuyqRAwLmLYcnXZ/r 0ceg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wAX2+OwNFeeUZjBeEsjIZKrfL1qZu8pl6CTdHwneZDo=; b=qyRzggLb0BY948otcdEIYCgLXJm4thy7ZhiO1Hi66WT2wNqgaR8E991PMH0c5oV/2l /Fnj2NX7cXvh/NCbZVRtVcYvDDJWZovKnYuZWoVr3DwWblqxbf/v8cKl1Oj0mpX1b3N6 MqBTu8lS8Hm8XgJxro6nJWK0f7qntmWNa0e6oFZ3YazG2C5Kcb+j6lMnHk5Kysxh4CM7 98hF7EjOR9rCUdMKY3vCFjauk9S9vaM6/PM4/3a0C2VXV7IP78Iqo6M4go5tKghtAW9y +pFIFelzZn8hRJ50ObYxEeaPfPUipH0YFv5WHRSVEO2HWbu1qW9SrotYCTSPP0BY4PHn RQ/Q== X-Gm-Message-State: AFqh2komcyXWcO+m1PCCiAm4IsK1NmXbT0DRqNIdN+03VjbYFyypGmWq ZqAniBFvyG1kxuidyHjF0TV6TlQenlBnpbYs X-Google-Smtp-Source: AMrXdXuuPWUhrqpbC+EXNpi+uFRSkHTzvkEu/xrt7R5ehmNG8jOVZlj8Yb4OQSj2fdANxSOM3wGPVA== X-Received: by 2002:a05:6870:238f:b0:144:9783:54dd with SMTP id e15-20020a056870238f00b00144978354ddmr1462648oap.11.1671646996592; Wed, 21 Dec 2022 10:23:16 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Cleber Rosa , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test Date: Wed, 21 Dec 2022 15:22:46 -0300 Message-Id: <20221221182300.307900-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. Cc: Cleber Rosa Cc: Philippe Mathieu-Daudé Cc: Wainer dos Santos Moschetta Cc: Beraldo Leal Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Wainer dos Santos Moschetta --- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py new file mode 100644 index 0000000000..abc99ced30 --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,65 @@ +# opensbi boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado_qemu import wait_for_console_pattern + +class RiscvOpensbi(QemuSystemTest): + """ + :avocado: tags=accel:tcg + """ + timeout = 5 + + def test_riscv64_virt(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:virt + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_spike(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:spike + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:sifive_u + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv32_virt(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:virt + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:sifive_u + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') From patchwork Wed Dec 21 18:22:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2320C10F1B for ; Wed, 21 Dec 2022 18:23:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kW-000844-NA; Wed, 21 Dec 2022 13:23:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kQ-0007zf-3a for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:22 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kO-0007pT-L9 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:21 -0500 Received: by mail-oi1-x236.google.com with SMTP id o66so12600164oia.6 for ; Wed, 21 Dec 2022 10:23:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qqzmyj9XmxTFjNFYEDd87lGar6iNWg88ub+LrFILNQE=; b=CAjUi+kyEjL/bSXsDx+WlfRXwY8Puvso355kuS5w3v/sqPf7/HLtVbCxYk/IWEknGb hRr0IuHO04IIeGn4K6dbErddZfuUZnjeEE9BPuXUXNKf0nmZ7n/oSlazAh+4LixUdUho lt98L7Z6a5DLnOEogd2SupUMixhhvpdltEEJOipZ94Zdn0hH24lQukAuVz+k68pSfY2R v46jiAhXD0d60aJ4HuXZaYzP1Ods+luAesVvWMPqFEIC77INvgkNA3uHwJXIK4AYBX+c 1j3QxqG4fR3c2afA58FyhWWCmxncBmRbdkVWhWpHuUcPihasGLEI7JghyioS8yOq32iE cj0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qqzmyj9XmxTFjNFYEDd87lGar6iNWg88ub+LrFILNQE=; b=WRui+wSCn5u2x6GZ43R7tZsK9wZ3lJKLw2Vpv+9lLv1kcxyiR9ZgxiUwjujn2Y9nNn DHHwn6eikLFDzv3Dr7MTmOkJiF0ZY/R10pX8gtW4e79ULC8KlwkvS7kb4DfTN6HZZ9WT VTgcUAVuZ3lJolFF4AmhX9ivlTb9KsjUX82FSt8PlERQC2IBMHi5nMQQRzQW+hNieSJr tdkeeQpBcpFXcEWdrfiQWMr5aRhsRwWC40fCFPsNhs+hrBjZTI/Op9CUV/XZYAPb2JzW t69C2LWhIynRsAohbFV5+To74LJpo6xS7V/ELXq7xccpbNIbD2FpYEqPQ3AzNQvTknnQ vVjQ== X-Gm-Message-State: AFqh2krJtVublL063qxkYOqP6ee9Q7ZKAiasCSBZEbDLXgloM96wcU0E DMPKfVd/s3ap1ocjJfW8VFPxkhtk/uIvE/XJ X-Google-Smtp-Source: AMrXdXtXJ2YBJxKWYMfyXci1z8bLhq1z/cB5cFZeClyvuzgpv68Dufi3DjwxtxwsDvE7k5B+u/NS2A== X-Received: by 2002:a05:6808:8f0:b0:35c:4b2c:6a5 with SMTP id d16-20020a05680808f000b0035c4b2c06a5mr1301480oic.51.1671646998865; Wed, 21 Dec 2022 10:23:18 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:18 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 02/15] hw/riscv/spike: use 'fdt' from MachineState Date: Wed, 21 Dec 2022 15:22:47 -0300 Message-Id: <20221221182300.307900-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SpikeState and use MachineState::fdt instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 12 +++++------- include/hw/riscv/spike.h | 2 -- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 13946acf0d..d96f013e2e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -52,6 +52,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; + int fdt_size; uint64_t addr, size; unsigned long clint_addr; int cpu, socket; @@ -64,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = s->fdt = create_device_tree(&s->fdt_size); + fdt = mc->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -296,18 +297,15 @@ static void spike_board_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, s->fdt); - - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt = s->fdt; + machine->ram_size, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 73d69234de..d13a147942 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -37,8 +37,6 @@ struct SpikeState { /*< public >*/ RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; - void *fdt; - int fdt_size; }; enum { From patchwork Wed Dec 21 18:22:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A05BC10F1B for ; Wed, 21 Dec 2022 18:25:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kX-00085g-Iq; Wed, 21 Dec 2022 13:23:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kS-00082G-3s for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:24 -0500 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kQ-0007oj-Gu for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:23 -0500 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1445ca00781so20159788fac.1 for ; Wed, 21 Dec 2022 10:23:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=74zPKwHf8N53W2PxXJGQXmpqGXy9m0+YJHtlrDRJ0ds=; b=ZGOlmcnHxbHCSd40jy5pAlYM7ad/e+Kx+iH89HGS3DO7vKHXjhC1mJfwuD6K6veCde byI2hZ2dq0IvGQR1io6nz65JFBVjppiOvDuwUMYQ1MwP3Q/WwgyjqwpkNnVod4mLNxhX OYYmCs6lAS831cW3f1+IELQub6+peoxAdXyxHei66p5HCBI4+nOih/Kh6Dp0qvcGE9vg EBAbPhzOUJfBVOpRy6KeOuTbk8p0AEWSwS0N8aMKmm2IdQX9NXNYG3Ic0SgVxJpsLU+g zgHup2BsDYRjsyhUO0+gxF4pI9MCxjtYtFIBliZ43rdVgx671LyU3PD6TzFdyhn2hiw4 d5kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=74zPKwHf8N53W2PxXJGQXmpqGXy9m0+YJHtlrDRJ0ds=; b=uU4yrpyHlIVvPz+6JU1UL3sGWGUTB5CL/7CCbAMUWrrQsnDzvZ/OrQ65Jilb8XuxNy ycMiTBgr/ttgqJodmpSiprs6UFG3HpDBuAWXZS+VeUemMBMpePG57KpYljjHCbDvviyI +q5y0nPUjt+nbPVwpiBiwFn3mk+O4K2Tz0+ScLQN2CIqrLUi2XC54jpdOAOJnm/Z0ynx JMLZS9N5/xl4WVFW93qTKqACCtbzkRAQnhjGBYWUpz1x4jcvQkM7gAfrUlGbmLnsaPgk xmkkwIPptDDNGZHvTW1J+LY0fFMdBSga/dC8qKPsjj+Ep3l0kYLdmrp47sVBcIFZ11VN TVeA== X-Gm-Message-State: AFqh2kpaXkPbII0z/zT25tN8E8Tw+rML1MZPS6Lv2Dl0q5gCOnNwvbk/ YRqxk5aJV4x26vQX+7mkDQPkLburLdS67U3E X-Google-Smtp-Source: AMrXdXtbCGveGgnqQQIJlZrV8G3lIeAQ4qTCll1i04ubWTRc/zZHy9rDohHTndDV+e+BCVg85WqGyw== X-Received: by 2002:a05:6870:3d8a:b0:14c:6a70:9660 with SMTP id lm10-20020a0568703d8a00b0014c6a709660mr1264074oab.43.1671647001263; Wed, 21 Dec 2022 10:23:21 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:20 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 03/15] hw/riscv/sifive_u: use 'fdt' from MachineState Date: Wed, 21 Dec 2022 15:22:48 -0300 Message-Id: <20221221182300.307900-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt instead. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 15 ++++++--------- include/hw/riscv/sifive_u.h | 3 --- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b40a4767e2..9cf66957ab 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, { MachineState *ms = MACHINE(qdev_get_machine()); void *fdt; - int cpu; + int cpu, fdt_size; uint32_t *cells; char *nodename; uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; @@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, }; if (ms->dtb) { - fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); + fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size); if (!fdt) { error_report("load_device_tree() failed"); exit(1); } goto update_bootargs; } else { - fdt = s->fdt = create_device_tree(&s->fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -615,9 +615,9 @@ static void sifive_u_machine_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } } else { @@ -630,14 +630,11 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, s->fdt); + machine->ram_size, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt = s->fdt; - /* reset vector */ uint32_t reset_vec[12] = { s->msel, /* MSEL pin state */ diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e680d61ece..4a8828a30e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -67,9 +67,6 @@ typedef struct SiFiveUState { /*< public >*/ SiFiveUSoCState soc; - void *fdt; - int fdt_size; - bool start_in_flash; uint32_t msel; uint32_t serial; From patchwork Wed Dec 21 18:22:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFBD6C10F1B for ; Wed, 21 Dec 2022 18:26:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kY-00086a-Fk; Wed, 21 Dec 2022 13:23:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kU-00083Z-Ng for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:28 -0500 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kT-0007qH-5D for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:26 -0500 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-14449b7814bso20154156fac.3 for ; Wed, 21 Dec 2022 10:23:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7RkRJF9o2c3C5CMhU+t5ZhyG4d5D3mhoMdfolGfNI5A=; b=l3X1279vNzRS9eoA1217HxROrlF3YdTMbtlmZL0aAd3rwwFAOSfsZO2nliQdgR+D2B gZ5vwP6aLAC7dcNV5YHkkVDPJy6Kk3oVHoJ0ivvVF5FPigAY9mMl5CQYhCjSKgy/NwiM 2jXsIcAqBv1bD+Abq6wAEo/KQGx+Rrg/4BAI9JIaKSyd0aoFD2MB7MqSp2+ML7oPap0P eO35vKlLR29gDUQ4B1+lWB/lQHytsQlw/6ZbwG9WS7T9wlx+CTK9by1mO522SJCaS4Ak 6rSb9gWzwzxRUMILZ2lrsxTa1ZLfFfxNRcTBiiI0+VV8qjXqEsIg+Jd1Xa/YMehQRNI9 ZDXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7RkRJF9o2c3C5CMhU+t5ZhyG4d5D3mhoMdfolGfNI5A=; b=DzZIAoOuACc6bx6u5A5KPskuarQElp+72TMQ0F+mmD+hkOcWtpGUWdWrEPrEpgvUS2 Q8tsiGGvHkDhdAU5w1M53CSUkpZ5VKS29m96to1P6jong5APEKZogk4c8T48NY82GDDu YsJJPwLOBohGg3IE/aD3sp0/dow/na87JQkbGsP/uwMn3Sh1voHgdQ9U70ge1YsG8L9u 6C4qY1v2RtmykOR70l32tfPfSacG0yPmmwVjIbiKdkOAPziwBUPRHeI5K2L8er3tWOvC d4ET6sqkkMScyFUJehEjAppUtfrYbnWeCt8nD4qfFrDEHc13eJR4NxDOESRNdLbQr1Gr YlMQ== X-Gm-Message-State: AFqh2kotZfsPKN9AQJBQ23t54k8CjbvgIujsOgq4tm7NpoJ0ls6nDPql f5BrTwXizWSZj2geEO2Dqez3FPkV8r2+0nsn X-Google-Smtp-Source: AMrXdXtkO/6paE+LYEq5GnKwbTjr8zmBocj31mBuFluQuGG0URpBMEUiUaY9gvYtpN3u4jIFzZokFw== X-Received: by 2002:a05:6870:910f:b0:14b:cdc5:879 with SMTP id o15-20020a056870910f00b0014bcdc50879mr1390732oae.8.1671647003425; Wed, 21 Dec 2022 10:23:23 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:23 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 04/15] hw/riscv/boot.c: make riscv_find_firmware() static Date: Wed, 21 Dec 2022 15:22:49 -0300 Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The only caller is riscv_find_and_load_firmware(), which is in the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/boot.c | 44 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ebd351c840..7361d5c0d8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -75,6 +75,28 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, } } +static char *riscv_find_firmware(const char *firmware_filename) +{ + char *filename; + + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); + if (filename == NULL) { + if (!qtest_enabled()) { + /* + * We only ship OpenSBI binary bios images in the QEMU source. + * For machines that use images other than the default bios, + * running QEMU test will complain hence let's suppress the error + * report for QEMU testing. + */ + error_report("Unable to load the RISC-V firmware \"%s\"", + firmware_filename); + exit(1); + } + } + + return filename; +} + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, @@ -104,28 +126,6 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, return firmware_end_addr; } -char *riscv_find_firmware(const char *firmware_filename) -{ - char *filename; - - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); - if (filename == NULL) { - if (!qtest_enabled()) { - /* - * We only ship OpenSBI binary bios images in the QEMU source. - * For machines that use images other than the default bios, - * running QEMU test will complain hence let's suppress the error - * report for QEMU testing. - */ - error_report("Unable to load the RISC-V firmware \"%s\"", - firmware_filename); - exit(1); - } - } - - return filename; -} - target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 93e5f8760d..c03e4e74c5 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,7 +37,6 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); From patchwork Wed Dec 21 18:22:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C53EC4332F for ; Wed, 21 Dec 2022 18:24:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kZ-00087h-Pu; Wed, 21 Dec 2022 13:23:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kX-00084p-28 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:29 -0500 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kV-0007pB-9i for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:28 -0500 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1433ef3b61fso20094175fac.10 for ; Wed, 21 Dec 2022 10:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lZoBmiJkkWhRinFmahJoiZPpwFUsq8AacgVvO+2kw0k=; b=D8jkteHKZcZO7/7rlSOCuelx9sayuD4tvhC14Yvmpqk1hSkxqyKqCEWsiEzr6QwG4M oXGdxNgJJM1FRXk/rdKnJfO4kO52s43PDfx280R3hSpWaCgb97/PMRZmcNC5//u6qYI5 0ICGEtu+qdybpZPQVJz95NePmrzKRdLE0fK8xBpidh1AVFHD8kGqeDuaTT2HUjMiraWL NWjSc5qv6mDXM1OiEs85dAQF+f06+OmTf4E33s7xxGq8NhEcLWAE/VOl+EPU48anZlLh W3R9U52ovD1rKks5pmDqI+dsTMHagJgKVh/Utv41kMH4p276hqoVSbrsgW6Kk9ZfYJPy /65g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lZoBmiJkkWhRinFmahJoiZPpwFUsq8AacgVvO+2kw0k=; b=De1pfY24GRtJcpXqfh8lUzvQ+Eq/wlb84DEtJqWEnb2ynWcX09Xcfk7Jk7ta6qwd1K ifbkFJYUXABs4carRxhoEVSNK56BOV3tYHZ8VPxHSdlEJh7AG72avN8BD+dOs6T6cIZX mux0psFMtmUb5TsD7NIN4iP5dN0UcSdIcI9G7I21BQp26LtaybBq0Gd/HJ5BAsho1Sbs Ipkuf1AN/LfArvBXqCPGomytJrmyixhrnJXfrs84grM4pvOQUY5tD+3kStpsnJYG980/ 7QuHqjtBcvtneaWLgVIyoRELkI0TMrlBunE/OQ0m0AwO7oQ9SNrmEpgS/QBv/KjEL/nq VKoQ== X-Gm-Message-State: AFqh2kpzIuNavToPmbxfmCJY3sgzfTU+FmiZvs+sP7qDFkP8AKYMHr1f a/myF7HQdQamc52b8MkOKpz6xmthy3YQzeMS X-Google-Smtp-Source: AMrXdXsEZLLL8TsI/4+Rhx1NeV5ZeMmuZSvbsbhT0HGY5wHOWyxUzoNShQ46V1VBmcBjBHKIpsWVJA== X-Received: by 2002:a05:6870:aa86:b0:14b:ffbe:51d5 with SMTP id gr6-20020a056870aa8600b0014bffbe51d5mr7464747oab.5.1671647005859; Wed, 21 Dec 2022 10:23:25 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:25 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 05/15] hw/riscv/boot.c: introduce riscv_default_firmware_name() Date: Wed, 21 Dec 2022 15:22:50 -0300 Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some boards are duplicating the 'riscv_find_and_load_firmware' call because the 32 and 64 bits images have different names. Create a function to handle this detail instead of hardcoding it in the boards. Ideally we would bake this logic inside riscv_find_and_load_firmware(), or even create a riscv_load_default_firmware(), but at this moment we cannot infer whether the machine is running 32 or 64 bits without accessing RISCVHartArrayState, which in turn can't be accessed via the common code from boot.c. In the end we would exchange 'firmware_name' for a flag with riscv_is_32bit(), which isn't much better than what we already have today. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/boot.c | 9 +++++++++ hw/riscv/sifive_u.c | 11 ++++------- hw/riscv/spike.c | 14 +++++--------- hw/riscv/virt.c | 10 +++------- include/hw/riscv/boot.h | 1 + 5 files changed, 22 insertions(+), 23 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 7361d5c0d8..e1a544b1d9 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -75,6 +75,15 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, } } +const char *riscv_default_firmware_name(RISCVHartArrayState *harts) +{ + if (riscv_is_32bit(harts)) { + return RISCV32_BIOS_BIN; + } + + return RISCV64_BIOS_BIN; +} + static char *riscv_find_firmware(const char *firmware_filename) { char *filename; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9cf66957ab..ddceb750ea 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -533,6 +533,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *flash0 = g_new(MemoryRegion, 1); target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name; uint32_t start_addr_hi32 = 0x00000000; int i; uint32_t fdt_load_addr; @@ -595,13 +596,9 @@ static void sifive_u_machine_init(MachineState *machine) break; } - if (riscv_is_32bit(&s->soc.u_cpus)) { - firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV32_BIOS_BIN, start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV64_BIOS_BIN, start_addr, NULL); - } + firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, + start_addr, NULL); if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d96f013e2e..43341c20b6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -191,6 +191,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *system_memory = get_system_memory(); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name; uint32_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; @@ -261,15 +262,10 @@ static void spike_board_init(MachineState *machine) * keeping ELF files here was intentional because BIN files don't work * for the Spike machine as HTIF emulation depends on ELF parsing. */ - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, - htif_symbol_callback); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, - htif_symbol_callback); - } + firmware_name = riscv_default_firmware_name(&s->soc[0]); + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, + memmap[SPIKE_DRAM].base, + htif_symbol_callback); /* Load kernel */ if (machine->kernel_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..408f7a2256 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1237,6 +1237,7 @@ static void virt_machine_done(Notifier *notifier, void *data) MachineState *machine = MACHINE(s); target_ulong start_addr = memmap[VIRT_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); uint32_t fdt_load_addr; uint64_t kernel_entry; @@ -1256,13 +1257,8 @@ static void virt_machine_done(Notifier *notifier, void *data) } } - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV32_BIOS_BIN, start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV64_BIOS_BIN, start_addr, NULL); - } + firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, + start_addr, NULL); /* * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c03e4e74c5..60cf320c88 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,6 +37,7 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, symbol_fn_t sym_cb); +const char *riscv_default_firmware_name(RISCVHartArrayState *harts); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); From patchwork Wed Dec 21 18:22:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54D79C4332F for ; Wed, 21 Dec 2022 18:25:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kb-000893-DW; Wed, 21 Dec 2022 13:23:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kZ-00087X-Gy for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:31 -0500 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kX-0007qx-PX for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:31 -0500 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-143ffc8c2b2so20144478fac.2 for ; Wed, 21 Dec 2022 10:23:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tRuVtqu0y6HSFA/62eqdmXWh2hHPYGAd1pNKzZ7sbeQ=; b=G9mhRDhC/3y6Dc0dx3bWSGjJLdcFG3rBFAPpRXw/Axc6YuBI8NeRIywyJHj1KpZ6Q4 gmhbUnbd+UxbMl5lbkjYTuLCsCqYC0mbWlWm/3DGFqLyEKUROTKbgTlsssb4rhT199Ss I/fNSl5PYC4BmMoyrANRIP3ip2o3UV+XgKZIjSFSe7Jri2y09RlapDm7uEm9gy6XN7kA TjFGyJqC8H35F6l0BL//Qn1uboTClLeW/O3Mf3Q5rKBBkjFf4kF9bK016nxIfqnPJY3u 76K8Ry5ghcLiYeWpNIJz5BAWxJLYlKQ1HQT2oz6fyx5W64N3RGt4LydR+pXLROswHbOD LdbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tRuVtqu0y6HSFA/62eqdmXWh2hHPYGAd1pNKzZ7sbeQ=; b=Yr9CNyES0TtZTGTN/He3sM8j+DDTwV5YRzjq7niLjQlY+pVv+LiTrqp7ffYR5LYUH2 HkeM7qAaFDoPf06OYqcZCqP7RuNKKOKupkCAush8g+CW/tIVNgbKuDAuOSYZQqpikg/k mc6NO82d3E9ZYPeHWED52ZuVzpBX8UzVnMDS2bF6aKGhuEquwSGdL4vliTEZ0i8stSZz OMAf8PcKEc4dfqju49YFZfe45hADyt+/n6HmemtevVh6con8r7sSS/O9s2pWLI7p2OUh RvOM1ngK91Wb0mXsFfsf8hH1pHcpBl/clk6q+dhszMG2wuVYUhJSr4Z9TOPYZg325oYf h0iQ== X-Gm-Message-State: AFqh2kolv1vi76dxc2ySwCQw6mMiiHGQIpHRR4ddBqNTVsrjZfMLXKPM ZChyYfTylkgqC2w3EvA4Rd9H5frXDvmesXsA X-Google-Smtp-Source: AMrXdXsCRiPATMchVfMqj/9I+RyKRDzUMUpQx4yBTQDts9L2Z3CxW2qBINTUSTSz+lyohZYqhYMQJw== X-Received: by 2002:a05:6870:cd11:b0:144:b4d6:4df1 with SMTP id qk17-20020a056870cd1100b00144b4d64df1mr1002408oab.30.1671647008143; Wed, 21 Dec 2022 10:23:28 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 06/15] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Date: Wed, 21 Dec 2022 15:22:51 -0300 Message-Id: <20221221182300.307900-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This will make the code more in line with what the other boards are doing. We'll also avoid an extra check to machine->kernel_filename since we already checked that before executing riscv_load_kernel(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 43341c20b6..f37a9bebbf 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -257,6 +257,10 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); + /* Create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(&s->soc[0])); + /* * Not like other RISC-V machines that use plain binary bios images, * keeping ELF files here was intentional because BIN files don't work @@ -275,6 +279,17 @@ static void spike_board_init(MachineState *machine) kernel_entry = riscv_load_kernel(machine->kernel_filename, kernel_start_addr, htif_symbol_callback); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", + end); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode @@ -283,22 +298,6 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); - - /* Load initrd */ - if (machine->kernel_filename && machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); - } - /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, machine->ram_size, machine->fdt); From patchwork Wed Dec 21 18:22:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3ADE0C4332F for ; Wed, 21 Dec 2022 18:23:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kc-00089v-KM; Wed, 21 Dec 2022 13:23:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kb-00088t-7V for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:33 -0500 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kZ-0007og-G3 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:33 -0500 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-12c8312131fso20141788fac.4 for ; Wed, 21 Dec 2022 10:23:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nAtAM5x8S/ZPGivdQ7BsLDTU3Z8ReHOtMwCvIqWKh0Y=; b=HBlwcVDu9iVFKTK4tBYWOyBFAzl4mCuCo4VjFvK4Ej7pIgqYlQePhGSTysiOhU1Q80 8mU/8Rl1okoeSJGkJw8zyIOv1iNaI1qgAMFY2MN9EYUzL/9Fu9kuS62Odq67YkhbPgGS sI0Lg/xBjfSk0pndkctCqzeFgmdU9MkEZDcQR0PQtIPNhjBV+DGNf8rqNw7qcbyiFFb/ Cl9Qwol99kErlqOrMQHIWT8cGpU0oCr4LQELAgOICuWiHJLkEcyCLWeBkoS5zkDUIUQO UpOBk8Aneh1Bgufhd3HWbmdCMoA1cJIECfIDgyht0dWzojWlYa3jYDLvjEc5pZE4NnWh +EGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nAtAM5x8S/ZPGivdQ7BsLDTU3Z8ReHOtMwCvIqWKh0Y=; b=5aP37O1uXJN64g61+qf102ken1lEHJ69qT+aGFtwjqSc6gY0GeJzf5PRzcTeH9od2K iR7slYipUFg0+ObZ2MW+X0DEY4gWkoIw4sZPUYo3hLKlT2a8CbpZ9xxvEaW9EiilYpIU loGx1SzOajFx9tcLkDhmnN1pgPAj33O9xj55T5vaWJVi8tbjAX9QaonSnSsK+8Jvo62G gRyLVy1f9emRsJ+epZRjdVqC63donzUlsAmACpm7HJW0zHbXqy4947syHzGB0dQ+ldUQ caZdqJS/SxR0rX8q86kYjh/kYgi63tUM+J6CNlWy3gFld5YCceE4FnBhTYecdaL0sQ4L 0ryw== X-Gm-Message-State: AFqh2kpNX9g2MgcQJ6VIv73r1EWDKqDSjJ1FGMvQnseiWmQYbuT3iufg 4i6NHDzjr/owx+cIpkypHaBXtH8kUbEzDfA0 X-Google-Smtp-Source: AMrXdXuvfgsL9oFlrVso2wugD5+Ec2rd4GgEgZPhkgYnPuyyxL00s43vD2mkFmrHtmM3LNVpK8PNVg== X-Received: by 2002:a05:6871:468f:b0:144:870e:5859 with SMTP id ni15-20020a056871468f00b00144870e5859mr6715908oab.57.1671647010563; Wed, 21 Dec 2022 10:23:30 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:30 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 07/15] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Date: Wed, 21 Dec 2022 15:22:52 -0300 Message-Id: <20221221182300.307900-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org riscv_load_initrd() returns the initrd end addr while also writing a 'start' var to mark the addr start. These informations are being used just to write the initrd FDT node. Every existing caller of riscv_load_initrd() is writing the FDT in the same manner. We can simplify things by writing the FDT inside riscv_load_initrd(), sparing callers from having to manage start/end addrs to write the FDT themselves. An 'if (fdt)' check is already inserted at the end of the function because we'll end up using it later on with other boards that doesn´t have a FDT. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- hw/riscv/boot.c | 18 ++++++++++++------ hw/riscv/microchip_pfsoc.c | 10 ++-------- hw/riscv/sifive_u.c | 10 ++-------- hw/riscv/spike.c | 10 ++-------- hw/riscv/virt.c | 10 ++-------- include/hw/riscv/boot.h | 4 ++-- 6 files changed, 22 insertions(+), 40 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e1a544b1d9..8aed803d8c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -193,9 +193,10 @@ target_ulong riscv_load_kernel(const char *kernel_filename, exit(1); } -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start) +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt) { + hwaddr start, end; ssize_t size; /* @@ -209,18 +210,23 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, * halfway into RAM, and for boards with 256MB of RAM or more we put * the initrd at 128MB. */ - *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - size = load_ramdisk(filename, *start, mem_size - *start); + size = load_ramdisk(filename, start, mem_size - start); if (size == -1) { - size = load_image_targphys(filename, *start, mem_size - *start); + size = load_image_targphys(filename, start, mem_size - start); if (size == -1) { error_report("could not load ramdisk '%s'", filename); exit(1); } } - return *start + size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } } uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index b10321b564..593a799549 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,14 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-end", end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ddceb750ea..37f5087172 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -608,14 +608,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index f37a9bebbf..e08de61205 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -281,14 +281,8 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 408f7a2256..5967b136b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1291,14 +1291,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr, NULL); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 60cf320c88..6f4c606edc 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,8 +44,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start); +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, From patchwork Wed Dec 21 18:22:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B477FC4332F for ; Wed, 21 Dec 2022 18:26:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kf-0008Ai-GB; Wed, 21 Dec 2022 13:23:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83ke-0008A8-2F for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:36 -0500 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kc-0007s0-FJ for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:35 -0500 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1442977d77dso20122096fac.6 for ; Wed, 21 Dec 2022 10:23:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TlMNl+y5tE2XtGKVprHcbifOvzze22gNRp7j44Ksk+A=; b=hvyAZRW1huwQMKfWZ3QSyzVfJPUjOCBqXJOARO20Le1a5t3JRrWcDs9T2cPEx9ExoW t/TTNVCRMquwrzPChHiVluCdhWcLBZ6NurLbeyGJJEnC5ocbLTo8RtDhLZjKWmxki1FO TLHV7bzQ0oHVf4vikSjUEDLxJoqFZo6N9LKSTmGMk0ONhOEDYUD3O9jkGfGqYeGziwh+ HOiKq2EXPp5EVCYztp+iQCJFvsy4IuP97kbe7+ur9A7+EinWe6fau4oA8lTHJww42PZl 7i/BUrxNjnxgZJ4vcv9811ar5aa0fYrR2Airyh+puMthHc5mGUIlZeN3BAaN4morY67f d2tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TlMNl+y5tE2XtGKVprHcbifOvzze22gNRp7j44Ksk+A=; b=op2Zk/nFOC/ZP8KSZxyoXPvNGYhys6wnJE6+bmGLOFWm0YpnRD7OZHYBONYsAmFKP8 cMZ8pHDCK8VtXlm9qk2b1yV5/wNL8+ULoVpk9+bCvn8SBEn314QhN6E031u7i+Nl934L Xt9DHWv3JgPLL7dT1yO46IZqIO9DIb6f6PChACRSvfVeJmBN0VGBPoH3BMa+B+riqiCb PI5jCF4h+NUr75ybLlOqQVukDaCidfnVOJOPVanTwhDBuXenfuHeC3oQlKQYhVmc/lwc 2HyydSJ19ygbwh25OxCqZolIFPfrsLihq7hOFlxnxq1tVdi8HfpO1ESnSOwyRluR7DQS FTng== X-Gm-Message-State: AFqh2koFb2UMs6s727z9bltOIXuN92x67VM5pKg3UV4qSc9Q5PJrQpBn 45RnXHEB62OtC/K2c4zaBuGgCW8GOk7kswP7 X-Google-Smtp-Source: AMrXdXtmhQnHDRaMny7znpBe3fiDn6lkDsY6KzhAxtTHK6g3U5+wsaiIymhB4KVrrHRX78pBxqQ0iw== X-Received: by 2002:a05:6870:46a6:b0:148:15ba:886d with SMTP id a38-20020a05687046a600b0014815ba886dmr1630064oap.54.1671647013213; Wed, 21 Dec 2022 10:23:33 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:32 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 08/15] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Date: Wed, 21 Dec 2022 15:22:53 -0300 Message-Id: <20221221182300.307900-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The sifive_u, spike and virt machines are writing the 'bootargs' FDT node during their respective create_fdt(). Given that bootargs is written only when '-append' is used, and this option is only allowed with the '-kernel' option, which in turn is already being check before executing riscv_load_kernel(), write 'bootargs' in the same code path as riscv_load_kernel(). Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 11 +++++------ hw/riscv/spike.c | 9 +++++---- hw/riscv/virt.c | 11 +++++------ 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 37f5087172..3e6df87b5b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -117,7 +117,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { @@ -510,11 +509,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); g_free(nodename); - -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } static void sifive_u_machine_reset(void *opaque, int n, int level) @@ -611,6 +605,11 @@ static void sifive_u_machine_init(MachineState *machine) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index e08de61205..6d50abd425 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -178,10 +178,6 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); - - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } static void spike_board_init(MachineState *machine) @@ -284,6 +280,11 @@ static void spike_board_init(MachineState *machine) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5967b136b4..6c946b6def 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { mc->fdt = create_device_tree(&s->fdt_size); if (!mc->fdt) { @@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, create_fdt_fw_cfg(s, memmap); create_fdt_pmu(s); -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); - } - /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); @@ -1294,6 +1288,11 @@ static void virt_machine_done(Notifier *notifier, void *data) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode From patchwork Wed Dec 21 18:22:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F759C10F1B for ; Wed, 21 Dec 2022 18:24:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kh-0008FJ-HC; Wed, 21 Dec 2022 13:23:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kg-0008Av-15 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:38 -0500 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83ke-0007q9-Eh for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:37 -0500 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-142b72a728fso20120923fac.9 for ; Wed, 21 Dec 2022 10:23:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2cWUbrq1GsC2cyn2csFMCljmaagKBjvpjpYOjHyY9E0=; b=TnsFAACt1a5KRnSegU92UqGYf+YKgT1wB0+DjANGabSmkOo0XzsSIQyANYIB4Ux9iT 0iUtTPO1EP6GQUjMwrueoeiq4mLEgmDZg6TlM+slJ+w8aP2v3XPcxO+LMbw+bEgXdSFV ++NhYQNhu1gtqw3PXuIylhF8NvXEMOVSUgX56MUORn7rMPFJ3JAsxi56pR10Z5eLbHZy vR7O5chpU54iTFCjt2fxIzSYX5+PrpTP3Ow5yoCDFi3S+a/WZlZM9+aStItIKxvfC/lA XfMO83251TVJMxArjHqyKzeQ/9mGKoedh+yirZ80P8NvZeUwfPcckPVDfzrQlq1dpQbJ /VtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2cWUbrq1GsC2cyn2csFMCljmaagKBjvpjpYOjHyY9E0=; b=oDYgKK+KNpAXL6bQK7ybfYCKcDEv2FgS2TZ1JUVh2b3DVxA7Snqkc7NuNzAZ4hkqPA AraTz8XiTMcxB9xjiabFWMZ+EpI0gP4i4eUA6EtZ2eT4tPIvSJHVxZmArIQeEw5bW+H4 sS+Ww8SpVkUPLvc0F/XBBA8L/4QPONWR4eXXNYePqSwdyI+hBikdZxjpbrr38cPgBlML 86qrJHwSyuWUU8wRhfHjpCCCOWagvB1alEItaQtwwUkAxrhzjsIAYnFzRgGYcsfUEiIY 5VXvQbFX3dtcakMzxeqNmzVhJjAjIGXEjOqbwwhFBUmDhjIAar/qfTrIXX3ScuhP7MKg ZVpA== X-Gm-Message-State: AFqh2krcudJcEIBDRLu795Z8ineGeN/4rd3ZJ5M+N+UkiKwF7yZhYTFJ Jgvy8oFRcYz7EELKo91aYY27WdIivlmgfRGm X-Google-Smtp-Source: AMrXdXuB7YG6hfn8fbKy+KG0sXVDA0kIKH2zp/1ElIZr0iGp4Y0LwZLjr3rzgpcHV5PHGyb8eH5V8Q== X-Received: by 2002:a05:6870:494a:b0:137:3adc:6a39 with SMTP id fl10-20020a056870494a00b001373adc6a39mr1279890oab.39.1671647015513; Wed, 21 Dec 2022 10:23:35 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:35 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 09/15] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Date: Wed, 21 Dec 2022 15:22:54 -0300 Message-Id: <20221221182300.307900-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be retrieved by the MachineState object for all callers. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 3 +-- 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 8aed803d8c..4b46a9c51b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -193,9 +193,11 @@ target_ulong riscv_load_kernel(const char *kernel_filename, exit(1); } -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt) +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) { + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; hwaddr start, end; ssize_t size; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 593a799549..1e9b0a420e 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3e6df87b5b..c40885ed5c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -602,8 +602,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 6d50abd425..1eeee8f349 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -277,8 +277,7 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6c946b6def..02f1369843 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1285,8 +1285,7 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr, NULL); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 6f4c606edc..a2861c9431 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,8 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt); +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, From patchwork Wed Dec 21 18:22:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94AE3C10F1B for ; Wed, 21 Dec 2022 18:23:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kk-0008I1-IX; Wed, 21 Dec 2022 13:23:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83ki-0008GW-H7 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:40 -0500 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kg-0007oj-R1 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:40 -0500 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1445ca00781so20160813fac.1 for ; Wed, 21 Dec 2022 10:23:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UP1YWN/4d3fREVx8YBdysopigU4Qtv31qo0Og9ikRe4=; b=pZS0VV/n/art+54XSWvgOsfWojloytHat1IbY5P5lcJ6DPinBaaciRsgiagqbLxHPW IbUky+GEiCsADwp7K+9kakzykuM5IwB+L5QphY7qQ6rVRChb5U0TNJF0eKOSB9ywuOmq BLdSpza0w+zeLHTUUbuPQxoFbSmptyPHdVtUbkPbGNe7D45kBPEvByUlM0T/3twimvrh FPGKIkTa4srXPuo/Pu1VSuhrSTACXWiUnDjsOepTvJsDMAtwZzDWXwcrEwe5Viby3XwH vR16gVmmp6ARlaUi9rifVZFpnYpA+cO6eom3YggElPfJtQ4lHjJj0y5ME6Y4VeGblA5I AG6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UP1YWN/4d3fREVx8YBdysopigU4Qtv31qo0Og9ikRe4=; b=ETvqlTBnv0C2ZTxB/JFBqEdnp2LwCU36gBhL6w/4uNHK2FUPIGL3WKAcxyLiVMeKwd UyuKxTruaBpEe6MhP7v3SmslmOkwWPwZdDSN9tKCiweOkECIqFuG5q6neuNt0/pnKowi XFoojzBPGbXa2/nDcgrNeXsfmfC+XUhRLKGQpDJao7qJaW9Eh8XyBW47drRUO1dykWiH jMzarEU9tCcTOxL9xVR/WeDtteoE2T+a1zo7oDgqGcbPjc10mICInho7Na/9+U9uuGvO gtJnnt3JFnKPUKfrPKMQF0H+6dHgy+xSloeotWu2Ejh2x+ZvriavARJeA631Un+odNT9 youA== X-Gm-Message-State: AFqh2kphpk42mvZ7uCmBoPwIJwq7SX9SLjrh05C6hs586nJw0r3KU8a/ Jy1+ehNNJFhCWi9nzrh8lpgTyzYtBPy/o5Dt X-Google-Smtp-Source: AMrXdXsjWQqlsq0TZfgkI4hknWiBYvn7lrhslSZ2VrUzMGI/qaOXVtFFJ4bWLHGnPuKso3zMML8/yg== X-Received: by 2002:a05:6870:9e44:b0:144:fb4f:82a6 with SMTP id pt4-20020a0568709e4400b00144fb4f82a6mr1165516oab.56.1671647017935; Wed, 21 Dec 2022 10:23:37 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:37 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 10/15] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Date: Wed, 21 Dec 2022 15:22:55 -0300 Message-Id: <20221221182300.307900-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/opentitan.c | 3 +-- hw/riscv/sifive_e.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 8 files changed, 9 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4b46a9c51b..c79a08e6fe 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -160,10 +160,11 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { + const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; /* diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1e9b0a420e..82ae5e7023 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 85ffdac5be..64d5d435b9 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..3e3f4b0088 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c40885ed5c..bac394c959 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1eeee8f349..c9c69f92fc 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -272,8 +272,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, htif_symbol_callback); if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 02f1369843..c8e35f861e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index a2861c9431..2256b04986 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -41,7 +41,7 @@ const char *riscv_default_firmware_name(RISCVHartArrayState *harts); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); From patchwork Wed Dec 21 18:22:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BE87C4332F for ; Wed, 21 Dec 2022 18:25:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83km-0008JJ-Es; Wed, 21 Dec 2022 13:23:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kl-0008Ig-0v for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:43 -0500 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kj-0007p6-Ay for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:42 -0500 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-14455716674so20126416fac.7 for ; Wed, 21 Dec 2022 10:23:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R5/g+vsti7lSiZsONctWIYs7IL7csCnpYe9T5na6ABg=; b=pDWPuhUOwiwYEEKPle1SfOnDyv2BbQJXP+mg5kZe9uQwgzr2m/bXb1HzDqIpw1Vhq4 v0bq/DgVmDk6taXFBm2TiSk+CblReg9p6YSyeeTF4tJV+FAGnMFYiLFFgl9vSrLiKaqg 7TaS8+m+wJpONK3GFnjruvSXJ0QHxA1lssd4Mu3DwYVJ6CdyEjLaQZ2IIu7NjgGTjYJW UUG6CsevUlM1XuNNj+G7o2q8cSkrnL2L9TmyfHXHG7iOE/KqtFpNYyeaMgQ7D2pw3tvq b0FWY59uZaRhBJxHTlcZkrDJ7pgwwNkC6bjHLZAXfO/wUB5XhbPxo2ka3g3LAJPvnyFr JK8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R5/g+vsti7lSiZsONctWIYs7IL7csCnpYe9T5na6ABg=; b=xBJ1wKfOgx6KGMUyQ84ZgN2+F8/wjNzwIDBXqaDHxOiXDmoDzxjyn4E3WLqEOW+2l8 +uZw8U5eQ8FKrZp83ROds/z8CeWtRANywQcBFXiqYEpL6hXzqcYaDxvok4fCmyW/H70A cULjfkgs4aep9iZlx51E1PI3GBdCfdyjbxYP5gF4cygadUgQt1drsxa3p/xTK8qYhSZE cIuJDODxzC2LE/+ozhhm8rzclKUEEoxBWAsH49Mfk0wI77m13V2Rmja1MQz7BF6cTxYO dOPQrGyD8+oUkmVcePbt8tAr0S8dm9Pz7sWzrlqi6TnL8PpqZc9Ei4MkAK3vdP8sj5if X2Jg== X-Gm-Message-State: AFqh2kqZzIRYi4g5RPikupA2H4TyOsPhjOWy4WiJH8FM+Usks+K8Zf7g bIcrgOspc7+6wyNNi6pTC5Bsmh1CQVxpXHvO X-Google-Smtp-Source: AMrXdXsiTRF39pcr4kud/TzJUwgxBq6nvrr7YvTjseSCSuX1Y8rSW8RD38OkZBjMSMTJ0eJqxsnNdQ== X-Received: by 2002:a05:6871:8a6:b0:144:863a:8039 with SMTP id r38-20020a05687108a600b00144863a8039mr1582023oaq.21.1671647020396; Wed, 21 Dec 2022 10:23:40 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:40 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 11/15] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Wed, 21 Dec 2022 15:22:56 -0300 Message-Id: <20221221182300.307900-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. Every other board that uses riscv_load_kernel() will have this same behavior, including boards that doesn't have a valid FDT, so we need to take care to not do FDT operations without checking it first. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- hw/riscv/boot.c | 21 ++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 9 --------- hw/riscv/sifive_u.c | 9 --------- hw/riscv/spike.c | 9 --------- hw/riscv/virt.c | 9 --------- 5 files changed, 18 insertions(+), 39 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c79a08e6fe..afe5bae03d 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -166,6 +166,7 @@ target_ulong riscv_load_kernel(MachineState *machine, { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; /* * NB: Use low address not ELF entry point to ensure that the fw_dynamic @@ -177,21 +178,35 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..57fd6739a5 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -631,15 +631,6 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } - /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, machine->ram_size, machine->fdt); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bac394c959..0c9bf7fe6a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -599,15 +599,6 @@ static void sifive_u_machine_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c9c69f92fc..2b9af5689e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -274,15 +274,6 @@ static void spike_board_init(MachineState *machine) kernel_entry = riscv_load_kernel(machine, kernel_start_addr, htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c8e35f861e..11c903a212 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1282,15 +1282,6 @@ static void virt_machine_done(Notifier *notifier, void *data) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode From patchwork Wed Dec 21 18:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75120C4332F for ; Wed, 21 Dec 2022 18:24:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83ko-0008Ma-3w; Wed, 21 Dec 2022 13:23:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kn-0008LQ-D7 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:45 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kl-0007qV-Hy for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:44 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-14449b7814bso20155231fac.3 for ; Wed, 21 Dec 2022 10:23:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YZdFtJ+Ib6cOG1cjexHN2bKEmyb+yFYcJLvdmuWEz4U=; b=d2u5eBq376GcfsWJzOdvL89wnzregggnTUZHLJUOjGDmGzazp8X+V4V79p+pZM/A4m p4+LPuzEcRmrLhBn0SLfPfZkSD0UpJ3VaZ/jw7FHTKKF5St8QGlRXrSDhlDXJfZ3tw9/ huJXdXcDgOB1nSDtZCPsi3NmS76gGR53GiuDrCY6JKgIzjpC6/oHdFUOUsSv8FuKWt/V /A7PKhG6s1OhLeIORIvInKx+IAsRNkO/ZyLolBPt9l0RmBWCfS7Wh1VLcWqFWNaWtBPC kxHlY4hcnVOwgbX7U9clpf2+xRFXmAx8jD/s+zcQ5rDHYUn4SSEhKzPMHyyE7J3K1rZ1 wzqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YZdFtJ+Ib6cOG1cjexHN2bKEmyb+yFYcJLvdmuWEz4U=; b=tLCq7kPZvTn4vjmopmALbfzrv3QsrTlBtPiXdhOdlbt7AdWNmpp1N+xlyv3AjpnM8C 90vHt/xm8lfSp/B9otGVZt+Mv+fvgzfc2wpyyD3ZBEbc+uPHhSJ56Ev5yiPn2cVnSQQj 6q6Kq4H5w37FJlG6ijb8KdsQyVHUTJ9duK8jRc0QM4LLj9z8mdj5zWw79bbJJQGGGqkZ lPe/Nr3zfCHH0pVDvEL52azjN7yAIEbiBuNEXGPYk2EUdX8gOAaoYlcceNAWmRKgtB53 h4oD7dljqTRJYxzNA+8gJIFoxjTEnEgY1DUpXBkx1qCUBPpIFM5ZRabaxuMgFDu4lrLW 2+tA== X-Gm-Message-State: AFqh2kqEO53xxnNSlUT8l0aLMJHMLZpNOzRe3Noi4DKPcymucDDKicgz zMeSfPDoaYa0fgRErVrTQ9lI66MCPTwYwm2y X-Google-Smtp-Source: AMrXdXtTnYS7zDQ8487j8OcgKFMIYeHmr0u5eFlyHtcfUJjKYCnK1hgEk7nZv+G26+aj9RGBC5uJ2g== X-Received: by 2002:a05:6870:4d03:b0:143:bb26:dd09 with SMTP id pn3-20020a0568704d0300b00143bb26dd09mr1409196oab.35.1671647022597; Wed, 21 Dec 2022 10:23:42 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:42 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 12/15] hw/riscv/boot.c: make riscv_load_initrd() static Date: Wed, 21 Dec 2022 15:22:57 -0300 Message-Id: <20221221182300.307900-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The only remaining caller is riscv_load_kernel() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 76 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index afe5bae03d..55a3fc1a51 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -160,6 +160,44 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) @@ -209,44 +247,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 2256b04986..fde0633573 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,7 +44,6 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, From patchwork Wed Dec 21 18:22:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8605C4332F for ; Wed, 21 Dec 2022 18:24:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kq-0008OQ-TK; Wed, 21 Dec 2022 13:23:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kp-0008NY-8E for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:47 -0500 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kn-0007u2-RN for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:47 -0500 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-1322d768ba7so20146848fac.5 for ; Wed, 21 Dec 2022 10:23:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YCZj+C44vgbv4KDySdgyMP5uDwH1vphijk3niATbpoQ=; b=WkvVSKzWE336zqZ/chyAS51w1iSguphdkXkpjQruZvv6x1zLqrCOXuVvOuSuqWHBTj UCDefVmfmS1ThfrlWmPk8NIvr7FVTP5oFkuWeiDukks1srjSoWdBhJlT5VXF/0aSHdS8 Ea3vSQ/bfBVpQHanSrBJfqsYQHFFTMssEJwCW/iNqALsY0IHy7xOB9w8qfz1s9pZv3GH Pv2bJRqyIFPew18NIeo+UBPu9YjGbkqN/7QbR4InL1WNQ8J85w+jXKX5fcWHc09AbUvZ DoYc7fYIbDTRRgRyTe08u8GTAQzHOz5LPLI4Z5CcQKJRpK/XPEfKkx8JC4pzCSfbAPXt JTTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YCZj+C44vgbv4KDySdgyMP5uDwH1vphijk3niATbpoQ=; b=UhlaFOiKncW/hg6OYhzl7VfrLx6ZtEBppyjC3Yd3QVYzf00e7x/dYj+3XzL5AGhv78 BLezeg/91mze2TS+XpJULHVSyEPXFpd5XwdoTSAqldWteBPUqlri56senuJQS2pA8k7g Us35f92Gfj1e9YcDKLocpzQwE4FfElU3mchjGN4iGxTUhp6RhMlV0y3JRsJrH/GXc3TJ yn094eZmxyuvfYQfhVUdDBcozpUz3xjnJ7ZywO3CHmG5IeojpI6zqd5ZfDJmrUsnJUo7 CVnKgLrnO1KSkXy0ExgVySzRiQgBfP8eZWIz9/zXX5XQq/U7XCu4in2e8PdfN+pYMTqT sakw== X-Gm-Message-State: AFqh2koOrccSfM7GPm6usbo4knIKc+T610mHwe1X3TzQG20aP5qzBBVj ZVX8GLy8vo3axdhvhQ6MF2uUaJcj7/v/3Z0q X-Google-Smtp-Source: AMrXdXt+DZVgK/eIrczVphW5HIcxoEzN7aQ8NTKrNmEhLUv2HKvRRTESLkmXm6GwYItGrVcnADhpdA== X-Received: by 2002:a05:6871:894:b0:148:53c7:bf30 with SMTP id r20-20020a056871089400b0014853c7bf30mr1534337oaq.48.1671647024715; Wed, 21 Dec 2022 10:23:44 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 13/15] hw/riscv/spike.c: simplify create_fdt() Date: Wed, 21 Dec 2022 15:22:58 -0300 Message-Id: <20221221182300.307900-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 'mem_size' and 'cmdline' aren't being used and the MachineState pointer is being retrieved via a MACHINE() macro. Remove 'mem_size' and 'cmdline' and add MachineState as a parameter. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/spike.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2b9af5689e..181bf394a0 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -48,15 +48,14 @@ static const MemMapEntry spike_memmap[] = { [SPIKE_DRAM] = { 0x80000000, 0x0 }, }; -static void create_fdt(SpikeState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) +static void create_fdt(MachineState *mc, SpikeState *s, + const MemMapEntry *memmap, bool is_32_bit) { void *fdt; int fdt_size; uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc = MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; @@ -254,8 +253,7 @@ static void spike_board_init(MachineState *machine) mask_rom); /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + create_fdt(machine, s, memmap, riscv_is_32bit(&s->soc[0])); /* * Not like other RISC-V machines that use plain binary bios images, From patchwork Wed Dec 21 18:22:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E176C4332F for ; Wed, 21 Dec 2022 18:28:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83ks-0008SR-NB; Wed, 21 Dec 2022 13:23:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kr-0008OZ-66 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:49 -0500 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kp-0007rx-Ml for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:48 -0500 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-144b21f5e5fso20087314fac.12 for ; Wed, 21 Dec 2022 10:23:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UCo1YHm2H4SIqdKOmUrpwX43J8/JiKOmCLBYdwukgIg=; b=nbkickxKkDusAdflOl6IennIzQIF7amH+Q6DmXbOKlxtWUPkm9lLnqIi768miY7Jws KgCPVoPQc1dDY/3VXl7iAirx8fxbJz9HM2Ytk4ogmQBTyh6H4d/HUN7RRvKYVNJt/C9t ouwgUVrzy3D8qZ3f2EK2/EejIqw7CTLfntiKxmbyTD78OBUYibPX8nIL0Nx6zNg3+kcf BTyFGdXVvsTgMGh0XfWyH4MnOrv7sdr7r0WUa5ChMlP6Lm0QJcZ9KDI7BcqNE4d4ch3k ukDNXzf3JpkWu4/3Z52uPORvLh0ck2CI2Gz62tiUHJGVVZFP2gmGHkFZ+VY/xs3hVjyQ /yRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UCo1YHm2H4SIqdKOmUrpwX43J8/JiKOmCLBYdwukgIg=; b=HDtwvHcqUeb5w3hVHljHHM8oFDrkf6fG1+Lr2lMG0TbnczRfLaRnEQyqIc1uJ4FhQl qNPboJ+ktCmtfXAv4qm94XPLlKi96eKlZY2v5BE/AnrYgI5GH7/pdDbe++CTHl53ZByi MCD+Bl5Fv1BMij9qfEeqMNsYUSYtFDF9q5rzK9h9bozZbBroI4K0doDZlz69JzjAFeFm 7mGk17s14JSBc63oELjshtL9DLb6xZcLXcebCmvTlCEtEOw7TcGryBxEOoBpTOYtW0xM P8MxoRDVt5o1/m/Gy5h2nZ+t/agMqUPt9fL8U/Hon4Bq+uOAeFQ7UQZAFNz+IFY4GGyn ySlg== X-Gm-Message-State: AFqh2kr0/t7L9Zn9YMhX6DbSGHHaFY2VaAbxxmWsKcvzZxXfGyOefJBN 5DzLiUO+amZimsSywSMDRGIXSP2AEbWVeZ7p X-Google-Smtp-Source: AMrXdXvly/jXyJg7Apg5CkvGcD+/AS4YohlTaEqJ0VUFRSAsLI4/ST09RHfVsE6bNMMj5S4ZbyFv4Q== X-Received: by 2002:a05:6871:4501:b0:144:fc01:370 with SMTP id nj1-20020a056871450100b00144fc010370mr1237461oab.0.1671647026806; Wed, 21 Dec 2022 10:23:46 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 14/15] hw/riscv/virt.c: simplify create_fdt() Date: Wed, 21 Dec 2022 15:22:59 -0300 Message-Id: <20221221182300.307900-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 'mem_size' and 'cmdline' aren't being used and the MachineState pointer is being retrieved via a MACHINE() macro. Remove 'mem_size' and 'cmdline' and add MachineState as a parameter. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 11c903a212..b13299cee8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -998,10 +998,9 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) g_free(nodename); } -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) +static void create_fdt(MachineState *mc, RISCVVirtState *s, + const MemMapEntry *memmap, bool is_32_bit) { - MachineState *mc = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; uint8_t rng_seed[32]; @@ -1498,8 +1497,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + create_fdt(machine, s, memmap, riscv_is_32bit(&s->soc[0])); s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); From patchwork Wed Dec 21 18:23:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13079070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93E4EC4167B for ; Wed, 21 Dec 2022 18:25:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83kw-00009S-Dl; Wed, 21 Dec 2022 13:23:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83ku-00005F-Qc for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:52 -0500 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kt-0007p6-8y for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:52 -0500 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-14455716674so20126954fac.7 for ; Wed, 21 Dec 2022 10:23:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b+lO0sWlVx+Emu6U20opc5IL8+URL7UAx/BqzRgm2mA=; b=N0KRvNv9OR2OGHcwa7RPdWwr4hXgtHYPdMGnQpKOqW1IHfTUuTIDerTK9i5KV6nDRP 0HUZVTdg+D9jwJ3Z/jbPnrTDtrFErnFzO8VeqPV2CcBaidVHYDeAiNTmf23IkPLF+SPt 89Es72j6im7kR7Ddt8QthU3EuuEGZ/ccfn013ckAwpk5QPlrGUJ04mmz3vLKPq3x1vJN 8FNTtdvhIit3bE60Vs/zKwfTBE1hAW5mR7KULVcKMjxkrMtCa/r4dF36A4d1FaEsE0fW 8DleBf6mXXj4swJLde5BDc154RfE0hEcVMEdft/IzuUYqLbF5M1vJ4vO43AHZF6+YAIX n1Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b+lO0sWlVx+Emu6U20opc5IL8+URL7UAx/BqzRgm2mA=; b=vKXU0v/TY1wgxtDlxPG73GhZS4VOxcfbKAC/iY3kmZ9wGQQuwmsKsnaicZLwkbOlC2 0+gm3VH2zhZuvdHDsxiLmGEUVZqkLb3QDLy7aWVYExTIiLEJx6cSeQdim3LooLAsdAmL +Eesk35eQXsgsBRmlGvOToR5pWlvVL0qSAOsR/QME2CBY2YNSAV7Rb0e3wiUIzAtGRJg pPi4iNGbFRQtdMKwwaY2K4YiqXA4e7geTFedbDQ6a/AynS6aT3oxv69YuePDE8yo/wm0 7t1YykBk5OC70fB1+bjswrEK1kk33VP9ekWA7xX0DT1YhGvTqp2mTXqV1GEpsS9y8BAn 5B+w== X-Gm-Message-State: AFqh2kp4swPeisAGaWy/wKyPtS+WRNXzoyHLaiZJ1pODhJsV4a9deOXe rN5uwzlNoOZ+BfvlDEJYELR7VuEXMLRIlygL X-Google-Smtp-Source: AMrXdXt02TTh+GTXRAxrx5DGAs/pJjjl7+jTtIeC7J+Dh2Gp1jagDcX6gUNqJH4Q2PGpfMytqlVg2g== X-Received: by 2002:a05:6870:2f13:b0:144:81f0:7258 with SMTP id qj19-20020a0568702f1300b0014481f07258mr1062914oab.21.1671647030282; Wed, 21 Dec 2022 10:23:50 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH 15/15] hw/riscv/sifive_u: simplify create_fdt() Date: Wed, 21 Dec 2022 15:23:00 -0300 Message-Id: <20221221182300.307900-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org cmdline' isn't being used. A MachineState pointer is being retrieved via a MACHINE() macro calling qdev_get_machine(). 'mem_size' is being set as machine->ram_size. Remove the 'cmdline' and 'mem_size' parameters, add MachineState as a parameter to avoid the cast and retrieve 'mem_size' via ms->ram_size. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza --- hw/riscv/sifive_u.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 0c9bf7fe6a..97a561dc52 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -93,10 +93,10 @@ static const MemMapEntry sifive_u_memmap[] = { #define OTP_SERIAL 1 #define GEM_REVISION 0x10070109 -static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) +static void create_fdt(MachineState *ms, SiFiveUState *s, + const MemMapEntry *memmap, bool is_32_bit) { - MachineState *ms = MACHINE(qdev_get_machine()); + uint64_t mem_size = ms->ram_size; void *fdt; int cpu, fdt_size; uint32_t *cells; @@ -560,8 +560,7 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc.u_cpus)); + create_fdt(machine, s, memmap, riscv_is_32bit(&s->soc.u_cpus)); if (s->start_in_flash) { /*