From patchwork Thu Dec 22 08:25:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13079511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E95F8C001B2 for ; Thu, 22 Dec 2022 08:26:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E57410E51E; Thu, 22 Dec 2022 08:26:31 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 51E8910E517; Thu, 22 Dec 2022 08:26:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671697584; x=1703233584; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qN7eu68SRN3kOk9mSYnF/dTMHKU7Y8ch3Wm+DmnVDbQ=; b=IvVMVY0b7PBJ5hj/jJjYjXK8/5WvUjdDeAmeK5RUO1De+4NJSdy3luD7 yGEqg4izWTQEr2h1wCNT3aJt8W+/X8qTZkQUtGPtLQ2TQn6jIF7VehAHc wfCgrLlNpztsQPNAVKopRHtH1+Q2r6nH/aLeKHjWPvFFDhZmiEIhSr2aE tfL/1kfz3sJpRT12thse+3OOGwx15VKCAJYYjxeRlJPZ5ah6B6Bu6yT4N rKuOLXD7Rwu5AGBSWLb7Ux14DWaTcchVJ2ur30+7IW5w1aNIXgRPO68Mx i5EqtITM2BQQeDqF59u/RAznYYqAD7zYbHHQQ5ZoNWz9m1/ZWiRY8J2yl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="384426685" X-IronPort-AV: E=Sophos;i="5.96,265,1665471600"; d="scan'208";a="384426685" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 00:26:23 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="645127593" X-IronPort-AV: E=Sophos;i="5.96,265,1665471600"; d="scan'208";a="645127593" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 00:26:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 22 Dec 2022 00:25:54 -0800 Message-Id: <20221222082557.1364711-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222082557.1364711-1-lucas.demarchi@intel.com> References: <20221222082557.1364711-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/gt: Remove platform comments from workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The comments are redundant to the checks being done to apply the workarounds and very often get outdated as workarounds need to be extended to new platforms or steppings. Remove them altogether with the following matches (platforms extracted from intel_workarounds.c): find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \ 's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*/\1/' find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \ 's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*\*\//\1 Same things was executed in the gem directory, omitted here for brevity. There were a few false positives that included the workaround description. Those were manually patched. Signed-off-by: Lucas De Marchi Acked-by: Matt Roper --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 6 +- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 20 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/intel_reset.c | 4 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 10 +- drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 440 +++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 16 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +- 16 files changed, 266 insertions(+), 266 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index bc9521078807..a2a49cc25ca3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -46,7 +46,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *i915, if (!drm_mm_initialized(&i915->mm.stolen)) return -ENODEV; - /* WaSkipStolenMemoryFirstPage:bdw+ */ + /* WaSkipStolenMemoryFirstPage */ if (GRAPHICS_VER(i915) >= 8 && start < 4096) start = 4096; diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index e1c76e5bfa82..d7a40ed66d9e 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) if (GRAPHICS_VER(rq->engine->i915) == 9) vf_flush_wa = true; - /* WaForGAMHang:kbl */ + /* WaForGAMHang */ if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0)) dc_flush_wa = true; } @@ -189,7 +189,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) flags |= PIPE_CONTROL_FLUSH_L3; flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; - /* Wa_1409600907:tgl,adl-p */ + /* Wa_1409600907 */ flags |= PIPE_CONTROL_DEPTH_STALL; flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; flags |= PIPE_CONTROL_FLUSH_ENABLE; @@ -462,7 +462,7 @@ int gen8_emit_bb_start_noarb(struct i915_request *rq, return PTR_ERR(cs); /* - * WaDisableCtxRestoreArbitration:bdw,chv + * WaDisableCtxRestoreArbitration * * We don't need to perform MI_ARB_ENABLE as often as we do (in * particular all the gen that do not need the w/a at all!), if we @@ -657,7 +657,7 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs) return cs; } -/* Wa_14014475959:dg2 */ +/* Wa_14014475959 */ #define CCS_SEMAPHORE_PPHWSP_OFFSET 0x540 static u32 ccs_semaphore_offset(struct i915_request *rq) { @@ -665,7 +665,7 @@ static u32 ccs_semaphore_offset(struct i915_request *rq) (LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET; } -/* Wa_14014475959:dg2 */ +/* Wa_14014475959 */ static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs) { int i; @@ -704,7 +704,7 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) !intel_uc_uses_guc_submission(&rq->engine->gt->uc)) cs = gen12_emit_preempt_busywait(rq, cs); - /* Wa_14014475959:dg2 */ + /* Wa_14014475959 */ if (intel_engine_uses_wa_hold_ccs_switchout(rq->engine)) cs = ccs_emit_wa_busywait(rq, cs); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 99c4b866addd..ef45dfc6adae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1614,7 +1614,7 @@ static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) } /* - * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any + * Wa_22011802037 * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 49a8f10d76c7..9f232c743ee7 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -683,7 +683,7 @@ static u64 execlists_update_context(struct i915_request *rq) desc |= map_i915_prio_to_lrc_desc_prio(rq_prio(rq)); /* - * WaIdleLiteRestore:bdw,skl + * WaIdleLiteRestore * * We should never submit the context with the same RING_TAIL twice * just in case we submit an empty ring, which confuses the HW. @@ -2981,7 +2981,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) * Thus assume it is best to stop engines on all gens * where we have a gpu reset. * - * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES) + * WaKBLVECSSemaphoreWaitPoll * * FIXME: Wa for more modern gens needs to be validated */ @@ -2989,7 +2989,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) intel_engine_stop_cs(engine); /* - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need + * Wa_22011802037 * to wait for any pending mi force wakeups */ if (IS_GRAPHICS_VER(engine->i915, 11, 12)) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 7eeee5a7cb33..5b7244dceb67 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1126,7 +1126,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) GT_TRACE(gt, "invalidated engines %08x\n", awake); - /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ + /* Wa_2207587034 */ if (awake && (IS_TIGERLAKE(i915) || IS_DG1(i915) || diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index e37164a60d37..25d4b554cf25 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -409,7 +409,7 @@ void gtt_write_workarounds(struct intel_gt *gt) * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ + /* WaIncreaseDefaultTLBEntries */ if (IS_BROADWELL(i915)) intel_uncore_write(uncore, GEN8_L3_LRA_1_GPGPU, diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7771a19008c6..8dc764781b1a 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1389,12 +1389,12 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_cmd_buf_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs); - /* Wa_22011450934:dg2 */ + /* Wa_22011450934 */ if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(ce->engine->i915, G11, STEP_A0, STEP_B0)) cs = dg2_emit_rcs_hang_wabb(ce, cs); - /* Wa_16013000631:dg2 */ + /* Wa_16013000631 */ if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) || IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); @@ -1417,7 +1417,7 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_timestamp_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs); - /* Wa_16013000631:dg2 */ + /* Wa_16013000631 */ if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) || IS_DG2_G11(ce->engine->i915)) if (ce->engine->class == COMPUTE_CLASS) @@ -1654,14 +1654,14 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) */ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) { - /* WaDisableCtxRestoreArbitration:bdw,chv */ + /* WaDisableCtxRestoreArbitration */ *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; - /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ + /* WaFlushCoherentL3CacheLinesAtContextSwitch */ if (IS_BROADWELL(engine->i915)) batch = gen8_emit_flush_coherentl3_wa(engine, batch); - /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ + /* WaClearSlmSpaceAtContextSwitch */ /* Actual scratch location is at 128 bytes offset */ batch = gen8_emit_pipe_control(batch, PIPE_CONTROL_FLUSH_L3 | @@ -1707,7 +1707,7 @@ static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) { static const struct lri lri[] = { - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ + /* WaDisableGatherAtSetShaderCommonSlice */ { COMMON_SLICE_CHICKEN2, __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, @@ -1731,10 +1731,10 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ + /* WaFlushCoherentL3CacheLinesAtContextSwitch */ batch = gen8_emit_flush_coherentl3_wa(engine, batch); - /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */ + /* WaClearSlmSpaceAtContextSwitch */ batch = gen8_emit_pipe_control(batch, PIPE_CONTROL_FLUSH_L3 | PIPE_CONTROL_STORE_DATA_INDEX | @@ -1744,7 +1744,7 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); - /* WaMediaPoolStateCmdInWABB:bxt,glk */ + /* WaMediaPoolStateCmdInWABB */ if (HAS_POOLED_EU(engine->i915)) { /* * EU pool configuration is setup along with golden context diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 69b489e8dfed..b7f56a788424 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -509,7 +509,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, if (GEM_DEBUG_WARN_ON(table->size > table->n_entries)) return 0; - /* WaDisableSkipCaching:skl,bxt,kbl,glk */ + /* WaDisableSkipCaching */ if (GRAPHICS_VER(i915) == 9) { int i; diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 2ee4051e4d96..9cb04e9a4c13 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -156,7 +156,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { /* - * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only + * WaRsDoubleRc6WrlWithCoarsePowerGating * when CPG is enabled */ set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); @@ -206,7 +206,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_EI_MODE(1); /* - * WaRsDisableCoarsePowerGating:skl,cnl + * WaRsDisableCoarsePowerGating * - Render/Media PG need to be disabled with RC6. */ if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index ffde89c5835a..f59d38a5e2a0 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -201,7 +201,7 @@ static int g4x_do_reset(struct intel_gt *gt, struct intel_uncore *uncore = gt->uncore; int ret; - /* WaVcpClkGateDisableForMediaReset:ctg,elk */ + /* WaVcpClkGateDisableForMediaReset */ intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, 0, VCP_UNIT_CLOCK_GATE_DISABLE); intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D); @@ -613,7 +613,7 @@ static int gen8_reset_engines(struct intel_gt *gt, } /* - * Wa_22011100796:dg2, whenever Full soft reset is required, + * Wa_22011100796 * reset all individual engines firstly, and then do a full soft reset. * * This is best effort, so ignore any error from the initial reset. diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 827adb0cfaea..704b50467ce3 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -317,10 +317,10 @@ static void reset_prepare(struct intel_engine_cs *engine) * Thus assume it is best to stop engines on all gens * where we have a gpu reset. * - * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES) + * WaKBLVECSSemaphoreWaitPoll * - * WaMediaResetMainRingCleanup:ctg,elk (presumably) - * WaClearRingBufHeadRegAtInit:ctg,elk + * WaMediaResetMainRingCleanup + * WaClearRingBufHeadRegAtInit * * FIXME: Wa for more modern gens needs to be validated */ @@ -714,7 +714,7 @@ static int mi_set_context(struct i915_request *rq, if (IS_ERR(cs)) return PTR_ERR(cs); - /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ + /* WaProgramMiArbOnOffAroundMiSetContext */ if (GRAPHICS_VER(i915) == 7) { *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; if (num_engines) { @@ -765,7 +765,7 @@ static int mi_set_context(struct i915_request *rq, *cs++ = i915_ggtt_offset(ce->state) | flags; /* * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP - * WaMiSetContext_Hang:snb,ivb,vlv + * WaMiSetContext_Hang */ *cs++ = MI_NOOP; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 9ad3bc7201cb..4eeddd60c95b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1443,7 +1443,7 @@ static bool vlv_rps_enable(struct intel_rps *rps) GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_CONT); - /* WaGsvRC0ResidencyMethod:vlv */ + /* WaGsvRC0ResidencyMethod */ rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED; vlv_punit_get(i915); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bf84efb3f15f..edfa7d98a409 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -314,10 +314,10 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, { wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); - /* WaDisableAsyncFlipPerfMode:bdw,chv */ + /* WaDisableAsyncFlipPerfMode */ wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); - /* WaDisablePartialInstShootdown:bdw,chv */ + /* WaDisablePartialInstShootdown */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); @@ -325,8 +325,8 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, * workaround for a possible hang in the unlikely event a TLB * invalidation occurs during a PSD flush. */ - /* WaForceEnableNonCoherent:bdw,chv */ - /* WaHdcDisableFetchWhenMasked:bdw,chv */ + /* WaForceEnableNonCoherent */ + /* WaHdcDisableFetchWhenMasked */ wa_masked_en(wal, HDC_CHICKEN0, HDC_DONOT_FETCH_MEM_WHEN_MASKED | HDC_FORCE_NON_COHERENT); @@ -341,7 +341,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, */ wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); - /* Wa4x4STCOptimizationDisable:bdw,chv */ + /* Wa4x4STCOptimizationDisable */ wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); /* @@ -364,10 +364,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, gen8_ctx_workarounds_init(engine, wal); - /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ + /* WaDisableThreadStallDopClockGating */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); - /* WaDisableDopClockGating:bdw + /* WaDisableDopClockGating * * Also see the related UCGTCL1 write in bdw_init_clock_gating() * to disable EUTC clock gating. @@ -379,9 +379,9 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, GEN8_SAMPLER_POWER_BYPASS_DIS); wa_masked_en(wal, HDC_CHICKEN0, - /* WaForceContextSaveRestoreNonCoherent:bdw */ + /* WaForceContextSaveRestoreNonCoherent */ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | - /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ + /* WaDisableFenceDestinationToSLM */ (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); } @@ -390,7 +390,7 @@ static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, { gen8_ctx_workarounds_init(engine, wal); - /* WaDisableThreadStallDopClockGating:chv */ + /* WaDisableThreadStallDopClockGating */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); /* Improve HiZ throughput on CHV. */ @@ -403,7 +403,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, struct drm_i915_private *i915 = engine->i915; if (HAS_LLC(i915)) { - /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl + /* WaCompressedResourceSamplerPbeMediaNewHashMode * * Must match Display Engine. See * WaCompressedResourceDisplayNewHashMode. @@ -414,29 +414,29 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); } - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ - /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ + /* WaClearFlowControlGpgpuContextSave */ + /* WaDisablePartialInstShootdown */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, FLOW_CONTROL_ENABLE | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); - /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ - /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ + /* WaEnableYV12BugFixInHalfSliceChicken7 */ + /* WaEnableSamplerGPGPUPreemptionSupport */ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_YV12_BUGFIX | GEN9_ENABLE_GPGPU_PREEMPTION); - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ - /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ + /* Wa4x4STCOptimizationDisable */ + /* WaDisablePartialResolveInVc */ wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ + /* WaCcsTlbPrefetchDisable */ wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); - /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ + /* WaForceContextSaveRestoreNonCoherent */ wa_masked_en(wal, HDC_CHICKEN0, HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); @@ -454,11 +454,11 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, * a TLB invalidation occurs during a PSD flush. */ - /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ + /* WaForceEnableNonCoherent */ wa_masked_en(wal, HDC_CHICKEN0, HDC_FORCE_NON_COHERENT); - /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ + /* WaDisableSamplerPowerBypassForSOPingPong */ if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || @@ -466,7 +466,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ + /* WaDisableSTUnitPowerOptimization */ wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); /* @@ -480,15 +480,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, * while maintaining old contract with userspace. */ - /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ + /* WaDisable3DMidCmdPreemption */ wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); - /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ + /* WaDisableGPGPUMidCmdPreemption */ wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); - /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ + /* WaClearHIZ_WM_CHICKEN3 */ if (IS_GEN9_LP(i915)) wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); } @@ -545,11 +545,11 @@ static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, { gen9_ctx_workarounds_init(engine, wal); - /* WaDisableThreadStallDopClockGating:bxt */ + /* WaDisableThreadStallDopClockGating */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); - /* WaToEnableHwFixForPushConstHWBug:bxt */ + /* WaToEnableHwFixForPushConstHWBug */ wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); } @@ -561,12 +561,12 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, gen9_ctx_workarounds_init(engine, wal); - /* WaToEnableHwFixForPushConstHWBug:kbl */ + /* WaToEnableHwFixForPushConstHWBug */ if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); - /* WaDisableSbeCacheDispatchPortSharing:kbl */ + /* WaDisableSbeCacheDispatchPortSharing */ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } @@ -576,7 +576,7 @@ static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, { gen9_ctx_workarounds_init(engine, wal); - /* WaToEnableHwFixForPushConstHWBug:glk */ + /* WaToEnableHwFixForPushConstHWBug */ wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); } @@ -586,11 +586,11 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, { gen9_ctx_workarounds_init(engine, wal); - /* WaToEnableHwFixForPushConstHWBug:cfl */ + /* WaToEnableHwFixForPushConstHWBug */ wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); - /* WaDisableSbeCacheDispatchPortSharing:cfl */ + /* WaDisableSbeCacheDispatchPortSharing */ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } @@ -598,13 +598,13 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { - /* Wa_1406697149 (WaDisableBankHangMode:icl) */ + /* Wa_1406697149 (WaDisableBankHangMode */ wa_write(wal, GEN8_L3CNTLREG, intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | GEN8_ERRDETBCTRL); - /* WaForceEnableNonCoherent:icl + /* WaForceEnableNonCoherent * This is not the same workaround as in early Gen9 platforms, where * lacking this could cause system hangs, but coherency performance * overhead is high and only a few compute workloads really need it @@ -613,13 +613,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, */ wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); - /* WaEnableFloatBlendOptimization:icl */ + /* WaEnableFloatBlendOptimization */ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 0 /* write-only, so skip validation */, true); - /* WaDisableGPGPUMidThreadPreemption:icl */ + /* WaDisableGPGPUMidThreadPreemption */ wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); @@ -628,13 +628,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, GEN11_SAMPLER_ENABLE_HEADLESS_MSG); - /* Wa_1604278689:icl,ehl */ + /* Wa_1604278689 */ wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 0, /* write-only register; skip validation */ 0xFFFFFFFF); - /* Wa_1406306137:icl,ehl */ + /* Wa_1406306137 */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } @@ -668,7 +668,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, * workaround. * * Note that the programming of this register is further modified - * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. + * according to the FF_MODE2 guidance given by Wa_1608008084 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong * value when read. The default value for this register is zero for all * fields and there are no bit masks. So instead of doing a RMW we @@ -690,21 +690,21 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, gen12_ctx_gt_tuning_init(engine, wal); /* - * Wa_1409142259:tgl,dg1,adl-p - * Wa_1409347922:tgl,dg1,adl-p - * Wa_1409252684:tgl,dg1,adl-p - * Wa_1409217633:tgl,dg1,adl-p - * Wa_1409207793:tgl,dg1,adl-p - * Wa_1409178076:tgl,dg1,adl-p - * Wa_1408979724:tgl,dg1,adl-p - * Wa_14010443199:tgl,rkl,dg1,adl-p - * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p - * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p + * Wa_1409142259 + * Wa_1409347922 + * Wa_1409252684 + * Wa_1409217633 + * Wa_1409207793 + * Wa_1409178076 + * Wa_1408979724 + * Wa_14010443199 + * Wa_14010698770 + * Wa_1409342910 */ wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); - /* WaDisableGPGPUMidThreadPreemption:gen12 */ + /* WaDisableGPGPUMidThreadPreemption */ wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); @@ -745,44 +745,44 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, { dg2_ctx_gt_tuning_init(engine, wal); - /* Wa_16011186671:dg2_g11 */ + /* Wa_16011186671 */ if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); } if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { - /* Wa_14010469329:dg2_g10 */ + /* Wa_14010469329 */ wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); /* - * Wa_22010465075:dg2_g10 - * Wa_22010613112:dg2_g10 - * Wa_14010698770:dg2_g10 + * Wa_22010465075 + * Wa_22010613112 + * Wa_14010698770 */ wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); } - /* Wa_16013271637:dg2 */ + /* Wa_16013271637 */ wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, MSC_MSAA_REODER_BUF_BYPASS_DISABLE); - /* Wa_14014947963:dg2 */ + /* Wa_14014947963 */ if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); - /* Wa_18018764978:dg2 */ + /* Wa_18018764978 */ if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); - /* Wa_15010599737:dg2 */ + /* Wa_15010599737 */ wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); - /* Wa_18019271663:dg2 */ + /* Wa_18019271663 */ wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); } @@ -955,7 +955,7 @@ static void gen4_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ + /* WaDisable_RenderCache_OperationalFlush */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); } @@ -964,7 +964,7 @@ g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { gen4_gt_workarounds_init(gt, wal); - /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ + /* WaDisableRenderCachePipelinedFlush */ wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); } @@ -984,27 +984,27 @@ snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) static void ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ + /* Apply the WaDisableRHWOOptimizationForRenderHang */ wa_masked_dis(wal, GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); - /* WaApplyL3ControlAndL3ChickenMode:ivb */ + /* WaApplyL3ControlAndL3ChickenMode */ wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); - /* WaForceL3Serialization:ivb */ + /* WaForceL3Serialization */ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); } static void vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { - /* WaForceL3Serialization:vlv */ + /* WaForceL3Serialization */ wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); /* - * WaIncreaseL3CreditsForVLVB0:vlv + * WaIncreaseL3CreditsForVLVB0 * This is the hardware default actually. */ wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); @@ -1021,7 +1021,7 @@ hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 0 /* XXX does this reg exist? */, true); - /* WaVSRefCountFullforceMissDisable:hsw */ + /* WaVSRefCountFullforceMissDisable */ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); } @@ -1035,7 +1035,7 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) GEM_BUG_ON(GRAPHICS_VER(i915) != 9); /* - * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml + * WaProgramMgsrForCorrectSliceSpecificMmioReads * Before any MMIO read into slice/subslice specific registers, MCR * packet control register needs to be programmed to point to any * enabled s/ss pair. Otherwise, incorrect values will be returned. @@ -1068,17 +1068,17 @@ gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { struct drm_i915_private *i915 = gt->i915; - /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ + /* WaProgramMgsrForCorrectSliceSpecificMmioReads */ gen9_wa_init_mcr(i915, wal); - /* WaDisableKillLogic:bxt,skl,kbl */ + /* WaDisableKillLogic */ if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) wa_write_or(wal, GAM_ECOCHK, ECOCHK_DIS_TLB); if (HAS_LLC(i915)) { - /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl + /* WaCompressedResourceSamplerPbeMediaNewHashMode * * Must match Display Engine. See * WaCompressedResourceDisplayNewHashMode. @@ -1088,7 +1088,7 @@ gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) MMCD_PCLA | MMCD_HOTSPOT_EN); } - /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ + /* WaDisableHDCInvalidation */ wa_write_or(wal, GAM_ECOCHK, BDW_DISABLE_HDC_INVALIDATION); @@ -1099,12 +1099,12 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { gen9_gt_workarounds_init(gt, wal); - /* WaDisableGafsUnitClkGating:skl */ + /* WaDisableGafsUnitClkGating */ wa_write_or(wal, GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); - /* WaInPlaceDecompressionHang:skl */ + /* WaInPlaceDecompressionHang */ if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) wa_write_or(wal, GEN9_GAMT_ECO_REG_RW_IA, @@ -1116,18 +1116,18 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { gen9_gt_workarounds_init(gt, wal); - /* WaDisableDynamicCreditSharing:kbl */ + /* WaDisableDynamicCreditSharing */ if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); - /* WaDisableGafsUnitClkGating:kbl */ + /* WaDisableGafsUnitClkGating */ wa_write_or(wal, GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); - /* WaInPlaceDecompressionHang:kbl */ + /* WaInPlaceDecompressionHang */ wa_write_or(wal, GEN9_GAMT_ECO_REG_RW_IA, GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); @@ -1144,12 +1144,12 @@ cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { gen9_gt_workarounds_init(gt, wal); - /* WaDisableGafsUnitClkGating:cfl */ + /* WaDisableGafsUnitClkGating */ wa_write_or(wal, GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); - /* WaInPlaceDecompressionHang:cfl */ + /* WaInPlaceDecompressionHang */ wa_write_or(wal, GEN9_GAMT_ECO_REG_RW_IA, GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); @@ -1327,13 +1327,13 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) icl_wa_init_mcr(gt, wal); - /* WaModifyGamTlbPartitioning:icl */ + /* WaModifyGamTlbPartitioning */ wa_write_clr_set(wal, GEN11_GACB_PERF_CTRL, GEN11_HASH_CTRL_MASK, GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); - /* Wa_1405766107:icl + /* Wa_1405766107 * Formerly known as WaCL2SFHalfMaxAlloc */ wa_write_or(wal, @@ -1341,30 +1341,30 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); - /* Wa_220166154:icl + /* Wa_220166154 * Formerly known as WaDisCtxReload */ wa_write_or(wal, GEN8_GAMW_ECO_DEV_RW_IA, GAMW_ECO_DEV_CTX_RELOAD_DISABLE); - /* Wa_1406463099:icl + /* Wa_1406463099 * Formerly known as WaGamTlbPendError */ wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); - /* Wa_1407352427:icl,ehl */ + /* Wa_1407352427 */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, PSDUNIT_CLKGATE_DIS); - /* Wa_1406680159:icl,ehl */ + /* Wa_1406680159 */ wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, GWUNIT_CLKGATE_DIS); - /* Wa_1607087056:icl,ehl,jsl */ + /* Wa_1607087056 */ if (IS_ICELAKE(i915) || IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, @@ -1405,10 +1405,10 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { icl_wa_init_mcr(gt, wal); - /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ + /* Wa_14011060649 */ wa_14011060649(gt, wal); - /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ + /* Wa_14011059788 */ wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); } @@ -1419,19 +1419,19 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) gen12_gt_workarounds_init(gt, wal); - /* Wa_1409420604:tgl */ + /* Wa_1409420604 */ if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS); - /* Wa_1607087056:tgl also know as BUG:1409180338 */ + /* Wa_1607087056 */ if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, GEN11_SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); - /* Wa_1408615072:tgl[a0] */ + /* Wa_1408615072 */ if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); @@ -1444,19 +1444,19 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) gen12_gt_workarounds_init(gt, wal); - /* Wa_1607087056:dg1 */ + /* Wa_1607087056 */ if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, GEN11_SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); - /* Wa_1409420604:dg1 */ + /* Wa_1409420604 */ if (IS_DG1(i915)) wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS); - /* Wa_1408615072:dg1 */ + /* Wa_1408615072 */ /* Empirical testing shows this register is unaffected by engine reset. */ if (IS_DG1(i915)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, @@ -1470,15 +1470,15 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) xehp_init_mcr(gt, wal); - /* Wa_1409757795:xehpsdv */ + /* Wa_1409757795 */ wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); - /* Wa_16011155590:xehpsdv */ + /* Wa_16011155590 */ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, TSGUNIT_CLKGATE_DIS); - /* Wa_14011780169:xehpsdv */ + /* Wa_14011780169 */ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | GAMTLBVDBOX7_CLKGATE_DIS | @@ -1509,11 +1509,11 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMTLBVEBOX0_CLKGATE_DIS); } - /* Wa_16012725990:xehpsdv */ + /* Wa_16012725990 */ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); - /* Wa_14011060649:xehpsdv */ + /* Wa_14011060649 */ wa_14011060649(gt, wal); } @@ -1525,7 +1525,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) xehp_init_mcr(gt, wal); - /* Wa_14011060649:dg2 */ + /* Wa_14011060649 */ wa_14011060649(gt, wal); /* @@ -1539,33 +1539,33 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) if (engine->class != VIDEO_DECODE_CLASS) continue; - /* Wa_16010515920:dg2_g10 */ + /* Wa_16010515920 */ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), ALNUNIT_CLKGATE_DIS); } if (IS_DG2_G10(gt->i915)) { - /* Wa_22010523718:dg2 */ + /* Wa_22010523718 */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS); - /* Wa_14011006942:dg2 */ + /* Wa_14011006942 */ wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS); } if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { - /* Wa_14010948348:dg2_g10 */ + /* Wa_14010948348 */ wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); - /* Wa_14011037102:dg2_g10 */ + /* Wa_14011037102 */ wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); - /* Wa_14011371254:dg2_g10 */ + /* Wa_14011371254 */ wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); - /* Wa_14011431319:dg2_g10 */ + /* Wa_14011431319 */ wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS | @@ -1594,15 +1594,15 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS); - /* Wa_14010569222:dg2_g10 */ + /* Wa_14010569222 */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS); - /* Wa_14011028019:dg2_g10 */ + /* Wa_14011028019 */ wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); } - /* Wa_14014830051:dg2 */ + /* Wa_14014830051 */ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); /* @@ -1898,16 +1898,16 @@ whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) static void gen9_whitelist_build(struct i915_wa_list *w) { - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ + /* WaVFEStateAfterPipeControlwithMediaStateClear */ whitelist_reg(w, GEN9_CTX_PREEMPT_REG); - /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ + /* WaEnablePreemptionGranularityControlByUMD */ whitelist_reg(w, GEN8_CS_CHICKEN1); - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ + /* WaAllowUMDToModifyHDCChicken1 */ whitelist_reg(w, GEN8_HDC_CHICKEN1); - /* WaSendPushConstantsFromMMIO:skl,bxt */ + /* WaSendPushConstantsFromMMIO */ whitelist_reg(w, COMMON_SLICE_CHICKEN2); } @@ -1920,7 +1920,7 @@ static void skl_whitelist_build(struct intel_engine_cs *engine) gen9_whitelist_build(w); - /* WaDisableLSQCROPERFforOCL:skl */ + /* WaDisableLSQCROPERFforOCL */ whitelist_mcr_reg(w, GEN8_L3SQCREG4); } @@ -1941,7 +1941,7 @@ static void kbl_whitelist_build(struct intel_engine_cs *engine) gen9_whitelist_build(w); - /* WaDisableLSQCROPERFforOCL:kbl */ + /* WaDisableLSQCROPERFforOCL */ whitelist_mcr_reg(w, GEN8_L3SQCREG4); } @@ -1968,7 +1968,7 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) gen9_whitelist_build(w); /* - * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml + * WaAllowPMDepthAndInvocationCountAccessFromUMD * * This covers 4 register which are next to one another : * - PS_INVOCATION_COUNT @@ -2006,17 +2006,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) switch (engine->class) { case RENDER_CLASS: - /* WaAllowUMDToModifyHalfSliceChicken7:icl */ + /* WaAllowUMDToModifyHalfSliceChicken7 */ whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); - /* WaAllowUMDToModifySamplerMode:icl */ + /* WaAllowUMDToModifySamplerMode */ whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); - /* WaEnableStateCacheRedirectToCS:icl */ + /* WaEnableStateCacheRedirectToCS */ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); /* - * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl + * WaAllowPMDepthAndInvocationCountAccessFromUMD * * This covers 4 register which are next to one another : * - PS_INVOCATION_COUNT @@ -2055,8 +2055,8 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) switch (engine->class) { case RENDER_CLASS: /* - * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl - * Wa_1408556865:tgl + * WaAllowPMDepthAndInvocationCountAccessFromUMD + * Wa_1408556865 * * This covers 4 registers which are next to one another : * - PS_INVOCATION_COUNT @@ -2069,13 +2069,13 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_RANGE_4); /* - * Wa_1808121037:tgl - * Wa_14012131227:dg1 - * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p + * Wa_1808121037 + * Wa_14012131227 + * Wa_1508744258 */ whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); - /* Wa_1806527549:tgl */ + /* Wa_1806527549 */ whitelist_reg(w, HIZ_CHICKEN); break; default: @@ -2111,7 +2111,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) switch (engine->class) { case RENDER_CLASS: /* - * Wa_1507100340:dg2_g10 + * Wa_1507100340 * * This covers 4 registers which are next to one another : * - PS_INVOCATION_COUNT @@ -2126,7 +2126,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) break; case COMPUTE_CLASS: - /* Wa_16011157294:dg2_g10 */ + /* Wa_16011157294 */ if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) whitelist_reg(w, GEN9_CTX_PREEMPT_REG); break; @@ -2157,7 +2157,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine) { allow_read_ctx_timestamp(engine); - /* Wa_16014440446:pvc */ + /* Wa_16014440446 */ blacklist_trtt(engine); } @@ -2279,26 +2279,26 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) struct drm_i915_private *i915 = engine->i915; if (IS_DG2(i915)) { - /* Wa_1509235366:dg2 */ + /* Wa_1509235366 */ wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); } if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { - /* Wa_14013392000:dg2_g11 */ + /* Wa_14013392000 */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); } if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || IS_DG2_G11(i915) || IS_DG2_G12(i915)) { - /* Wa_1509727124:dg2 */ + /* Wa_1509727124 */ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB); } if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { - /* Wa_14012419201:dg2 */ + /* Wa_14012419201 */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); } @@ -2306,19 +2306,19 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || IS_DG2_G11(i915)) { /* - * Wa_22012826095:dg2 - * Wa_22013059131:dg2 + * Wa_22012826095 + * Wa_22013059131 */ wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, MAXREQS_PER_BANK, REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); - /* Wa_22013059131:dg2 */ + /* Wa_22013059131 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT); } - /* Wa_1308578152:dg2_g10 when first gslice is fused off */ + /* Wa_1308578152 */ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && needs_wa_1308578152(engine)) { wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, @@ -2327,17 +2327,17 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || IS_DG2_G11(i915) || IS_DG2_G12(i915)) { - /* Wa_22013037850:dg2 */ + /* Wa_22013037850 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DISABLE_128B_EVICTION_COMMAND_UDW); - /* Wa_22012856258:dg2 */ + /* Wa_22012856258 */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION); /* - * Wa_22010960976:dg2 - * Wa_14013347512:dg2 + * Wa_22010960976 + * Wa_14013347512 */ wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); @@ -2345,14 +2345,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { /* - * Wa_1608949956:dg2_g10 - * Wa_14010198302:dg2_g10 + * Wa_1608949956 + * Wa_14010198302 */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); /* - * Wa_14010918519:dg2_g10 + * Wa_14010918519 * * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, * so ignoring verification. @@ -2363,41 +2363,41 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { - /* Wa_22010430635:dg2 */ + /* Wa_22010430635 */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_GRF_CLEAR); - /* Wa_14010648519:dg2 */ + /* Wa_14010648519 */ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); } - /* Wa_14013202645:dg2 */ + /* Wa_14013202645 */ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); - /* Wa_22012532006:dg2 */ + /* Wa_22012532006 */ if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { - /* Wa_14010680813:dg2_g10 */ + /* Wa_14010680813 */ wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); } if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { - /* Wa_14012362059:dg2 */ + /* Wa_14012362059 */ wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); } if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || IS_DG2_G10(i915)) { - /* Wa_22014600077:dg2 */ + /* Wa_22014600077 */ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 0 /* Wa_14012342262 write-only reg, so skip verification */, @@ -2407,8 +2407,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { /* - * Wa_1607138336:tgl[a0],dg1[a0] - * Wa_1607063988:tgl[a0],dg1[a0] + * Wa_1607138336 + * Wa_1607063988 */ wa_write_or(wal, GEN9_CTX_PREEMPT_REG, @@ -2417,8 +2417,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { /* - * Wa_1606679103:tgl - * (see also Wa_1606682166:icl) + * Wa_1606679103 + * (see also Wa_1606682166 */ wa_write_or(wal, GEN7_SARCHKMD, @@ -2427,14 +2427,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ + /* Wa_1606931601 */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); /* - * Wa_1407928979:tgl A* - * Wa_18011464164:tgl[B0+],dg1[B0+] - * Wa_22010931296:tgl[B0+],dg1[B0+] - * Wa_14010919138:rkl,dg1,adl-s,adl-p + * Wa_1407928979 + * Wa_18011464164 + * Wa_22010931296 + * Wa_14010919138 */ wa_write_or(wal, GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE); @@ -2443,10 +2443,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { /* - * Wa_1606700617:tgl,dg1,adl-p - * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p - * Wa_14010826681:tgl,dg1,rkl,adl-p - * Wa_18019627453:dg2 + * Wa_1606700617 + * Wa_22010271021 + * Wa_14010826681 + * Wa_18019627453 */ wa_masked_en(wal, GEN9_CS_DEBUG_MODE1, @@ -2456,13 +2456,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ + /* Wa_1409804808 */ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); /* - * Wa_1409085225:tgl - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p + * Wa_1409085225 + * Wa_14010229206 */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); } @@ -2470,9 +2470,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl,rkl,dg1[a0],adlp + * Wa_1607030317 + * Wa_1607186500 + * Wa_1607297627 * * On TGL and RKL there are multiple entries for this WA in the * BSpec; some indicate this is an A0-only WA, others indicate @@ -2487,7 +2487,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { - /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ + /* Wa_1406941453 */ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, ENABLE_SMALLPL); @@ -2500,7 +2500,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); /* - * Wa_1405543622:icl + * Wa_1405543622 * Formerly known as WaGAPZPriorityScheme */ wa_write_or(wal, @@ -2508,7 +2508,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN11_ARBITRATION_PRIO_ORDER_MASK); /* - * Wa_1604223664:icl + * Wa_1604223664 * Formerly known as WaL3BankAddressHashing */ wa_write_clr_set(wal, @@ -2521,38 +2521,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN11_BANK_HASH_ADDR_EXCL_BIT0); /* - * Wa_1405733216:icl + * Wa_1405733216 * Formerly known as WaDisableCleanEvicts */ wa_mcr_write_or(wal, GEN8_L3SQCREG4, GEN11_LQSC_CLEAN_EVICT_DISABLE); - /* Wa_1606682166:icl */ + /* Wa_1606682166 */ wa_write_or(wal, GEN7_SARCHKMD, GEN7_DISABLE_SAMPLER_PREFETCH); - /* Wa_1409178092:icl */ + /* Wa_1409178092 */ wa_mcr_write_clr_set(wal, GEN11_SCRATCH2, GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 0); - /* WaEnable32PlaneMode:icl */ + /* WaEnable32PlaneMode */ wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, GEN11_ENABLE_32_PLANE_MODE); /* - * Wa_1408615072:icl,ehl (vsunit) - * Wa_1407596294:icl,ehl (hsunit) + * Wa_1408615072 + * Wa_1407596294 */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); /* - * Wa_1408767742:icl[a2..forever],ehl[all] - * Wa_1605460711:icl[a0..c0] + * Wa_1408767742 + * Wa_1605460711 */ wa_write_or(wal, GEN7_FF_THREAD_MODE, @@ -2627,31 +2627,31 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { - /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ + /* WaEnableGapsTsvCreditFix */ wa_write_or(wal, GEN8_GARBCNTL, GEN9_GAPS_TSV_CREDIT_DISABLE); } if (IS_BROXTON(i915)) { - /* WaDisablePooledEuLoadBalancingFix:bxt */ + /* WaDisablePooledEuLoadBalancingFix */ wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); } if (GRAPHICS_VER(i915) == 9) { - /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ + /* WaContextSwitchWithConcurrentTLBInvalidate */ wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ + /* WaEnableLbsSlaRetryTimerDecrement */ wa_mcr_write_or(wal, BDW_SCRATCH1, GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); - /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ + /* WaProgramL3SqcReg1DefaultForPerf */ if (IS_GEN9_LP(i915)) wa_mcr_write_clr_set(wal, GEN8_L3SQCREG1, @@ -2659,7 +2659,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2)); - /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ + /* WaOCLCoherentLineFlush */ wa_mcr_write_or(wal, GEN8_L3SQCREG4, GEN8_LQSC_FLUSH_COHERENT_LINES); @@ -2674,7 +2674,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_HASWELL(i915)) { - /* WaSampleCChickenBitEnable:hsw */ + /* WaSampleCChickenBitEnable */ wa_masked_en(wal, HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); @@ -2685,13 +2685,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_VALLEYVIEW(i915)) { - /* WaDisableEarlyCull:vlv */ + /* WaDisableEarlyCull */ wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); /* - * WaVSThreadDispatchOverride:ivb,vlv + * WaVSThreadDispatchOverride * * This actually overrides the dispatch * mode for all thread types. @@ -2703,8 +2703,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN7_FF_VS_SCHED_HW | GEN7_FF_DS_SCHED_HW); - /* WaPsdDispatchEnable:vlv */ - /* WaDisablePSDDualDispatchEnable:vlv */ + /* WaPsdDispatchEnable */ + /* WaDisablePSDDualDispatchEnable */ wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, GEN7_MAX_PS_THREAD_DEP | @@ -2712,7 +2712,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_IVYBRIDGE(i915)) { - /* WaDisableEarlyCull:ivb */ + /* WaDisableEarlyCull */ wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); @@ -2725,7 +2725,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } /* - * WaVSThreadDispatchOverride:ivb,vlv + * WaVSThreadDispatchOverride * * This actually overrides the dispatch * mode for all thread types. @@ -2737,7 +2737,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN7_FF_VS_SCHED_HW | GEN7_FF_DS_SCHED_HW); - /* WaDisablePSDDualDispatchEnable:ivb */ + /* WaDisablePSDDualDispatchEnable */ if (IS_IVB_GT1(i915)) wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, @@ -2745,17 +2745,17 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (GRAPHICS_VER(i915) == 7) { - /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ + /* WaBCSVCSTlbInvalidationMode */ wa_masked_en(wal, RING_MODE_GEN7(RENDER_RING_BASE), GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); - /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ + /* WaDisable_RenderCache_OperationalFlush */ wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); /* * BSpec says this must be set, even though - * WaDisable4x2SubspanOptimization:ivb,hsw + * WaDisable4x2SubspanOptimization * WaDisable4x2SubspanOptimization isn't listed for VLV. */ wa_masked_en(wal, @@ -2782,7 +2782,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * order to use MI_WAIT_FOR_EVENT within the CS. It should * already be programmed to '1' on all products. * - * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv + * WaDisableAsyncFlipPerfMode */ wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), @@ -2792,20 +2792,20 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) /* * Required for the hardware to program scanline values for * waiting - * WaEnableFlushTlbInvalidationMode:snb + * WaEnableFlushTlbInvalidationMode */ wa_masked_en(wal, GFX_MODE, GFX_TLB_INVALIDATE_EXPLICIT); - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ + /* WaDisableHiZPlanesWhenMSAAEnabled */ wa_masked_en(wal, _3D_CHICKEN, _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); wa_masked_en(wal, _3D_CHICKEN3, - /* WaStripsFansDisableFastClipPerformanceFix:snb */ + /* WaStripsFansDisableFastClipPerformanceFix */ _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | /* * Bspec says: @@ -2828,7 +2828,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4); - /* WaDisable_RenderCache_OperationalFlush:snb */ + /* WaDisable_RenderCache_OperationalFlush */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); /* @@ -2843,7 +2843,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_GRAPHICS_VER(i915, 4, 6)) - /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ + /* WaTimedSingleVertexDispatch */ wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), /* XXX bit doesn't stick on Broadwater */ @@ -2871,7 +2871,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct drm_i915_private *i915 = engine->i915; - /* WaKBLVECSSemaphoreWaitPoll:kbl */ + /* WaKBLVECSSemaphoreWaitPoll */ if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { wa_write(wal, RING_SEMA_WAIT_POLL(engine->mmio_base), @@ -2883,7 +2883,7 @@ static void ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { - /* Wa_14014999345:pvc */ + /* Wa_14014999345 */ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); } } @@ -2960,38 +2960,38 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li GEN9_ROW_CHICKEN4, GEN12_DISABLE_GRF_CLEAR); - /* Wa_14010670810:xehpsdv */ + /* Wa_14010670810 */ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); - /* Wa_14010449647:xehpsdv */ + /* Wa_14010449647 */ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); - /* Wa_18011725039:xehpsdv */ + /* Wa_18011725039 */ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); } - /* Wa_14012362059:xehpsdv */ + /* Wa_14012362059 */ wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); - /* Wa_14014368820:xehpsdv */ + /* Wa_14014368820 */ wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); } if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { - /* Wa_14015227452:dg2,pvc */ + /* Wa_14015227452 */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); - /* Wa_22014226127:dg2,pvc */ + /* Wa_22014226127 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); - /* Wa_16015675438:dg2,pvc */ + /* Wa_16015675438 */ wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); - /* Wa_18018781329:dg2,pvc */ + /* Wa_18018781329 */ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); @@ -3000,12 +3000,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li if (IS_DG2(i915)) { /* - * Wa_16011620976:dg2_g11 - * Wa_22015475538:dg2 + * Wa_16011620976 + * Wa_22015475538 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); - /* Wa_18017747507:dg2 */ + /* Wa_18017747507 */ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index c0b5aa6fde26..2fea87ab9493 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -265,22 +265,22 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) struct intel_gt *gt = guc_to_gt(guc); u32 flags = 0; - /* Wa_22012773006:gen11,gen12 < XeHP */ + /* Wa_22012773006 */ if (GRAPHICS_VER(gt->i915) >= 11 && GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50)) flags |= GUC_WA_POLLCS; - /* Wa_16011759253:dg2_g10:a0 */ + /* Wa_16011759253 */ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) flags |= GUC_WA_GAM_CREDITS; - /* Wa_14014475959:dg2 */ + /* Wa_14014475959 */ if (IS_DG2(gt->i915)) flags |= GUC_WA_HOLD_CCS_SWITCHOUT; /* - * Wa_14012197797:dg2_g10:a0,dg2_g11:a0 - * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12 + * Wa_14012197797 + * Wa_22011391025 * * The same WA bit is used for both and 22011391025 is applicable to * all DG2. @@ -292,14 +292,14 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (IS_GRAPHICS_VER(gt->i915, 11, 12)) flags |= GUC_WA_PRE_PARSER; - /* Wa_16011777198:dg2 */ + /* Wa_16011777198 */ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) flags |= GUC_WA_RCS_RESET_BEFORE_RC6; /* - * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..) - * Wa_22012727685:dg2_g11[a0..) + * Wa_22012727170 + * Wa_22012727685 */ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 53f7f599cde3..663058a1211b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1621,7 +1621,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine) intel_engine_stop_cs(engine); /* - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need + * Wa_22011802037 * to wait for any pending mi force wakeups */ intel_engine_wait_for_pending_mi_fw(engine); @@ -4201,7 +4201,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine) engine->flags |= I915_ENGINE_HAS_PREEMPTION; engine->flags |= I915_ENGINE_HAS_TIMESLICES; - /* Wa_14014475959:dg2 */ + /* Wa_14014475959 */ if (IS_DG2(engine->i915) && engine->class == COMPUTE_CLASS) engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 9a8a1abf71d7..f612b654dc76 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -489,8 +489,8 @@ static int __uc_init_hw(struct intel_uc *uc) intel_guc_reset_interrupts(guc); - /* WaEnableuKernelHeaderValidFix:skl */ - /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ + /* WaEnableuKernelHeaderValidFix */ + /* WaEnableGuCBootHashCheckNotSet */ if (GRAPHICS_VER(i915) == 9) attempts = 3; else From patchwork Thu Dec 22 08:25:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13079512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE01FC001B2 for ; Thu, 22 Dec 2022 08:26:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01E1C10E520; Thu, 22 Dec 2022 08:26:43 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 205D710E516; Thu, 22 Dec 2022 08:26:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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22 Dec 2022 00:26:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 22 Dec 2022 00:25:55 -0800 Message-Id: <20221222082557.1364711-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222082557.1364711-1-lucas.demarchi@intel.com> References: <20221222082557.1364711-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] fixup! drm/i915/gt: Remove platform comments from workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++---- 5 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index ef45dfc6adae..25a982925cf2 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1614,7 +1614,7 @@ static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) } /* - * Wa_22011802037 + * Wa_22011802037 - In addition to stopping the cs, we need to wait for any * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 9f232c743ee7..1510255f6a50 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2989,7 +2989,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) intel_engine_stop_cs(engine); /* - * Wa_22011802037 + * Wa_22011802037 - In addition to stopping the cs, we need * to wait for any pending mi force wakeups */ if (IS_GRAPHICS_VER(engine->i915, 11, 12)) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index f59d38a5e2a0..b3ea634958d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -613,7 +613,7 @@ static int gen8_reset_engines(struct intel_gt *gt, } /* - * Wa_22011100796 + * Wa_22011100796 - whenever Full soft reset is required, * reset all individual engines firstly, and then do a full soft reset. * * This is best effort, so ignore any error from the initial reset. diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 704b50467ce3..5414df579341 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -317,9 +317,9 @@ static void reset_prepare(struct intel_engine_cs *engine) * Thus assume it is best to stop engines on all gens * where we have a gpu reset. * - * WaKBLVECSSemaphoreWaitPoll + * WaKBLVECSSemaphoreWaitPoll - on ALL_ENGINES * - * WaMediaResetMainRingCleanup + * WaMediaResetMainRingCleanup - presumably * WaClearRingBufHeadRegAtInit * * FIXME: Wa for more modern gens needs to be validated diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index edfa7d98a409..b01af1ed2382 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1425,7 +1425,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS); - /* Wa_1607087056 */ + /* Wa_1607087056 - also know as BUG:1409180338 */ if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, GEN11_SLICE_UNIT_LEVEL_CLKGATE, @@ -2318,7 +2318,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) FORCE_1_SUB_MESSAGE_PER_FRAGMENT); } - /* Wa_1308578152 */ + /* Wa_1308578152 - when first gslice is fused off */ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && needs_wa_1308578152(engine)) { wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, @@ -2417,8 +2417,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { /* - * Wa_1606679103 - * (see also Wa_1606682166 + * Wa_1606679103 - see also Wa_1606682166 */ wa_write_or(wal, GEN7_SARCHKMD, From patchwork Thu Dec 22 08:25:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13079509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95338C4167B for ; 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a="384426686" X-IronPort-AV: E=Sophos;i="5.96,265,1665471600"; d="scan'208";a="384426686" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 00:26:23 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="645127599" X-IronPort-AV: E=Sophos;i="5.96,265,1665471600"; d="scan'208";a="645127599" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 00:26:22 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 22 Dec 2022 00:25:56 -0800 Message-Id: <20221222082557.1364711-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222082557.1364711-1-lucas.demarchi@intel.com> References: <20221222082557.1364711-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915: Remove platform comments from workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The comments are redundant to the checks being done to apply the workarounds and very often get outdated as workarounds need to be extended to new platforms or steppings. Remove them altogether with the following matches (platforms extracted from intel_workarounds.c): find drivers/gpu/drm/i915/ -name '*.c' | xargs sed -i -E \ 's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*/\1/' find drivers/gpu/drm/i915/ -name '*.c' | xargs sed -i -E \ 's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*\*\//\1 There were a few false positives that included the workaround description. Those were manually patched. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/icl_dsi.c | 10 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 20 +-- .../drm/i915/display/intel_display_power.c | 8 +- .../i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 10 +- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- .../drm/i915/display/intel_modeset_setup.c | 4 +- .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 24 ++-- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- drivers/gpu/drm/i915/display/intel_vga.c | 2 +- .../drm/i915/display/skl_universal_plane.c | 6 +- drivers/gpu/drm/i915/display/skl_watermark.c | 8 +- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 10 +- drivers/gpu/drm/i915/intel_pm.c | 132 +++++++++--------- drivers/gpu/drm/i915/intel_uncore.c | 8 +- 26 files changed, 135 insertions(+), 135 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index c3580d96765c..7e6e51b496aa 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -261,7 +261,7 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, temp |= HDMI_AUDIO_ENABLE; /* - * WaEnableHDMI8bpcBefore12bpc:snb,ivb + * WaEnableHDMI8bpcBefore12bpc * * The procedure for 12bpc is as follows: * 1. disable HDMI clock gating diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ecaeb7dc196b..dc26f2716dcb 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -807,7 +807,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) num_formats = ARRAY_SIZE(vlv_primary_formats); } else if (DISPLAY_VER(dev_priv) >= 4) { /* - * WaFP16GammaEnabling:ivb + * WaFP16GammaEnabling * "Workaround : When using the 64-bit format, the plane * output on each color channel has one quarter amplitude. * It can be brought up to full amplitude by using pipe diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ae14c794c4bc..eff1c46d6ab2 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1241,7 +1241,7 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state, } /* - * Wa_1409054076:icl,jsl,ehl + * Wa_1409054076 * When pipe A is disabled and MIPI DSI is enabled on pipe B, * the AMT KVMR feature will incorrectly see pipe A as enabled. * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave @@ -1259,7 +1259,7 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, } /* - * Wa_16012360555:adl-p + * Wa_16012360555 * SW will have to program the "LP to HS Wakeup Guardband" * to account for the repeaters on the HS Request/Ready * PPI signaling between the Display engine and the DPHY. @@ -1288,10 +1288,10 @@ static void gen11_dsi_enable(struct intel_atomic_state *state, drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); - /* Wa_1409054076:icl,jsl,ehl */ + /* Wa_1409054076 */ icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); - /* Wa_16012360555:adl-p */ + /* Wa_16012360555 */ adlp_set_lp_hs_wakeup_gb(encoder); /* step6d: enable dsi transcoder */ @@ -1456,7 +1456,7 @@ static void gen11_dsi_disable(struct intel_atomic_state *state, /* step2d,e: disable transcoder and wait */ gen11_dsi_disable_transcoder(encoder); - /* Wa_1409054076:icl,jsl,ehl */ + /* Wa_1409054076 */ icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); /* step2f,g: powerdown panel */ diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 10e1fc9d0698..fe9ca39bdfbd 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -557,7 +557,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr * once the sprite has been enabled. * * - * WaCxSRDisabledForSpriteScaling:ivb + * WaCxSRDisabledForSpriteScaling * IVB SPR_SCALE/Scaling Enable * "Low Power watermarks must be disabled for at least one * frame before enabling sprite scaling, and kept disabled diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0c107a38f9d0..2ea764c40a36 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3350,7 +3350,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.cdclk.table = dg2_cdclk_table; } else if (IS_ALDERLAKE_P(dev_priv)) { dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; - /* Wa_22011320316:adl-p[a0] */ + /* Wa_22011320316 */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; else diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index d190fa0d393b..9e10eebc8463 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -380,7 +380,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) cntl |= MCURSOR_ROTATE_180; - /* Wa_22012358565:adl-p */ + /* Wa_22012358565 */ if (DISPLAY_VER(dev_priv) == 13) cntl |= MCURSOR_ARB_SLOTS(1); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e75b9b2a0e01..c93b0bccc934 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -300,7 +300,7 @@ skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); } -/* Wa_2006604312:icl,ehl */ +/* Wa_2006604312 */ static void icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) @@ -313,7 +313,7 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); } -/* Wa_1604331009:icl,jsl,ehl */ +/* Wa_1604331009 */ static void icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) @@ -560,7 +560,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) /* FIXME: assert CPU port conditions for SNB+ */ } - /* Wa_22012358565:adl-p */ + /* Wa_22012358565 */ if (DISPLAY_VER(dev_priv) == 13) intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 0, PIPE_ARB_USE_PROG_SLOTS); @@ -1031,7 +1031,7 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) else if (DISPLAY_VER(dev_priv) >= 13) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; - /* Wa_14010547955:dg2 */ + /* Wa_14010547955 */ if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) tmp |= DG2_RENDER_CCSTAG_4_3_EN; @@ -1167,7 +1167,7 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - /* Wa_2006604312:icl,ehl */ + /* Wa_2006604312 */ if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) return true; @@ -1178,7 +1178,7 @@ static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - /* Wa_1604331009:icl,jsl,ehl */ + /* Wa_1604331009 */ if (is_hdr_mode(crtc_state) && crtc_state->active_planes & BIT(PLANE_CURSOR) && DISPLAY_VER(dev_priv) == 11) @@ -1356,12 +1356,12 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, needs_nv12_wa(new_crtc_state)) skl_wa_827(dev_priv, pipe, true); - /* Wa_2006604312:icl,ehl */ + /* Wa_2006604312 */ if (!needs_scalerclk_wa(old_crtc_state) && needs_scalerclk_wa(new_crtc_state)) icl_wa_scalerclkgating(dev_priv, pipe, true); - /* Wa_1604331009:icl,jsl,ehl */ + /* Wa_1604331009 */ if (!needs_cursorclk_wa(old_crtc_state) && needs_cursorclk_wa(new_crtc_state)) icl_wa_cursorclkgating(dev_priv, pipe, true); @@ -1384,7 +1384,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, * one frame before enabling scaling. LP watermarks can be re-enabled * when scaling is disabled. * - * WaCxSRDisabledForSpriteScaling:ivb + * WaCxSRDisabledForSpriteScaling */ if (old_crtc_state->hw.active && new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) @@ -8213,7 +8213,7 @@ intel_mode_valid(struct drm_device *dev, /* * Cantiga+ cannot handle modes with a hsync front porch of 0. - * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. + * WaPruneModeWithIncorrectHsyncOffset */ if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && mode->hsync_start == mode->hdisplay) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 1a23ecd4623a..2265f48ba215 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1583,7 +1583,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) - /* Wa_1409767108:tgl,dg1,adl-s */ + /* Wa_1409767108 */ table = wa_1409767108_buddy_page_masks; else table = tgl_buddy_page_masks; @@ -1604,7 +1604,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), table[config].page_mask); - /* Wa_22010178259:tgl,dg1,rkl,adl-s */ + /* Wa_22010178259 */ if (DISPLAY_VER(dev_priv) == 12) intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), BW_BUDDY_TLB_REQ_TIMER_MASK, @@ -1622,7 +1622,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ + /* Wa_14011294188 */ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1) intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, @@ -1669,7 +1669,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (resume) intel_dmc_load_program(dev_priv); - /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */ + /* Wa_14011508470 */ if (DISPLAY_VER(dev_priv) >= 12) { val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 8710dd41ffd4..284b89a865e7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -341,7 +341,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : SKL_PW_CTL_IDX_TO_PG(pw_idx); - /* Wa_16013190616:adlp */ + /* Wa_16013190616 */ if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 905b5dcdca14..76f3ba74a1f1 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -391,7 +391,7 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) return; /* - * Wa_16015201720:adl-p,dg2, mtl + * Wa_16015201720 * The WA requires clock gating to be disabled all the time * for pipe A and B. * For pipe C and D clock gating needs to be disabled only diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index c236aafe9be0..5484c55386ea 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1901,7 +1901,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) if (pipe != PIPE_A) { /* - * WaPixelRepeatModeFixForC0:chv + * WaPixelRepeatModeFixForC0 * * DPLLCMD is AWOL. Use chicken bits to propagate * the value from DPLLBMD to either pipe B or C. diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 1974eb580ed1..3b3c0a98a773 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3804,7 +3804,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte pll->info->id != DPLL_ID_ICL_DPLL0) return; /* - * Wa_16011069516:adl-p[a0] + * Wa_16011069516 * * All CMTG regs are unreliable until CMTG clock gating is disabled, * so we can only assume the default TRANS_CMTG_CHICKEN reg value and diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 5e69d3c11d21..fd2007972605 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -726,7 +726,7 @@ static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) static int intel_fbc_max_limit(struct drm_i915_private *i915) { - /* WaFbcOnly1to1Ratio:ctg */ + /* WaFbcOnly1to1Ratio */ if (IS_G4X(i915)) return 1; @@ -811,7 +811,7 @@ static void intel_fbc_program_cfb(struct intel_fbc *fbc) static void intel_fbc_program_workarounds(struct intel_fbc *fbc) { - /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */ + /* Wa_22014263786 */ if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915)) intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); @@ -890,7 +890,7 @@ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) /* 16bpp not supported on gen2 */ if (DISPLAY_VER(i915) == 2) return false; - /* WaFbcOnly1to1Ratio:ctg */ + /* WaFbcOnly1to1Ratio */ if (IS_G4X(i915)) return false; return true; @@ -1148,7 +1148,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } - /* WaFbcExceedCdClockThreshold:hsw,bdw */ + /* WaFbcExceedCdClockThreshold */ if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { const struct intel_cdclk_state *cdclk_state; @@ -1650,7 +1650,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *i915) static bool need_fbc_vtd_wa(struct drm_i915_private *i915) { - /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed */ if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { drm_info(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 063f1da4f229..db6bac23eaaa 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -784,7 +784,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * - TP1 to TP2 time with the default value * - FDI delay to 90h * - * WaFDIAutoLinkSetTimingOverrride:hsw + * WaFDIAutoLinkSetTimingOverrride */ intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index efa2da080f62..8d09b43bfcfd 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2064,7 +2064,7 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) return false; - /* Display Wa_1405510057:icl,ehl */ + /* Display Wa_1405510057 */ if (intel_hdmi_is_ycbcr420(crtc_state) && bpc == 10 && DISPLAY_VER(dev_priv) == 11 && (adjusted_mode->crtc_hblank_end - diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 96395bfbd41d..165ffe241e1e 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -643,7 +643,7 @@ get_encoder_power_domains(struct drm_i915_private *i915) static void intel_early_display_was(struct drm_i915_private *i915) { /* - * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl + * Display WA #1185 WaDisableDARBFClkGating * Also known as Wa_14010480278. */ if (IS_DISPLAY_VER(i915, 10, 12)) @@ -652,7 +652,7 @@ static void intel_early_display_was(struct drm_i915_private *i915) if (IS_HASWELL(i915)) { /* - * WaRsPkgCStateDisplayPMReq:hsw + * WaRsPkgCStateDisplayPMReq * System hang if this isn't done before disabling all planes! */ intel_de_write(i915, CHICKEN_PAR1_1, diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 08a94365b7d1..fefda17bfc60 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -31,7 +31,7 @@ static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv) drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); } -/* WaMPhyProgramming:hsw */ +/* WaMPhyProgramming */ static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv) { u32 tmp; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9820e5fdd087..328c886309f3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -543,7 +543,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); val |= intel_psr2_get_tp_time(intel_dp); - /* Wa_22012278275:adl-p */ + /* Wa_22012278275 */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { static const u8 map[] = { 2, /* 5 lines */ @@ -731,7 +731,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) return; - /* Wa_16011303918:adl-p */ + /* Wa_16011303918 */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) return; @@ -835,7 +835,7 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d if ((hblank_ns - req_ns) > 100) return true; - /* Not supported <13 / Wa_22012279113:adl-p */ + /* Not supported <13 / Wa_22012279113 */ if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) return false; @@ -923,7 +923,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - /* Wa_16011303918:adl-p */ + /* Wa_16011303918 */ if (crtc_state->vrr.enable && IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { drm_dbg_kms(&dev_priv->drm, @@ -1170,7 +1170,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, PSR2_ADD_VERTICAL_LINE_COUNT); /* - * Wa_16014451276:adlp,mtl[a0,b0] + * Wa_16014451276 * All supported adlp panels have 1-based X granularity, this may * cause issues if non-supported panels are used. */ @@ -1181,14 +1181,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, ADLP_1_BASED_X_GRANULARITY); - /* Wa_16011168373:adl-p */ + /* Wa_16011168373 */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), TRANS_SET_CONTEXT_LATENCY_MASK, TRANS_SET_CONTEXT_LATENCY_VALUE(1)); - /* Wa_16012604467:adlp,mtl[a0,b0] */ + /* Wa_16012604467 */ if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, @@ -1197,7 +1197,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, CLKGATE_DIS_MISC_DMASC_GATING_DIS); - /* Wa_16013835468:tgl[b0+], dg1 */ + /* Wa_16013835468 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || IS_DG1(dev_priv)) { u16 vtotal, vblank; @@ -1363,13 +1363,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); if (intel_dp->psr.psr2_enabled) { - /* Wa_16011168373:adl-p */ + /* Wa_16011168373 */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), TRANS_SET_CONTEXT_LATENCY_MASK, 0); - /* Wa_16012604467:adlp,mtl[a0,b0] */ + /* Wa_16012604467 */ if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, MTL_CLKGATE_DIS_TRANS(intel_dp->psr.transcoder), @@ -1378,7 +1378,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); - /* Wa_16013835468:tgl[b0+], dg1 */ + /* Wa_16013835468 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || IS_DG1(dev_priv)) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, @@ -1636,7 +1636,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, if (full_update) { /* - * Not applying Wa_14014971508:adlp,mtl as we do not support the + * Not applying Wa_14014971508 * feature that requires this workaround. */ val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e6b4d24b9cd0..1e8a52b3859d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -788,7 +788,7 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, int scale, i; /* - * WaFP16GammaEnabling:ivb,hsw + * WaFP16GammaEnabling * "Workaround : When using the 64-bit format, the sprite output * on each color channel has one quarter amplitude. It can be * brought up to full amplitude by using sprite internal gamma diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index a69bfcac9a94..5d1a27039aa3 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -34,7 +34,7 @@ void intel_vga_disable(struct drm_i915_private *dev_priv) if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE) return; - /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ + /* WaEnableVGAAccessThroughIOPort */ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); outb(0x01, VGA_SEQ_I); sr1 = inb(VGA_SEQ_D); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 4b79c2d2d617..baad2cd97a92 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -923,7 +923,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, else if (key->flags & I915_SET_COLORKEY_SOURCE) plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; - /* Wa_22012358565:adl-p */ + /* Wa_22012358565 */ if (DISPLAY_VER(dev_priv) == 13) plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); @@ -1401,7 +1401,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, return -EINVAL; } - /* Wa_1606054188:tgl,adl-s */ + /* Wa_1606054188 */ if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && intel_format_is_p01x(fb->format->format)) { @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, if (DISPLAY_VER(i915) < 12) return false; - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ + /* Wa_14010477008 */ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0)) return false; diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index ae4e9e680c2e..14a8c0c89916 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -1411,8 +1411,8 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915, enum plane_id plane_id) { /* - * Wa_1408961008:icl, ehl - * Wa_14012656716:tgl, adl + * Wa_1408961008 + * Wa_14012656716 * Underruns with WM1+ disabled */ return DISPLAY_VER(i915) == 11 || @@ -2011,7 +2011,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *i915, return; /* - * WaDisableTWM:skl,kbl,cfl,bxt + * WaDisableTWM * Transition WM are not recommended by HW team for GEN9 */ if (DISPLAY_VER(i915) == 9) @@ -3453,7 +3453,7 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) : MBUS_DBOX_A_CREDIT(8); else if (IS_ALDERLAKE_P(i915)) - /* Wa_22010947358:adl-p */ + /* Wa_22010947358 */ val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); else diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 490e8ae51228..9a3da69f8b9b 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -371,7 +371,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, reg = _MMIO(regs[engine->id]); - /* WaForceWakeRenderDuringMmioTLBInvalidate:skl + /* WaForceWakeRenderDuringMmioTLBInvalidate * we need to put a forcewake when invalidating RCS TLB caches, * otherwise device can go to RC6 state and interrupt invalidation * process diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 824a34ec0b83..49f7e1fbd96c 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1590,7 +1590,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) free_oa_buffer(stream); /* - * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6. + * Wa_16011777198 */ if (intel_uc_uses_guc_rc(>->uc) && (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || @@ -2801,7 +2801,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, int ret; /* - * Wa_1508761755:xehpsdv, dg2 + * Wa_1508761755 * EU NOA signals behave incorrectly if EU clock gating is enabled. * Disable thread stall DOP gating and EU DOP gating. */ @@ -2891,7 +2891,7 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream) u32 sqcnt1; /* - * Wa_1508761755:xehpsdv, dg2 + * Wa_1508761755 * Enable thread stall DOP gating and EU DOP gating. */ if (IS_XEHPSDV(i915) || IS_DG2(i915)) { @@ -3141,7 +3141,7 @@ get_sseu_config(struct intel_sseu *out_sseu, u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915) { /* - * Wa_18013179988:dg2 + * Wa_18013179988 * Wa_14015846243:mtl */ if (IS_DG2(i915) || IS_METEORLAKE(i915)) { @@ -3293,7 +3293,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL); /* - * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes + * Wa_16011777198 * OA to lose the configuration state. Prevent this by overriding GUCRC * mode. */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 73c88b1c9545..82a59738ca4a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -54,7 +54,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) { if (HAS_LLC(dev_priv)) { /* - * WaCompressedResourceDisplayNewHashMode:skl,kbl + * WaCompressedResourceDisplayNewHashMode * Display WA #0390: skl,kbl * * Must match Sampler, Pixel Back End, and Media. See @@ -63,14 +63,14 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); } - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ + /* See Bspec note for PSR2_CTL bit 31, Wa#828 */ intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); - /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ + /* WaEnableChickenDCPR */ intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); /* - * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl + * WaFbcWakeMemOn * Display WA #0859: skl,bxt,kbl,glk,cfl */ intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); @@ -80,7 +80,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) { gen9_init_clock_gating(dev_priv); - /* WaDisableSDEUnitClockGating:bxt */ + /* WaDisableSDEUnitClockGating */ intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* @@ -105,13 +105,13 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); /* - * WaFbcTurnOffFbcWatermark:bxt + * WaFbcTurnOffFbcWatermark * Display WA #0562: bxt */ intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); /* - * WaFbcHighMemBwCorruptionAvoidance:bxt + * WaFbcHighMemBwCorruptionAvoidance * Display WA #0883: bxt */ intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0); @@ -122,7 +122,7 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) gen9_init_clock_gating(dev_priv); /* - * WaDisablePWMClockGating:glk + * WaDisablePWMClockGating * Backlight PWM may stop in the asserted state, causing backlight * to stay fully on. */ @@ -1111,7 +1111,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, cpp = plane_state->hw.fb->format->cpp[0]; /* - * WaUse32BppForSRWM:ctg,elk + * WaUse32BppForSRWM * * The spec fails to list this restriction for the * HPLL watermark, which seems a little strange. @@ -4113,7 +4113,7 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) /* * Required for FBC - * WaFbcDisableDpfcClockGating:ilk + * WaFbcDisableDpfcClockGating */ dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | @@ -4148,7 +4148,7 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) * The bit 7,8,9 of 0x42020. */ if (IS_IRONLAKE_M(dev_priv)) { - /* WaFbcAsynchFlipDisableFbcQueue:ilk */ + /* WaFbcAsynchFlipDisableFbcQueue */ intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); } @@ -4230,8 +4230,8 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) * According to the spec, bit 11 (RCCUNIT) must also be set, * but we didn't debug actual testcases to find it out. * - * WaDisableRCCUnitClockGating:snb - * WaDisableRCPBUnitClockGating:snb + * WaDisableRCCUnitClockGating + * WaDisableRCPBUnitClockGating */ intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | @@ -4246,7 +4246,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) * The bit14 of 0x70180 * The bit14 of 0x71180 * - * WaFbcAsynchFlipDisableFbcQueue:snb + * WaFbcAsynchFlipDisableFbcQueue */ intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) | @@ -4298,7 +4298,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, u32 misccpctl; u32 val; - /* WaTempDisableDOPClkGating:bdw */ + /* WaTempDisableDOPClkGating */ misccpctl = intel_gt_mcr_multicast_rmw(to_gt(dev_priv), GEN8_MISCCPCTL, GEN8_DOP_CLOCK_GATE_ENABLE, 0); @@ -4319,11 +4319,11 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, static void icl_init_clock_gating(struct drm_i915_private *dev_priv) { - /* Wa_1409120013:icl,ehl */ + /* Wa_1409120013 */ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), DPFC_CHICKEN_COMP_DUMMY_PIXEL); - /*Wa_14010594013:icl, ehl */ + /*Wa_14010594013 */ intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); } @@ -4335,11 +4335,11 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), DPFC_CHICKEN_COMP_DUMMY_PIXEL); - /* Wa_1409825376:tgl (pre-prod)*/ + /* Wa_1409825376 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS); - /* Wa_14013723622:tgl,rkl,dg1,adl-s */ + /* Wa_14013723622 */ if (DISPLAY_VER(dev_priv) == 12) intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); @@ -4349,7 +4349,7 @@ static void adlp_init_clock_gating(struct drm_i915_private *dev_priv) { gen12lp_init_clock_gating(dev_priv); - /* Wa_22011091694:adlp */ + /* Wa_22011091694 */ intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); /* Bspec/49189 Initialize Sequence */ @@ -4360,27 +4360,27 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) { gen12lp_init_clock_gating(dev_priv); - /* Wa_1409836686:dg1[a0] */ + /* Wa_1409836686 */ if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0)) intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, DPT_GATING_DIS); } static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv) { - /* Wa_22010146351:xehpsdv */ + /* Wa_22010146351 */ if (IS_XEHPSDV_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0)) intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); } static void dg2_init_clock_gating(struct drm_i915_private *i915) { - /* Wa_22010954014:dg2 */ + /* Wa_22010954014 */ intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); /* - * Wa_14010733611:dg2_g10 - * Wa_22010146351:dg2_g10 + * Wa_14010733611 + * Wa_22010146351 */ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, @@ -4389,11 +4389,11 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915) static void pvc_init_clock_gating(struct drm_i915_private *dev_priv) { - /* Wa_14012385139:pvc */ + /* Wa_14012385139 */ if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0)) intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); - /* Wa_22010954014:pvc */ + /* Wa_22010954014 */ if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0)) intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); } @@ -4416,13 +4416,13 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); /* - * WaFbcTurnOffFbcWatermark:cfl + * WaFbcTurnOffFbcWatermark * Display WA #0562: cfl */ intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); /* - * WaFbcNukeOnHostModify:cfl + * WaFbcNukeOnHostModify * Display WA #0873: cfl */ intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), @@ -4436,24 +4436,24 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) /* WAC6entrylatency:kbl */ intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); - /* WaDisableSDEUnitClockGating:kbl */ + /* WaDisableSDEUnitClockGating */ if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0)) intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - /* WaDisableGamClockGating:kbl */ + /* WaDisableGamClockGating */ if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0)) intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1, 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE); /* - * WaFbcTurnOffFbcWatermark:kbl + * WaFbcTurnOffFbcWatermark * Display WA #0562: kbl */ intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); /* - * WaFbcNukeOnHostModify:kbl + * WaFbcNukeOnHostModify * Display WA #0873: kbl */ intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), @@ -4464,7 +4464,7 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv) { gen9_init_clock_gating(dev_priv); - /* WaDisableDopClockGating:skl */ + /* WaDisableDopClockGating */ intel_gt_mcr_multicast_rmw(to_gt(dev_priv), GEN8_MISCCPCTL, GEN8_DOP_CLOCK_GATE_ENABLE, 0); @@ -4472,20 +4472,20 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); /* - * WaFbcTurnOffFbcWatermark:skl + * WaFbcTurnOffFbcWatermark * Display WA #0562: skl */ intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); /* - * WaFbcNukeOnHostModify:skl + * WaFbcNukeOnHostModify * Display WA #0873: skl */ intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_NUKE_ON_ANY_MODIFICATION); /* - * WaFbcHighMemBwCorruptionAvoidance:skl + * WaFbcHighMemBwCorruptionAvoidance * Display WA #0883: skl */ intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0); @@ -4495,42 +4495,42 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) { enum pipe pipe; - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ + /* WaFbcAsynchFlipDisableFbcQueue */ intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); - /* WaSwitchSolVfFArbitrationPriority:bdw */ + /* WaSwitchSolVfFArbitrationPriority */ intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); - /* WaPsrDPAMaskVBlankInSRD:bdw */ + /* WaPsrDPAMaskVBlankInSRD */ intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, DPA_MASK_VBLANK_SRD); for_each_pipe(dev_priv, pipe) { - /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ + /* WaPsrDPRSUnmaskVBlankInSRD */ intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), 0, BDW_DPRS_MASK_VBLANK_SRD); } - /* WaVSRefCountFullforceMissDisable:bdw */ - /* WaDSRefCountFullforceMissDisable:bdw */ + /* WaVSRefCountFullforceMissDisable */ + /* WaDSRefCountFullforceMissDisable */ intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE, GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE), _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); - /* WaDisableSDEUnitClockGating:bdw */ + /* WaDisableSDEUnitClockGating */ intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - /* WaProgramL3SqcReg1Default:bdw */ + /* WaProgramL3SqcReg1Default */ gen8_set_l3sqc_credits(dev_priv, 30, 2); - /* WaKVMNotificationOnConfigChange:bdw */ + /* WaKVMNotificationOnConfigChange */ intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR2_1, 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); lpt_init_clock_gating(dev_priv); - /* WaDisableDopClockGating:bdw + /* WaDisableDopClockGating * * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP * clock gating. @@ -4540,14 +4540,14 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) { - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ + /* WaFbcAsynchFlipDisableFbcQueue */ intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); - /* This is required by WaCatErrorRejectionIssue:hsw */ + /* This is required by WaCatErrorRejectionIssue */ intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - /* WaSwitchSolVfFArbitrationPriority:hsw */ + /* WaSwitchSolVfFArbitrationPriority */ intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); lpt_init_clock_gating(dev_priv); @@ -4557,10 +4557,10 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) { intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); - /* WaFbcAsynchFlipDisableFbcQueue:ivb */ + /* WaFbcAsynchFlipDisableFbcQueue */ intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); - /* WaDisableBackToBackFlipFix:ivb */ + /* WaDisableBackToBackFlipFix */ intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3, CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); @@ -4578,12 +4578,12 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) /* * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating:ivb workaround. + * This implements the WaDisableRCZUnitClockGating */ intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - /* This is required by WaCatErrorRejectionIssue:ivb */ + /* This is required by WaCatErrorRejectionIssue */ intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); @@ -4600,33 +4600,33 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) { - /* WaDisableBackToBackFlipFix:vlv */ + /* WaDisableBackToBackFlipFix */ intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3, CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); - /* WaDisableDopClockGating:vlv */ + /* WaDisableDopClockGating */ intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - /* This is required by WaCatErrorRejectionIssue:vlv */ + /* This is required by WaCatErrorRejectionIssue */ intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); /* * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating:vlv workaround. + * This implements the WaDisableRCZUnitClockGating */ intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - /* WaDisableL3Bank2xClockGate:vlv + /* WaDisableL3Bank2xClockGate * Disabling L3 clock gating- MMIO 940c[25] = 1 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ intel_uncore_rmw(&dev_priv->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); /* - * WaDisableVLVClockGating_VBIIssue:vlv + * WaDisableVLVClockGating_VBIIssue * Disable clock gating on th GCFG unit to prevent a delay * in the reporting of vblank events. */ @@ -4635,23 +4635,23 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) static void chv_init_clock_gating(struct drm_i915_private *dev_priv) { - /* WaVSRefCountFullforceMissDisable:chv */ - /* WaDSRefCountFullforceMissDisable:chv */ + /* WaVSRefCountFullforceMissDisable */ + /* WaDSRefCountFullforceMissDisable */ intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE, GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); - /* WaDisableSemaphoreAndSyncFlipWait:chv */ + /* WaDisableSemaphoreAndSyncFlipWait */ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE), _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); - /* WaDisableCSUnitClockGating:chv */ + /* WaDisableCSUnitClockGating */ intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); - /* WaDisableSDEUnitClockGating:chv */ + /* WaDisableSDEUnitClockGating */ intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* - * WaProgramL3SqcReg1Default:chv + * WaProgramL3SqcReg1Default * See gfxspecs/Related Documents/Performance Guide/ * LSQC Setting Recommendations. */ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8dee9e62a73e..e56dbb20f2fe 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -210,7 +210,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, * the fallback ack. * * This workaround is described in HSDES #1604254524 and it's known as: - * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl + * WaRsForcewakeAddDelayForAck * although the name is a bit misleading. */ @@ -376,7 +376,7 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, { fw_domains_get_normal(uncore, fw_domains); - /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ + /* WaRsForcewakeWaitTC0 */ __gen6_gt_wait_for_thread_c0(uncore); } @@ -584,7 +584,7 @@ static void forcewake_early_sanitize(struct intel_uncore *uncore, { GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); - /* WaDisableShadowRegForCpd:chv */ + /* WaDisableShadowRegForCpd */ if (IS_CHERRYVIEW(uncore->i915)) { __raw_uncore_write32(uncore, GTFIFOCTL, __raw_uncore_read32(uncore, GTFIFOCTL) | @@ -1887,7 +1887,7 @@ static const struct intel_forcewake_range __xelpmp_fw_ranges[] = { static void ilk_dummy_write(struct intel_uncore *uncore) { - /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up + /* WaIssueDummyWriteToWakeupFromRC6 * the chip from rc6 before touching it for real. MI_MODE is masked, * hence harmless to write 0 into. */ __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); From patchwork Thu Dec 22 08:25:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13079508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8DBDC4332F for ; Thu, 22 Dec 2022 08:26:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D3D7D10E514; Thu, 22 Dec 2022 08:26:25 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E47CE10E514; Thu, 22 Dec 2022 08:26:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671697583; x=1703233583; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G26Xi+3Mu0RsqVsMq6+Wo/lBvmZFtlv/v/jQGWH5Td4=; b=K/cEpwdwUmkwVPI9dUNuTztrBZFPoUd0X0En7Bhp4w6lqFMhkXW7+UED bAnf7rASr/aKGcJS0n9653lp46Gq21+7wyjqAhja0TcwBS8gvlv+kLyyI 1qDWdfZZErUSJE9VmwKwRHuCxvasnFbg5qpNHuwRAHwbNI5zIrzanBt5B 1VmjtOzL5qPxJ4lwLONp/NyKd1TniIKzeN50WjKXQovFf5iwRQwdbCb/+ WRNs01AgCkfZ99XWhyE/urAZYOIm67KZ4Ropg8gZi7gM9Y5fdyUAa/MMJ NZMJwz+qFD/OjJ7UEVf5aYjoES5nFKPVjxq2WL8me9d10Zt7Mob7baZIx Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="384426683" X-IronPort-AV: E=Sophos;i="5.96,265,1665471600"; d="scan'208";a="384426683" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 00:26:23 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="645127601" X-IronPort-AV: E=Sophos;i="5.96,265,1665471600"; d="scan'208";a="645127601" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 00:26:23 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 22 Dec 2022 00:25:57 -0800 Message-Id: <20221222082557.1364711-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222082557.1364711-1-lucas.demarchi@intel.com> References: <20221222082557.1364711-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] fixup! drm/i915: Remove platform comments from workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 328c886309f3..543881838def 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1636,7 +1636,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, if (full_update) { /* - * Not applying Wa_14014971508 + * Not applying Wa_14014971508 as we do not support the * feature that requires this workaround. */ val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 49f7e1fbd96c..9e6686b8c8f0 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1590,7 +1590,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) free_oa_buffer(stream); /* - * Wa_16011777198 + * Wa_16011777198 - Unset the override of GUCRC mode to enable rc6. */ if (intel_uc_uses_guc_rc(>->uc) && (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || @@ -3293,7 +3293,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL); /* - * Wa_16011777198 + * Wa_16011777198 - GuC resets render as part of the Wa. This causes * OA to lose the configuration state. Prevent this by overriding GUCRC * mode. */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 82a59738ca4a..492973085297 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4578,7 +4578,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) /* * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating + * This implements the WaDisableRCZUnitClockGating workaround. */ intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); @@ -4615,7 +4615,7 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) /* * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating + * This implements the WaDisableRCZUnitClockGating workaround. */ intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e56dbb20f2fe..182791a9cabb 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1887,7 +1887,7 @@ static const struct intel_forcewake_range __xelpmp_fw_ranges[] = { static void ilk_dummy_write(struct intel_uncore *uncore) { - /* WaIssueDummyWriteToWakeupFromRC6 + /* WaIssueDummyWriteToWakeupFromRC6 - Issue a dummy write to wake up * the chip from rc6 before touching it for real. MI_MODE is masked, * hence harmless to write 0 into. */ __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);