From patchwork Tue Dec 27 13:21:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13082318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 989C3C10F1B for ; Tue, 27 Dec 2022 13:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229765AbiL0NWZ (ORCPT ); Tue, 27 Dec 2022 08:22:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229542AbiL0NWY (ORCPT ); Tue, 27 Dec 2022 08:22:24 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E94AB1D5; Tue, 27 Dec 2022 05:22:22 -0800 (PST) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BRCQWqW029614; Tue, 27 Dec 2022 13:22:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=FEkD/7L2yqfIqCP6f0tA+4AwwCo2FoWeZcYtHNDZaHk=; b=Uh2byEhV323wMlr5kuSG9wXhEC98n18qCTGrTOmiPGjrYeYhQ2AMz6Qaw6+0EQECNPC9 ih1u8ijWOSXStEqSog5SMh+VN+/CzKM3PH/DbOmkvxCIgjzPGxuslUHao7BE/NSDPCcc OQecDpS6XRmrERItASppVIozhnxB4HuKoW6dz+EVDYmrYz+pFxWj2SRKNGnir4SeVJ9s FiHInf/f65SqNEYVn0gimc0MCQhaimwVCbWFPjqvjZ6RFeNINquj+4BNWGySGVB2O88W ZkHNddDefhAx/sBayOZxamIZFhrEyQIOdZIaA+s8/BQxHbvuu10sTj1vfS5PXAiVtU9T xw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mnpsvnatv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Dec 2022 13:22:18 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BRDMH7Y031915 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Dec 2022 13:22:17 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 27 Dec 2022 05:22:14 -0800 From: Kathiravan T To: , , , , , , , CC: Varadarajan Narayanan , Sricharan R , Kathiravan T Subject: [PATCH] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs Date: Tue, 27 Dec 2022 18:51:55 +0530 Message-ID: <20221227132155.1386-1-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8QF3W2glX1RTMzU0_3CRGKOtr_lcO3yj X-Proofpoint-ORIG-GUID: 8QF3W2glX1RTMzU0_3CRGKOtr_lcO3yj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-27_09,2022-12-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1011 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212270110 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Varadarajan Narayanan Add programming sequence support for managing the Stromer PLLs. Co-developed-by: Sricharan R Signed-off-by: Sricharan R Signed-off-by: Varadarajan Narayanan Signed-off-by: Kathiravan T --- Changes since V2: - splitted this patch from IPQ5018 series[1] - Rebased on linux-6.2-rc1 [1] https://lore.kernel.org/linux-arm-msm/20220621161126.15883-1-quic_srichara@quicinc.com/ drivers/clk/qcom/clk-alpha-pll.c | 100 ++++++++++++++++++++++++++++++- drivers/clk/qcom/clk-alpha-pll.h | 7 ++- 2 files changed, 105 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f9e4cfd7261c..29866100df08 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -204,9 +204,24 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_CONFIG_CTL] = 0x1C, [PLL_OFF_STATUS] = 0x20, }, + [CLK_ALPHA_PLL_TYPE_STROMER] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0x14, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0x1c, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0xff, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); +static unsigned long +alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, + u32 alpha_width); /* * Even though 40 bits are present, use only 32 for ease of calculation. */ @@ -215,6 +230,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define ALPHA_BITWIDTH 32U #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) +#define ALPHA_PLL_STATUS_REG_SHIFT 8 + #define PLL_HUAYRA_M_WIDTH 8 #define PLL_HUAYRA_M_SHIFT 8 #define PLL_HUAYRA_M_MASK 0xff @@ -325,7 +342,7 @@ static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { - u32 val, mask; + u32 val, val_u, mask, mask_u; regmap_write(regmap, PLL_L_VAL(pll), config->l); regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); @@ -355,14 +372,85 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, mask |= config->pre_div_mask; mask |= config->post_div_mask; mask |= config->vco_mask; + mask |= config->alpha_en_mask; + mask |= config->alpha_mode_mask; regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ + val_u = config->status_reg_val << ALPHA_PLL_STATUS_REG_SHIFT; + val_u |= config->lock_det; + + mask_u = config->status_reg_mask; + mask_u |= config->lock_det; + + if (val_u) + regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); + + if (config->test_ctl_val) + regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + + if (config->test_ctl_hi_val) + regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + if (pll->flags & SUPPORTS_FSM_MODE) qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); } EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); +static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + u32 l; + u64 a; + + req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, + &l, &a, ALPHA_REG_BITWIDTH); + + return 0; +} + +static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l; + int ret; + u64 a; + + rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); + + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), + a >> ALPHA_BITWIDTH); + + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN, PLL_ALPHA_EN); + + if (!clk_hw_is_enabled(hw)) + return 0; + + /* + * Stromer PLL supports Dynamic programming. + * It allows the PLL frequency to be changed on-the-fly without first + * execution of a shutdown procedure followed by a bring up procedure. + */ + + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, + PLL_UPDATE); + + ret = wait_for_pll_update(pll); + if (ret) + return ret; + + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + return 0; +} + static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) { int ret; @@ -1013,6 +1101,16 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); +const struct clk_ops clk_alpha_pll_stromer_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = clk_alpha_pll_recalc_rate, + .determine_rate = clk_alpha_pll_stromer_determine_rate, + .set_rate = clk_alpha_pll_stromer_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); + const struct clk_ops clk_alpha_pll_fixed_trion_ops = { .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 2bdae362c827..1d122919e275 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. */ #ifndef __QCOM_CLK_ALPHA_PLL_H__ #define __QCOM_CLK_ALPHA_PLL_H__ @@ -22,6 +22,7 @@ enum { CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, + CLK_ALPHA_PLL_TYPE_STROMER, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -131,6 +132,9 @@ struct alpha_pll_config { u32 post_div_mask; u32 vco_val; u32 vco_mask; + u32 status_reg_val; + u32 status_reg_mask; + u32 lock_det; }; extern const struct clk_ops clk_alpha_pll_ops; @@ -139,6 +143,7 @@ extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; extern const struct clk_ops clk_alpha_pll_huayra_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; +extern const struct clk_ops clk_alpha_pll_stromer_ops; extern const struct clk_ops clk_alpha_pll_fabia_ops; extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;