From patchwork Wed Dec 28 08:40:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DA21C4332F for ; Wed, 28 Dec 2022 08:41:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232483AbiL1IlR (ORCPT ); Wed, 28 Dec 2022 03:41:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230127AbiL1Ik7 (ORCPT ); Wed, 28 Dec 2022 03:40:59 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45E82DFE for ; Wed, 28 Dec 2022 00:40:50 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id 79so10169447pgf.11 for ; Wed, 28 Dec 2022 00:40:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=neDlpAxOqPxKQsX09z7HIhUpqVcLiuVepxClOJ3AnCk=; b=TO9dKYGst245T1FMDa9SJ7Cxs4BbwS8yCPhWehj2oL1iNJWyO2XcJefzEiXWM6sR+z 1Fa3k6LqqS9mh5h5Iisk7cYKSGWAQsUAlL6CtNJou0B5lAhT9FP30D2aMfRfXixnha18 u3gSjZtQtaZWdpEzyasM0yOETDO8dugLpvvf9fLCZKeLO/kZnCTg8qvsuI1f/Ym7QKRj HV5VrmX/gP8FkhRCkIsLu3QZTwJoVBOpTzA5nBDPrt8tT2THbC2MVh15GpVEICGLEtWN enEq6qEW39ZV1z0Y3QUdwp02JupQ22ZktOsyg+AfteXCuQP0QaNBDjHeDBz0w5ZD9cT0 EIvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=neDlpAxOqPxKQsX09z7HIhUpqVcLiuVepxClOJ3AnCk=; b=7Xrqozk7Ko7sKZrTXAVffEjLPjHs4yzY5xVFddSikXXSQqtU8BYbsp+myOOhdGSmde bZogwWNQTFSBCjiVhZZ5QVv0Z7CKiGbt+LCNesgqcLsmPgNM3oeTF0CxUy+1b+10zy2e fn7mlaPTj4X5bYPhDpXT6WdtBeWruuvaGFBhWpND+8T8/xFalNIp6Zplq43FFDetApdK G27NMoqgbUepdCkD+SuyXbGCMza4WQT0tJQ5ciOjHpbx2mAldJc0DOKoKefYkqofzjhp XIDdKpSqGCRQB3wsx7T/UOgB05kLemoec/ttScaDmUjYgZHO6EiJZ1yjHL8R4J/bRSX0 Veuw== X-Gm-Message-State: AFqh2kpbPpz93eYKiZzjySCV9nD8cytl8zP5cWSA9cn8rAc3N9ukBLQJ MaecZkkSZ8JSCY9HD8WlRzE+ X-Google-Smtp-Source: AMrXdXuvED813YpAwBQ4YACRPHJyw43PMQJzcUevAevLVbG0LtLKRvEHNJeKmpG42psm7SVaqnFw1g== X-Received: by 2002:a05:6a00:1da2:b0:57d:8b30:db0a with SMTP id z34-20020a056a001da200b0057d8b30db0amr27459818pfw.9.1672216850324; Wed, 28 Dec 2022 00:40:50 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:40:49 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v5 01/17] EDAC/device: Make use of poll_msec value in edac_device_ctl_info struct Date: Wed, 28 Dec 2022 14:10:12 +0530 Message-Id: <20221228084028.46528-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The EDAC drivers may optionally pass the poll_msec value. Use that value if available, else fall back to 1000ms. Cc: # 4.9 Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam Signed-off-by: Borislav Petkov (AMD) Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride --- drivers/edac/edac_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c index 19522c568aa5..19c3ab2a434e 100644 --- a/drivers/edac/edac_device.c +++ b/drivers/edac/edac_device.c @@ -447,7 +447,7 @@ int edac_device_add_device(struct edac_device_ctl_info *edac_dev) * enable workq processing on this instance, * default = 1000 msec */ - edac_device_workq_setup(edac_dev, 1000); + edac_device_workq_setup(edac_dev, edac_dev->poll_msec ? edac_dev->poll_msec : 1000); } else { edac_dev->op_state = OP_RUNNING_INTERRUPT; } From patchwork Wed Dec 28 08:40:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF584C54E76 for ; Wed, 28 Dec 2022 08:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232659AbiL1IlW (ORCPT ); Wed, 28 Dec 2022 03:41:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232542AbiL1IlB (ORCPT ); Wed, 28 Dec 2022 03:41:01 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E095FCD6 for ; Wed, 28 Dec 2022 00:40:58 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id h7-20020a17090aa88700b00225f3e4c992so6833622pjq.1 for ; Wed, 28 Dec 2022 00:40:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vCj+eIEQcGnCqPz5ZSYr2aqyU+fsKL7bkSmfajhhbqw=; b=nh2vLpwyk3i88WoIGebvO24ZIfmBo4MbWEQ6zxuAbkNK1NrDjWdFI86Gl3KuTu8FhX Xjn+T0h/F2Lfn0tplbrQ8HWX7xQNWNVdLvpwiWiaXj35ObByDxpDboqqrsFziQ48gT3J 3U6eDfFSVG+YnqoW9rsNzkHJC+y4Qh2RAqzahA0tyxzuwsfLYL4Zp4O9ClzJ/11yeHyi QT2rao1/GsGNKxrhUlOZ5VBOwR3ZWL5o45/HllyRKOxd9UIwJMjC8opDVo1A9IX/7ZZI q+CIbj5C6ZgC+mYFKIS8t/3vHMGItPKkjknzYzAQhY7oD7LKpoBXCODrqDQshw64AoR1 QU3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vCj+eIEQcGnCqPz5ZSYr2aqyU+fsKL7bkSmfajhhbqw=; b=px1akHQIwZPI/k8U4ximo2UpeenIb27DCHiOMBfzd7gTO5fOgeJAJjH7uYD6t0UmUh swmYtHCzFLeG+JZK8XoY0ivZo1XhbuUiZ6z3cAeQAZE9YN3z4y3RpwnM46/fVZvE8jSb WHB5XV+F4qYToHNsMSNqO2tVqAdKTu8v+CFDPyQa7pfKVWFVMD+zVfN9cX39V5MaKSE+ mE2RlEVmZv2HfmGKGNyEjxBRO90wvQmJA2do9c+QD2sClNn2VJtcNzsss4BVRHAw6SaJ IW/37WoZgkxevt0zXHghOIlBLeS8baQFxBlJTtuY9FrFmWcW62naHWa+ZUeWipCvv0X1 U71w== X-Gm-Message-State: AFqh2kpY+tKWAeZ6ewWQ6LUc8oh5W1KLIK3qomXRye50PPZY3bu7ZbTC metRwJCGFvoiJmAqfJ5dMyIm X-Google-Smtp-Source: AMrXdXsnwu5WJi7+TnEJGtUOAUs6sawZwL2+5ZpDVe0Me44zOkwKOHWhKRKZnSS4aAi1PXOTzEhT4Q== X-Received: by 2002:a05:6a20:1455:b0:ae:661c:5553 with SMTP id a21-20020a056a20145500b000ae661c5553mr36999595pzi.4.1672216858060; Wed, 28 Dec 2022 00:40:58 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:40:57 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 02/17] EDAC/qcom: Add platform_device_id table for module autoloading Date: Wed, 28 Dec 2022 14:10:13 +0530 Message-Id: <20221228084028.46528-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org platform_device_id table needs to be added so that the driver can be autoloaded when the associated platform device gets registered. Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reported-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..9e77fa84e84f 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -397,12 +397,19 @@ static int qcom_llcc_edac_remove(struct platform_device *pdev) return 0; } +static const struct platform_device_id qcom_llcc_edac_id_table[] = { + { .name = "qcom_llcc_edac" }, + {} +}; +MODULE_DEVICE_TABLE(platform, qcom_llcc_edac_id_table); + static struct platform_driver qcom_llcc_edac_driver = { .probe = qcom_llcc_edac_probe, .remove = qcom_llcc_edac_remove, .driver = { .name = "qcom_llcc_edac", }, + .id_table = qcom_llcc_edac_id_table, }; module_platform_driver(qcom_llcc_edac_driver); From patchwork Wed Dec 28 08:40:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16932C46467 for ; Wed, 28 Dec 2022 08:41:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232494AbiL1Ils (ORCPT ); Wed, 28 Dec 2022 03:41:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232699AbiL1IlP (ORCPT ); Wed, 28 Dec 2022 03:41:15 -0500 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74E253A9 for ; Wed, 28 Dec 2022 00:41:06 -0800 (PST) Received: by mail-pf1-x42d.google.com with SMTP id k137so5519629pfd.8 for ; Wed, 28 Dec 2022 00:41:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q1NrdFunM3umkB8l0ZcJbFNj2UhbwdZo1HlNf5THZjI=; b=YWqrz5eGRIMsG0Ei1l5tGH6itYViuDMDjNgd0hF1Elmf6sDEYzP7h6Q0Dsz2GRvwfo 0uzKrsugC7Xg1enMvNSndm9h+svhJzCffttyCNPtG5P5obkMDMECSHXndyOQa+LF5jai I8caCiTs2IiLBTvWZdQomkKHw3UzLjkejpZdzOmm0DptQATdWVD4bIxbV2d8c60nOLYI cvfX1nSj0FtintmSBgA/JSPsPzpcOjGdtIUFX1Q3XQq88DPwcOBgIpvdbyQhCJ3FFZuR AjKKK8ffmlo6xuC8QcDy23H0S1BqiIFyJmLK4Wa5EY7fEL5gwNB0OL/IcX9Dp+nlOYQf u0bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q1NrdFunM3umkB8l0ZcJbFNj2UhbwdZo1HlNf5THZjI=; b=OcLK02nlEusgF7Bf4+d9LhMLTisZOCzhmNWO7ppaGjm+wYrGth1Q/U9RcsiQ1PLVus MnWBHkTIiRYYgRyaxIuQYeOM2gMU2ofaFTGYil77rNzdR34yqkokYx5y7jMXYtbKDpJq lbyfF73ERCqaWA+m1SfTQDgpE6FIrwgIrcU662+rKaxDTSjG17rZC0VQeEpG8/bfKnU8 wVoAV+aDGqvK0Tho2K6AwFeoa8mdNmcLVESGlC/gzHnvMghRdBiJowKGYdMIVaGn/dqB YR/49yiL6JvjxtIIcUDM3zDLZbz+nyH/BeWrw3cMdk+P5WkSihZYq8vOUu3/uma14DyB YCrQ== X-Gm-Message-State: AFqh2krsgMgSPWlAya+ZTZBRZdIR/kRBU8sY3V42ctc6015ZSIUliIE/ moJvJ9ARpWvDHM2l7BKOw9gf X-Google-Smtp-Source: AMrXdXuTBu6noNpF7JLy+QzCkqm8KyQsaNzc/BRre60Z7rZiBxPRbvjGR6qk/JZ42RzJtzgkNDpG0Q== X-Received: by 2002:aa7:83d1:0:b0:580:d71e:a2e5 with SMTP id j17-20020aa783d1000000b00580d71ea2e5mr13909138pfn.22.1672216865946; Wed, 28 Dec 2022 00:41:05 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:05 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v5 03/17] EDAC/qcom: Do not pass llcc_driv_data as edac_device_ctl_info's pvt_info Date: Wed, 28 Dec 2022 14:10:14 +0530 Message-Id: <20221228084028.46528-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The memory for "llcc_driv_data" is allocated by the LLCC driver. But when it is passed as "pvt_info" to the EDAC core, it will get freed during the qcom_edac driver release. So when the qcom_edac driver gets probed again, it will try to use the freed data leading to the use-after-free bug. Fix this by not passing "llcc_driv_data" as pvt_info but rather reference it using the "platform_data" in the qcom_edac driver. Cc: # 4.20 Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam Reviewed-by: Borislav Petkov (AMD) --- drivers/edac/qcom_edac.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 9e77fa84e84f..3256254c3722 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -252,7 +252,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) { - struct llcc_drv_data *drv = edev_ctl->pvt_info; + struct llcc_drv_data *drv = edev_ctl->dev->platform_data; int ret; ret = dump_syn_reg_values(drv, bank, err_type); @@ -289,7 +289,7 @@ static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; - struct llcc_drv_data *drv = edac_dev_ctl->pvt_info; + struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; irqreturn_t irq_rc = IRQ_NONE; u32 drp_error, trp_error, i; int ret; @@ -358,7 +358,6 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->dev_name = dev_name(dev); edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; - edev_ctl->pvt_info = llcc_driv_data; rc = edac_device_add_device(edev_ctl); if (rc) From patchwork Wed Dec 28 08:40:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44C99C4332F for ; Wed, 28 Dec 2022 08:41:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232733AbiL1Il6 (ORCPT ); Wed, 28 Dec 2022 03:41:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232661AbiL1IlT (ORCPT ); Wed, 28 Dec 2022 03:41:19 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA44AFD01 for ; Wed, 28 Dec 2022 00:41:13 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id 82so10219386pgc.0 for ; Wed, 28 Dec 2022 00:41:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=USFa3vv6r3M6at72+GYbrAEuQqTIcmw3cLL2W4/Vhuk=; b=kpqldBi40qr6VGpY4wIciIgIpry8ox+hTxyKAge6AX9QRyA7AAeM4uKrICN21Ek/NB EpxfHZd78zqiNNERABmX4jaGzGGQ3MF5KetlMnqlzpTbjNLQfRY2pLM0ogMMpk7wVcPZ LNxJqGsWgDQ1Y5HGeHze/TDe3rHfLFzktxduIOkD2lRHt/ZDbac6fnNLgrVlFiUaAym0 rkxiezXfc4OFwPt2q3iCSm95FVv9djSK0FbhNuW4AcFmIAV622ibpB+M1XIDCT6zprKK mMv09WZP2jedMbEOgDzL/xdVBeSbC+NGXqpoGWvhDXqkawAd2bN63Kr9Om77SCFRiXVQ NZOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=USFa3vv6r3M6at72+GYbrAEuQqTIcmw3cLL2W4/Vhuk=; b=ref2dGC4wIkuW7SLWwniQAVwbFYE9Zum9w+IYtug4gDDzzanBi2zXdJt+7NYF/uprR HQc1b9RaC2PEVxGHBhk4Oudi7T7HY23Sm64TItKODKOHvC2ajwe67XvFfljmPL9d4wim w5CjUKQp3L6JOrs2MhwLbu4Lb64kuRvipBlYkADXTdYPe+eL8xN9apV/0LmSZrT5w/0H E609i9Ke/g4Vxlmcl8OSuTjCb85EDWqij0dt8Y16J0OnHiKZHZ/N5nGkoGsIIq01I0bT sqrxb0CQQNZkrTc5EdWYjwxYJWOISh3Phesl059Mr33RD6g4tJofq0AdWDCwSZKJCrGw IPVA== X-Gm-Message-State: AFqh2kpbGTLEJTx4cyTq8qiIpi0BcJEw+QudFLv2x1Ft0SUOtpiOVCZ2 UdLmY3e+EeY5H05rGzQgjz/1 X-Google-Smtp-Source: AMrXdXttzAeX7SG+Jw9+MV91sz3bAxNDR5fgdUGZ8cafi5MRu6SswAWEpMziT8o2hrU+n9jRVEWSrw== X-Received: by 2002:a05:6a00:1885:b0:580:9a80:6e37 with SMTP id x5-20020a056a00188500b005809a806e37mr25225588pfh.25.1672216873572; Wed, 28 Dec 2022 00:41:13 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:12 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v5 04/17] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Wed, 28 Dec 2022 14:10:15 +0530 Message-Id: <20221228084028.46528-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Acked-by: Sai Prakash Ranjan Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From patchwork Wed Dec 28 08:40:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B906C46467 for ; Wed, 28 Dec 2022 08:42:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232250AbiL1ImE (ORCPT ); Wed, 28 Dec 2022 03:42:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbiL1IlY (ORCPT ); Wed, 28 Dec 2022 03:41:24 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B74AC1C6 for ; Wed, 28 Dec 2022 00:41:21 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id t2so15493830ply.2 for ; Wed, 28 Dec 2022 00:41:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jXuVNaTN8VlggSdcrqnxpaEGm5VyBVkNPNZuLm2UVUQ=; b=G2otba28c8R9SkCLtxMwFYiN17O6EhdwZZxOqqiLCgFK/iOcfxhT7dEtEG9pXQO1mZ +INv8/ecW+zjyG0CUUavohpIojcfRUD8no8fTf3UojOlYo+ILSyqPiG+vDw6GaZVolOY RhNNZYn95Tur2Mx83W6NnBzKdAEO3qPPIEazCITa8i2WnSdHyWABxItXAomVKWvcTmu6 FFty+9O3YOZsGp1kVN3Rp8bn4E6Cb+spcpR0+HJsaqKJ0VnkH6PrZmy4fBNTUw0sF6KD 0eNloPAO5c70k5QgF/WEowpussh1oy9lrWw/typFUjGXMdcj1XYA54R3dBKL00AQfgBg DTcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jXuVNaTN8VlggSdcrqnxpaEGm5VyBVkNPNZuLm2UVUQ=; b=ln3LICOnHL1H5mYxZaDVz1b7ydKCAhl3W8e3ZqsEbMW0FsX+IXoy/QiRi3BLF/98fX vTPLEat7n6T7HNmlGXkA9ApPR/j8hwwaovIv0XCQjDVyzdLvqPV5wOkzAqa241AGnzMU hW/Y8E5Rzr81PEue4xGWP1SrOsBF+8YSS7B2YaJ41u1zNoBXbHbh5qbOPd4p+PXYbXbI wH6oS11WqTqUS7ibgFX6+ANjukdX4j/3pchELHYKuXWCnHRQq1xaw+AgEqQuNVX95C6Z VXr1eDmmgWTRusNFzRhQK2Kr6SRjJ+zpqj3maCZ9hm+53eJzdtcETdAL7y9GaNy6nHkM Lt+w== X-Gm-Message-State: AFqh2kpIDpI4Ppz5AsTtG3fnFmEPvuNZGxuZIpoKPMejfcmbk0SRq/Q+ dDvL4umCllLKwClaKhnBB+pU X-Google-Smtp-Source: AMrXdXuSHe7D+cPtwNu+B2yM6U8GwVa1sZKdXJph2lYLq0tia0YBkYXpU5FhDXt7j9pTGiH5k12LBw== X-Received: by 2002:a05:6a20:1455:b0:ad:e06f:9540 with SMTP id a21-20020a056a20145500b000ade06f9540mr37719651pzi.4.1672216881185; Wed, 28 Dec 2022 00:41:21 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:20 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v5 05/17] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Wed, 28 Dec 2022 14:10:16 +0530 Message-Id: <20221228084028.46528-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..050e21d4a03e 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From patchwork Wed Dec 28 08:40:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6FC4C46467 for ; Wed, 28 Dec 2022 08:42:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232499AbiL1ImU (ORCPT ); Wed, 28 Dec 2022 03:42:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229912AbiL1Ilp (ORCPT ); Wed, 28 Dec 2022 03:41:45 -0500 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2ADDFD14 for ; Wed, 28 Dec 2022 00:41:28 -0800 (PST) Received: by mail-pf1-x42f.google.com with SMTP id z7so4626466pfq.13 for ; Wed, 28 Dec 2022 00:41:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e9QXXi64w5AkU0+SlZ8zyP2UpGIuUHr0Btt1KBRAP8A=; b=IvF0oXD98yyBIqJq+91laACS5kfVQK2q412wkuezxYCvLA0lRlwFwYxUfpurelPzpr xcHz5E9MOKe5LT4ggXttZ6W+FX0gMgXwGfz4TDWCHwDy7BGGlhn67taNPTvntvbk38t1 I8k2KnjjDamTOPL8uNTa2Jbxkrqv0Gti3JuhM+YvJTjm/U4kCZgfzZiz0eUSytiPx4uo PE0jeUZg0G25Dg8dQRgGQX7fT0+v69nM7x35iibVLlfaxLQtedX8JDseRMh7kN4Si/WZ Em3B54menA+Q92ONQkA9iJiloH/RbU5kjuj1ewOxyP5Lr+xFGibrFacCQUc5MYjn8iI8 eTKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e9QXXi64w5AkU0+SlZ8zyP2UpGIuUHr0Btt1KBRAP8A=; b=UZmjjairUmdDpjesSZs8xJA1FGmKgkb85hrm3swBlbU79HKW5zwmjMcHZ5YlJ0XWmL G8bhFCsGzuqDQB4nN6GzK00pAKyJyM/S5dzfoDMvSUOOklj3MKhfj0S8yKdtyAIyRleP 5kkzgRGAc6wiyUmPaWDwGY2C0xFEk1qXi39he4RdDMF85kgcfZVk2tF3ZbVSW/ApZSCh h/ArbJrL0eLfteRLS5LYyLwsubTVzy8GdLVRJT7nK1vqxCWRRDW7aTHooIrg51fTBfNU YeBW2LWYYivtojhpjEaPKRDTiBKJM51zFp/6o31PUylQ5ukmjv2npnvvP2QtlQ7m1M7H /n2g== X-Gm-Message-State: AFqh2kpx7RpQMnbJQbNywCeanhUweFBbgayw4+EUd8aQnhcJUwCTK6SK 5wHIp6UK4rTW2wxefwV6ciwr X-Google-Smtp-Source: AMrXdXtlsfFLE8Oyyf/2hwR+62V2eL//nmMUWLdt1iOWVVGNeRPnx2Wie08yHGNPwOCkqf08JFraOg== X-Received: by 2002:a62:f20f:0:b0:56b:b890:6ccd with SMTP id m15-20020a62f20f000000b0056bb8906ccdmr24974575pfh.4.1672216888505; Wed, 28 Dec 2022 00:41:28 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:27 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 06/17] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:17 +0530 Message-Id: <20221228084028.46528-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..4db68d4d78df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,11 @@ uart15: serial@a9c000 { llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 28 08:40:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09443C46467 for ; Wed, 28 Dec 2022 08:42:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232743AbiL1Imj (ORCPT ); Wed, 28 Dec 2022 03:42:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232735AbiL1Il7 (ORCPT ); Wed, 28 Dec 2022 03:41:59 -0500 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13D210053 for ; Wed, 28 Dec 2022 00:41:36 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id v3so10187889pgh.4 for ; Wed, 28 Dec 2022 00:41:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=kW/WrjOWRlX5MKh1BPZ4cXc5hc/bKSSEGcp2PXOUo2es5F10/wYS4gPlhOP6Ag+TWH eZFdWMexS1F5KQc4XKr8auMDT2nf/td0WUOrpKUJW8UK7LGkLoGyVW53MLV/rGQTwyzd 0PGEV2e/SDy4luCRc24OkAkwv4o5kKLi5pwOvMqZpfqlriOlicJrFCZQUsazH2cjc8Qn DPYjUlY/9hnhqjWpjyPT4R3ZpwtjDchZKTauIFAH0bro94vUSUVTGf8/vJ0bIxostFx7 nIxYTpry7XX2mhOomqnXBfoFeXuuthoGzHr9+s8GMZLhI43iUWDfYAzotk12Kq1g3vbx oCqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=ZloelHWCHqrF9zCDntnaSdFBrWxdtIaTwGF/3SnS07w30DBsj8pnj2tX+xqIJMwVGW AXxyfriNvoEJR4Ec1rhDpD8Ifq/Fis2fCbwA/gdlglEvPswJwxii2dl8Qitv5C3EvIb8 ZwhONTp8CT8g3ecZumUMyn7QjYUZcggIjbtK1orRyHHzI8vLOtos8rk84iXM3MqYXPKQ 5wK3bTbJ0AhIBW4D4Mv/wQgD0vJ+tLT8lBUoaQltuqTt6SSZAIuBH0F3HdgY3oXyZa4z v1EsgO5JuqR6BJ1E+m04lZWfCfXdCm/1KkxnhHKlzH7KE2oktpMbGnrvr9sWdWGU0hRX Dw/g== X-Gm-Message-State: AFqh2ko4rGiC796WC3UlO8i82kldSy/7ZTGDufS4+rhJp5pBsKJpbvs4 DX2JmCQ8h7I511129b0HfTmd X-Google-Smtp-Source: AMrXdXsHMZKjsZPtwSaCA4yciZsfAMRUTiPiFIMBgtJ2CyJ6XFGBh135+6ARBuEBVQC24ILKicoVRQ== X-Received: by 2002:aa7:8c56:0:b0:576:f89d:2c4b with SMTP id e22-20020aa78c56000000b00576f89d2c4bmr38550576pfd.32.1672216896063; Wed, 28 Dec 2022 00:41:36 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 07/17] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:18 +0530 Message-Id: <20221228084028.46528-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..f861f692c9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 28 08:40:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB4DC4332F for ; Wed, 28 Dec 2022 08:42:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229912AbiL1Im6 (ORCPT ); Wed, 28 Dec 2022 03:42:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232629AbiL1ImU (ORCPT ); Wed, 28 Dec 2022 03:42:20 -0500 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41F7C101CC for ; Wed, 28 Dec 2022 00:41:44 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id w26so10304700pfj.6 for ; Wed, 28 Dec 2022 00:41:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=kBSZ1t+GTRC3OHYUNF4styvFpo4TJhUf7z0CDD6j4ujk5g/Q1WobBQMKCew6VXvXgz G5xfkeHZg6fNcOtQ1KlMJ4MNYlCqLZEMDh6v9C82kmMm+/mVieUTsa2mNKm7HwyunWd1 fuKyz2/kC/m3F90TkIKQT6YdZhLZhStrZMS/yu6fI5HlpLMf25y0LsYVQgEhhEc9FMqc N7nWQcFfoyBjfZ1VnltBlKWPYQm2JiySPE0iwyBX0vrldan/S5JtrM3KqhJksBJbWXqQ r5CmWllE3nKhCut7+hyjPUQEArO0Ux4YOWBf1gJCZgek2o+arIa6CqOWQotrkvySua4v FsCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=GSX/DGqEnaVUlBYl+J8zi3ZT5/jxTtAeR4dpnX8wyQOzX2eu6FP/Rc812VAYa7a/IA w01oC1VpiKQ9EzW1c9OC9XzAWmm/5Th3eJNPmf9I9V3dx6SASt2oYhgtzBz1JXqW1puK t9qHFrlslzENjCJV5Pwo0zOQQM9R4b5BFlc4MgoYPPeZuArPV42+s1ngkfBjiopG3ton vGd4pt13Ai0kxxLk70Erp1lLZUc1FkIOpn+m8VUUrRXaC+Itdhsd1AjklxEtZXy7Cz08 eDoNnHBrBlnHC1TjAYkGiZaMWyfhJLhm00bkcD9CWNRRgF8Eu1jmpoQRXStLoFFIH5Xf Zn6g== X-Gm-Message-State: AFqh2kphuKz0GC0ZEl6s6cSC75hAO5nYd9RbR/8lfs9kp2pl6M9dLHFU EBNLN+4xhOWj9h7C+RC0wsq9 X-Google-Smtp-Source: AMrXdXt3wEnaBxmKKc+THXJmZZQodrKRWEZGxG+TcvQ9deo7zYP1wV+ItZNcl0gY5TwuRP/6CiAjzA== X-Received: by 2002:aa7:9290:0:b0:580:c8a1:70c4 with SMTP id j16-20020aa79290000000b00580c8a170c4mr14887725pfa.29.1672216903726; Wed, 28 Dec 2022 00:41:43 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:42 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 08/17] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:19 +0530 Message-Id: <20221228084028.46528-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..6c6eb6f4f650 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 28 08:40:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B70C4332F for ; Wed, 28 Dec 2022 08:43:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232725AbiL1InM (ORCPT ); Wed, 28 Dec 2022 03:43:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232812AbiL1Imj (ORCPT ); Wed, 28 Dec 2022 03:42:39 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C64C9FCE6 for ; Wed, 28 Dec 2022 00:41:51 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id s67so869805pgs.3 for ; Wed, 28 Dec 2022 00:41:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cEcc2ZZg4+/rCWO8lF+EBDL5HIag6zFEZ6LhCeBUUxo=; b=mM6JYQb0jk21og7RBPj3Pp04t+jep2+4Zn+V+h8iqDvgSqUJi+xO4sCiKl2AseYPGT 4ECPjuk5wGtGhAFBWt77nLJKn8jbWFjka0hpnyNoQLv10Oh2HWmfydarS7uN0Xs+wEXN 73YnCny+mzGFwoqfdhKR23yjYvkwx9otssh26xK5XKNsn/LhdbKpOJS/WvJ6SYx3SecF K8/E+1lzQXmeNHAcJu16O+BuyW0LiEzv8qrI0iDnFonMswmi2dmV9irgA7MceQRUTxEG F1UsM+ZNkoMn0NFfdaN5GLoeHoqhAQYUCcq8IlPflSKOlhArg8QkfIatJYVGWhgv0VH3 pjUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cEcc2ZZg4+/rCWO8lF+EBDL5HIag6zFEZ6LhCeBUUxo=; b=xFgd6qrp1Qev1pt36PYJt66HHA62lUUsstqRsi5T5DpGduxjryCIfCZDvKPfVmWM+8 wijsmQJMlG7Dugkt+Mh52niXGTvpIXefsmuboSuX3rmqrqwjrXx+xLP6Q1yfIZz5tV/g /yootgeI1mydQPAqsyVRMOIx6Lzrmf+ywdF0q5EG0UMK7VSqjl+L4AGbQrfVjZAUqsZn JpTzOtggIgkMqbD9IW3Ox9tTXaaTcZdiskuch9FBZs2MA0gnwJh8COZZSLv2LSR2g4bR Ezy0FgekF/rhh4i5D45UtD1uHjRrqVDE6Qk1Sj4oMnl6lTOWk9MLi+4wFeK5UTu6FyiQ 8Kbg== X-Gm-Message-State: AFqh2krAXh9Ydw1oHsVXIlZlVE5j+cyrH542vTUJKXH6WjIrGzOa9zKA hfo9Gk746RrsIlAPslOyKN/f X-Google-Smtp-Source: AMrXdXvZYH0gAWe1kQmcT/Bq4rXI3pGKlar5Q3Mhyfgz9CNgIOcmHM16EWtZr8j/D49kmR0RCsEO8A== X-Received: by 2002:a62:6347:0:b0:56b:d328:5441 with SMTP id x68-20020a626347000000b0056bd3285441mr22743715pfb.11.1672216911280; Wed, 28 Dec 2022 00:41:51 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:50 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 09/17] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:20 +0530 Message-Id: <20221228084028.46528-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..0510a5d510e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,14 @@ opp-6 { system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 28 08:40:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9882C46467 for ; Wed, 28 Dec 2022 08:43:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232874AbiL1InS (ORCPT ); Wed, 28 Dec 2022 03:43:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232822AbiL1Imv (ORCPT ); Wed, 28 Dec 2022 03:42:51 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C4AAB52 for ; Wed, 28 Dec 2022 00:41:59 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id m7-20020a17090a730700b00225ebb9cd01so7564534pjk.3 for ; Wed, 28 Dec 2022 00:41:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7WUljA05hxjrMgWInu+aANTEuP2TXhzChwqlFzG2wks=; b=YbRaJdKTjanKozZ9jibrWhveX5ctEFNkLx+F0Oa42QvbwyxD6ZLBU8UUZA7DFhvKhY mBGdAIrXoriXn5vAyZdODH0VG4OpyPkvIDDw1nNnfmEKmx4ak9mEn1kd931+EnbkXrnk hMjt7Kos6E23YPkKrviHBbwQ4tqcQyA9Q6zc3IMkPL0Hexc26EAq7tn/kEj03cPe/pu6 Nrwy6KcprdjCHevGZ5/F8tpfywa846CpI4sFNSBPHY/XcxKSVQ8Cncqs43kbWYMxrq5d WjV9TUYi7ynmn0t8KGDKlAo+MTr1OlBrgUCwKVODXiYULSnFk/Eq1jPAe3rOrcFdPO7G wwmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7WUljA05hxjrMgWInu+aANTEuP2TXhzChwqlFzG2wks=; b=l8jTdwOc6OJoodt28QIsTY7eLaM/Zc5lDoKTzlP3auAk5w8g7Ko7ld8lmBSLj8hYwe 3LtJ/EqAS/Z0k7ebU58Mur8S0iwBju8DsIQXDKLzWGeeHuro/T7VYP7pWfaraWXD2K4P hz3srvGXBv7Jwi1rezNkiSIiliHaNrKEojoteHlzfenZcIr0w+UCBzKom2d1ML8wXMuh z9vnFFC+RUycyoReGm8+vmgBVZ8YCakFQxEqTz2DFnz/EULD3P50pVlPGw/Cr+U2uqYi Cfk7b3PwI8CCyiDpdvtpwpzdB4vPUUlPkQGKLyuVLs4o7mTtBAZigc0i8tCtK6TamMhZ BWFA== X-Gm-Message-State: AFqh2kqWt/ZxAFOLUZJ+0JN39uwLoMRabyeXl57ikeANIrZ5ScRsyKbN BlfNaHeXgA/lYl+A9n6pUfnI X-Google-Smtp-Source: AMrXdXtZk6AwBn/gE/Qd6zoDfLS2rMhntnEviK9TyJo7SxfSdFi0mJohahvst5pggXiK2hSVI7uQFw== X-Received: by 2002:a05:6a20:bf29:b0:a5:df86:f2b4 with SMTP id gc41-20020a056a20bf2900b000a5df86f2b4mr25040116pzb.58.1672216918839; Wed, 28 Dec 2022 00:41:58 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:41:57 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 10/17] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:21 +0530 Message-Id: <20221228084028.46528-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..7fd2291b2638 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,11 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 28 08:40:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1EC0C46467 for ; Wed, 28 Dec 2022 08:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232776AbiL1In1 (ORCPT ); Wed, 28 Dec 2022 03:43:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232830AbiL1Im4 (ORCPT ); Wed, 28 Dec 2022 03:42:56 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 715B2FCFB for ; Wed, 28 Dec 2022 00:42:06 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id s67so870101pgs.3 for ; Wed, 28 Dec 2022 00:42:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=uLb/ZHO9acuGXZNYQw0lUOz91UCx2LOPc+k611i5+YRtO95j5kzMbttDQBFv4WsN0W 5COSlFAnhI/rFjK5rDSyMiedi+CJEIbfkD4ZT9RHzzNT5/NR/1lzYqMjpcwlT7EHaU+w SKhTfYGKgDDUV/8fsFm47WJBnV7GHvfU6bMJDpMJfghSd0cjU7bpHyJMzEipZxlTL7B+ YNQROHCqIBlxEv0lIATl6vG09xNE2RBGap5dEbTV5Fm1Bv5E9ZklknzxFYjw89GU9Vy7 WaTqqM1tS3GgpKQRLSbvKx0lO6daAXvo3naMY8avJXPdbDU/cXL6ZCGzRV4s9tK3bRQT vnEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=aU0NQbGSGDXdSE4RavXXBmUlmH6bau/lrUmX6rNKuM/ltEuCLXZqnWe//h6SfBI9cZ +ESoQjgTVKQ5/yvi+evcZq2Q5x2kYqvp5dJFOIApoSv8l6OeGNnDAWi8w6Q5rLv54JdK ets/O6sEmyKFIYcO/rmIEd4vhYBPonViXkrhyhCCwbB7rnShkHVPhoIg5MncWIP2u4Op ckDr8+BCGrRKFNpPBdvd5k80RygPdYW1zZy6VQElJo1N29SdiWaQuNViqPmJ9EbrBGQc PfaXbFOVVTAO3Pn2Q4qZnR/wZHpOwgQN3CrXBpVnU3BANbevomxOBN/yBuPlCA9kQ6g/ d7NA== X-Gm-Message-State: AFqh2kqYx/Sisxe6laVPD9Bff9K0hRwljYIqYr9lweMGUziQ59iJxnrJ twL38o9op6AjM0qZhMnGRZTM X-Google-Smtp-Source: AMrXdXuymwkmD8aRAux9K4d5I+wXwJyolE2y34HFPr4t+qgayngWSW2pHLm8hpfyJiQ/WKHrPHV9WA== X-Received: by 2002:a62:60c6:0:b0:581:6b38:25bc with SMTP id u189-20020a6260c6000000b005816b3825bcmr5248457pfb.29.1672216926093; Wed, 28 Dec 2022 00:42:06 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:05 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 11/17] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:22 +0530 Message-Id: <20221228084028.46528-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..d1b65fb3f3f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,11 @@ usb_1_dwc3: usb@a600000 { system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { From patchwork Wed Dec 28 08:40:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BEA3C46467 for ; Wed, 28 Dec 2022 08:43:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232675AbiL1Inm (ORCPT ); Wed, 28 Dec 2022 03:43:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232495AbiL1InH (ORCPT ); Wed, 28 Dec 2022 03:43:07 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F3881004B for ; Wed, 28 Dec 2022 00:42:14 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id r18so10174608pgr.12 for ; Wed, 28 Dec 2022 00:42:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=hy4nC4E4al+dabRomp+OPrVVRBkiPqSdQSNvbzvr0h9pg+JqKsvvABpx/N94VxyQKO 4Fc9F9yhAarvh4qVPjwL49Va/Ac8LACS+2UrPgzNKEoRKEyei1Ug5YubxpWyOCNIadU0 uNwihQdr3mimAIBAXbUNUpnJAQ3Y7Y3DNCDiyAGV3QW14AYYG8Uk4fFWlFj05fBMMT2j apC3V24LXwNTLaQgHg3JUOn0541oMPFbmXp44QRI3TXZ6t7oANDyGRU/cIhzgWytqQ6V qRBmMAyP9p4ZxshXyE9BgRIAbMua0AaTzPpsNoNvYI2J1hHHpkpHBbXfo/9019QWhk3C A90g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=v3d3/L/IPW/sS80XXRujZs+v8gG6mBF3TCAuNOg09fZ60+AgkTUcO4F0qXrZvOQ1p3 P4s9xRwRDq3C6+46F/yjEiUU81vizUigfVGXDUdBzhwomRt32YhMykAhhDsLq9PoW2Z3 XjzZdU9q9ABV8L9SVNZyd6vSQdFarOFcIjiKf38sP8h2crB3gVFJXdTQj3iamOKdco8B l8GoWGJMhV7YQmHwN2LjuS1RdwnbRLDcnrkBoQUGc9PHvGrBQdNrHi3yt33mVvqfT08D xKsFvQIqGLJ33fDke90afkbZPPuB8jq08x9eRW9QWKZPnAlJNs62qKif+Gyo2cl+CAd+ Fo9g== X-Gm-Message-State: AFqh2kr6qu8dU6karqnI3qjaj1iH5HKgQCLq9IJ3gD2W4z0yvYtH3lzi FbVnQ7S3qMLbOk0Kfr5yY4K1 X-Google-Smtp-Source: AMrXdXsdA71Nl1ydxefCHwsDLE8v0TrPoU4ByklG2203hhg+wQHNjtGUxESyx7kelBtm4Aeie4h7LA== X-Received: by 2002:a62:1c84:0:b0:576:e4c7:97bf with SMTP id c126-20020a621c84000000b00576e4c797bfmr24944004pfc.15.1672216933591; Wed, 28 Dec 2022 00:42:13 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:12 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 12/17] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:23 +0530 Message-Id: <20221228084028.46528-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..836732d16635 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,11 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_1: usb@a6f8800 { From patchwork Wed Dec 28 08:40:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75513C4332F for ; Wed, 28 Dec 2022 08:43:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232855AbiL1Inp (ORCPT ); Wed, 28 Dec 2022 03:43:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231477AbiL1InJ (ORCPT ); Wed, 28 Dec 2022 03:43:09 -0500 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99A59FCD6 for ; Wed, 28 Dec 2022 00:42:21 -0800 (PST) Received: by mail-pf1-x42e.google.com with SMTP id y21so8119464pfo.7 for ; Wed, 28 Dec 2022 00:42:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=SEHAxbm/tlwxbMSvXx6Kn83W/mjgAGY97O8DA9p40Utz3/TdUra97SQthAuFldzs4c MopJ9AxP316k24yxgi+N9YA61a6iL7//vk5MoaxSfpwkCvcWEuvMTb+c/tMtjSg2pXYD 6USwLwSPIuEOOmHQCSzUrCEC+Haz96l+Tk0WbxNLQt6Zn8dUIB43JJNKurRIXbPAczVQ vdR2snNFBpHyPbi8QDntU4OtHp2WrBJ1TKzjCY7xZcGylYTCSW1e8sqa9PqQuHe9uHyH fCbE3iCtQfSK3nnH4yOxugPpxc7iwHObl50gmgkVKW3CRn5McuEuTLXte0h0TAZpFDHl kFpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=T/vC0fORxyptwQ7jHnm3KOY5vaH5yQ+sNCiAaUTMv5MjsEB7hilvv8Slew4PBCebMD 9GLRxYQe+qbPkM4UuRPAwvsZ/B8+51gldbnJka0jacsZDNyZPwXIlvPuLemxwCu9gvGk shcOVfH0dzaCv6iFT2QWuP/Psl6J6LxIxCccz6IzlEVYOK/kzNJvWIWugOiTxAPzxiMV VdXyNkNumXxAVqXj6NlAi+4IXvJRmC0Go2JPvJltkLf9epocALposT9X/8rtJxawpF3C N3YQ6n1xsR1gDyTl0VTv8iz+dcczmQuVLWyld2cTglNbg7kH8sVDP9OYFWNHhkhmwUKm hmeA== X-Gm-Message-State: AFqh2kqVR7FjD6KWUPtXhsynS+Cbgi7DtecXTUx+nEksl0Xn9ajDn5TX Mkq+hLMA4JHThgE7LGfItEBIl9LyNV1UPCU= X-Google-Smtp-Source: AMrXdXsMqv2J4+7EQ7K+0q81giuxF+hAAR7j07C6EKMtcDjKLvEw/sT8ld3C/LgENPFwcw3yBVfmvQ== X-Received: by 2002:a62:f20f:0:b0:56b:b890:6ccd with SMTP id m15-20020a62f20f000000b0056bb8906ccdmr24976154pfh.4.1672216941105; Wed, 28 Dec 2022 00:42:21 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:20 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 13/17] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:24 +0530 Message-Id: <20221228084028.46528-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..12549a2912c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Dec 28 08:40:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74BF9C4332F for ; Wed, 28 Dec 2022 08:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232761AbiL1Int (ORCPT ); Wed, 28 Dec 2022 03:43:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232721AbiL1InM (ORCPT ); Wed, 28 Dec 2022 03:43:12 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E896FCD9 for ; Wed, 28 Dec 2022 00:42:29 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id o31-20020a17090a0a2200b00223fedffb30so15438014pjo.3 for ; Wed, 28 Dec 2022 00:42:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=iIHueAUz0G9Q5Qor23ltImQgj8YpTUuI/PbDrcEdsTQqLprCC3c+/GhTb7Wa8hwNUx PTj4TdPafPSASxxhHacbBAnqwos9HjyGHVsNYQqclReq/BLKrfQgtBRzSghtWrSTmJgr 44WjAWGVmA4fA5y4iGXiTIQ/qPE/dS5M/cAD8O/dQBXvu3PjOlLNfa/vzJDGvw8dag/2 7UK57ETnT0B5AgeooJ4F67sjWayL28Auq/DQSzGPr6xsXLTDdL+urgDlAB0KI1IIOu4P YK0vbGYdX/80fFPCl9BWo543P/lHDM9gc5daGv3xZbhWbFMf8b/77TbkQTQ+08H5ZQDE o3nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=BahXtkFsUn3+VOTCOirGHk9ezGykZe+63pEBEiHvI8yjBWORNTTC7jNdtMCBgsEHBm /Pu4BrkpJzYRKMplVoVBpkLLXsCsBXOkpXR5pHWS1LObp5vjRSeAoQZ7hbST2+uxVXh3 jd3FIfs1JNpE/qiuJWW4nJ3c28KnNLsYotw7QJ7IlW2stywiMVB4ZsLHqrgQkG5+wPQj kDWPnjY4s8PolbJbueD7suMEOnAeIWCsRtiky6AjtBNeVYW+Lm/fVOCkptHaKiBn7MFg 6X6Pxa8kZQ+rh0mfFOoKoiPLnmW+gxSqIUX9Pcsj18kgepVVtquAjHQQXuvHzophScSd 2Ggw== X-Gm-Message-State: AFqh2krb+AroFh2M4SMaH3JtVZwkwkB2mjCgicBKOWIFmkdBlvKNu6mt Be0ELMJzkQs9CyxYqDPg0uKS X-Google-Smtp-Source: AMrXdXubDuV4Ljz5PUmqbjDeuct0HvYN+u37AkAMnMvW2w/GVyk4a0aKPsRzW1uOqJG76o2FKQ4DcA== X-Received: by 2002:a05:6a21:9218:b0:9d:efbf:787d with SMTP id tl24-20020a056a21921800b0009defbf787dmr29695708pzb.50.1672216948793; Wed, 28 Dec 2022 00:42:28 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:27 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 14/17] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Wed, 28 Dec 2022 14:10:25 +0530 Message-Id: <20221228084028.46528-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..c7701f5e4af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From patchwork Wed Dec 28 08:40:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F75BC3DA7A for ; Wed, 28 Dec 2022 08:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232523AbiL1Inw (ORCPT ); Wed, 28 Dec 2022 03:43:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232819AbiL1InO (ORCPT ); Wed, 28 Dec 2022 03:43:14 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 708331D3 for ; Wed, 28 Dec 2022 00:42:36 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id jn22so15442568plb.13 for ; Wed, 28 Dec 2022 00:42:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=65hsAFSVLExCXYMDq8UQxFyuNWWlmEvo8D8bnHIehrE=; b=SsGfrkqinhbP8boq94X/MdsdinZz5T1nd1Zk62Ks/s97gNdsRa7p/R3tbYrDNIIHln gGgTvXij3GB+Xw0f2/ELmpPR7SiJ9M1MDvEYE87tm8n29J03+MSWMVZ6cf6wP3MDL+/s uAUkCbK1289tWlPYxpVAioLLPaHf/wwbY92ueeAjDyl4v2qo9RUkMqmSmPQM7sBSGf/5 XAN9HcTN7ZI+JaYilCILDRtqVFG7kfmIocdPo6ZG7c/kCcESqrsLLK1kHNOW7rcdoVF6 3BySnukO5b+th2813ItZgFMv9zuRRMn7svbVmbtukx3wd/vQd0BHcRFNbbvR8oJGu8xM Rs1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=65hsAFSVLExCXYMDq8UQxFyuNWWlmEvo8D8bnHIehrE=; b=NCsQb8wlIXeSAh6zeS2wDBeeHlsnU07LLfRKKyTv9YKyv94Ra3p9l2NsWzBF9VmDkw cfQJXzfeFrItsF+iR1uNb4UdjstVwxDnMIvu1BSaJ8bdidkHMC9oqGBlV1B/ZT1e1qr1 tv9VYEWTztIenp25BJEFrH7aki53QUA8sTcQUiyZoyMNTKMFPBQ1LrVLOib+xZ1VfeE+ yTuepYzHmvvJ78YB7ex/MDB5kPK9Zhx6c4W+VM5K+m6LB9unQMgYHxFhm32MKVhwZd7t fJl/X/KexTBMgAzBlg0Sj+ZFG91NaTKs0NFrNoTALThkVKChenDlWFM3RVxJj3E8ogRO 12KA== X-Gm-Message-State: AFqh2koBUnlX3yogrnZzaEiEdAFCUgsGuotInSSbC0MISyXV6lEGh0NK 24htRBx/WwzIsVzgAEcRgMSL X-Google-Smtp-Source: AMrXdXuN+Av3jzzhgvLyAUT/9W6YiSkjN7kWtQWggVQdgi5GFzm3Rb6UVfCiHFuH6swcs8Op9diapA== X-Received: by 2002:a05:6a20:4904:b0:9d:efbf:8156 with SMTP id ft4-20020a056a20490400b0009defbf8156mr40889302pzb.31.1672216955852; Wed, 28 Dec 2022 00:42:35 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 15/17] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Wed, 28 Dec 2022 14:10:26 +0530 Message-Id: <20221228084028.46528-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, we no longer need to rely on reg-names property and get the base addresses using index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those needs to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam Reviewed-by: Borislav Petkov (AMD) --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg = of_device_get_match_data(&pdev->dev); + + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { ret = PTR_ERR(drv_data->bcast_regmap); goto err; } - cfg = of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; From patchwork Wed Dec 28 08:40:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D52CDC3DA7A for ; Wed, 28 Dec 2022 08:44:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232921AbiL1Io1 (ORCPT ); Wed, 28 Dec 2022 03:44:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232830AbiL1In2 (ORCPT ); Wed, 28 Dec 2022 03:43:28 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C72D71004F for ; Wed, 28 Dec 2022 00:42:43 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id s67so870829pgs.3 for ; Wed, 28 Dec 2022 00:42:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dmgmy1WkNpy5rN0a0WaCg+UaF5eldkFegxv86WikVN4=; b=pVHwuZ2c7VrUE5Wd2ya4PpcVuLE6eNZ6ATLAbSIPuSaAUeIDwYtrZggSCCm2gmA8qH JTWC5T1yfXtnVTlvKQethFlb0qfZF8bYG6sKsZLFnxRFA5SUKm/En1vFVuX2j65a/OY3 IL/4uGH5m+ZfdPLzyDy9Z7ovx80C/GorxXYlXkXep0wCXiIeAxrOd/X+XbIPoFekW736 ydBVY0pcv1Wi9WmO8SmlHhLpa7ddE4XPFkR5dJ2GXFf8gGG2N7uI7cpsPGuMWnEhE3yU A1P2pdkm0woo+8+YjRKLZJJk+8U7Q1LmwE+DLx8d8VgHS/gZPlUrc3gHhs+iZEeymP6s gytw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dmgmy1WkNpy5rN0a0WaCg+UaF5eldkFegxv86WikVN4=; b=y6scuLnpI05qXKsThiT9EGymnicMD+YsiGWW0Q+jKj1lny1F20UvUsUkFQ9YjagadJ P+JIhW3gMiV3rv0Gizu4sHC/w5qgM7w+rV/VJh4M7wKqlyEkPFniiuWK8UPdFCOSp4o8 IO1FD3wJtrQzrd8MIFyfBzktczCoSvr9f032Mg2raHQW3xJAgNBeXfplRIziUnksjk+6 tg3imrtI28eW6IcDeCa+BWcHNWA4Lhz9F+jpA5lYkzGpCpoGQJLoeyOtg449+6MUyZda Owpr7fRUQnMHNmisnqRZ33WMM/YsiVMUINjQPmsWnDWGC1PzDpBfhScrdPmGHKXjruVe 1GzA== X-Gm-Message-State: AFqh2koT0htOnMpEA3gJAEzif8F9pU1zVEdDxdWam35TyNVWbj9CJNX1 zZiAXYSgGqJuue7ZFqo3fDsw X-Google-Smtp-Source: AMrXdXtJKvkLftrOG21ijD/t8yxigqDi4l4ZJej4ePx4o5qxlVks6rYjVxk7w2Wg5P1VmHt8j+zPYw== X-Received: by 2002:a05:6a00:414c:b0:581:7c46:debd with SMTP id bv12-20020a056a00414c00b005817c46debdmr3704718pfb.24.1672216963254; Wed, 28 Dec 2022 00:42:43 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:42 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v5 16/17] qcom: llcc/edac: Support polling mode for ECC handling Date: Wed, 28 Dec 2022 14:10:27 +0530 Message-Id: <20221228084028.46528-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 1d3cc1930a74..cfcdc35b0373 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE = 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) return ret; } -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -355,22 +361,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq = llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + edac_op_state = EDAC_OPSTATE_INT; + } else { + /* Fall back to polling mode otherwise */ + edac_op_state = EDAC_OPSTATE_POLL; + edev_ctl->poll_msec = ECC_POLL_MSEC; + edev_ctl->edac_check = llcc_ecc_check; + } + rc = edac_device_add_device(edev_ctl); if (rc) goto out_mem; platform_set_drvdata(pdev, edev_ctl); - /* Request for ecc irq */ - ecc_irq = llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc = -ENODEV; - goto out_dev; - } - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + /* Request ECC IRQ if available */ + if (ecc_irq > 0) { + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (rc) + goto out_dev; + } return rc; diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); return 0; err: From patchwork Wed Dec 28 08:40:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13082790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F2B6C4708D for ; Wed, 28 Dec 2022 08:44:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232934AbiL1Iov (ORCPT ); Wed, 28 Dec 2022 03:44:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232908AbiL1IoJ (ORCPT ); Wed, 28 Dec 2022 03:44:09 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B7FA1056B for ; Wed, 28 Dec 2022 00:42:51 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id k19so2608525pfg.11 for ; Wed, 28 Dec 2022 00:42:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t4t3wjs91jqYDdhcaBgIoHHF665G49/NIuIJvlGrcfA=; b=imJgc7Ixk5aekscKAi7ezzMRHSzFJJTv+Rq9u2se4QLC3CgFHjcLdLAqnY2rzzFixf FB/pf4o10XfdXgwrgeJuwnCZYYnEreMSGeaAybI3Jzs4/o52VhkkDlL6PJnDfWn9ShtF mqaC6Bf6E2WPM+/9orsIi8nkgVl4TyzU8rHRPvO4INIZML0JinHhsY7rM4Y0xeqCg9z9 l/2zHbqrpeISzR07n/1geMozRMXA5pbcrDiMRfIfZA5Ixv0GK4bdYcQfyyAQdnt8fIm5 8awUhpTgxQrL7XVdYHyYQoNIay9wGN9reUFCp1rLQH7N+o2jcbG5TXcArgmP8SXEtqCc FMvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t4t3wjs91jqYDdhcaBgIoHHF665G49/NIuIJvlGrcfA=; b=aREJz+5J33O3P+QIsjJjObS550X1tSAu90scIIOJSvNcJMqH85OfKwHuZuB37XKyfh Z09nbpKgM8eME8Rs3+8L0wOM09jPM7UapitZ5wReDdVSxIFHw2qkR+MoW0yvtcejg/s3 khmzts36t/88e5AWzg49qgj44AkMBvqkKDIrTjmwmVpTCUydGXJcfGzprXo2Kg0+hskl IYdjugqIFOiO/gbwg55ekvWKo1p6J6KBa18+XTVy1e2mptRs0k4pu5WLy59Rsvez0Wd0 j6RQmJodgRFxaJ1W2W+Qy2B6nzrLpaqAyXCG8weWkri81WfPPGG49Q5pMemdtZe9KdL8 4LRA== X-Gm-Message-State: AFqh2krUMn5g3o+TKjhwV6BIrqktISnECtOX3dMZ1yLn4J7SVSjVncig EpP+LOonc1YjSOL9KJLSFQYP X-Google-Smtp-Source: AMrXdXvSYBjnlw6dNXNKrCldqAfDaRwwTmdPy20rhmuxhW42MAtunz6GotQ6FvGBfFh2eY2A3ffN9g== X-Received: by 2002:a05:6a00:1485:b0:575:b783:b6b3 with SMTP id v5-20020a056a00148500b00575b783b6b3mr34741803pfu.28.1672216971036; Wed, 28 Dec 2022 00:42:51 -0800 (PST) Received: from localhost.localdomain ([117.217.178.73]) by smtp.gmail.com with ESMTPSA id d188-20020a6236c5000000b0057a9b146592sm9786286pfa.186.2022.12.28.00.42.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 00:42:50 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v5 17/17] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Date: Wed, 28 Dec 2022 14:10:28 +0530 Message-Id: <20221228084028.46528-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> References: <20221228084028.46528-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. Cc: # 5.10 Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/soc/qcom/llcc-qcom.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 7b7c5a38bac6..8d840702df50 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1012,11 +1012,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); + /* + * The platforms based on SDM845 SoC locks the access to EDAC registers + * in bootloader. So probing the EDAC driver will result in a crash. + * Hence, disable the creation of EDAC platform device on SDM845. + */ + if (!of_device_is_compatible(dev->of_node, "qcom,sdm845-llcc")) { + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); + } return 0; err: