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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id y16-20020ac255b0000000b004cb0242704asm1627039lfg.255.2022.12.28.03.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 03:24:59 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] arm64: dts: qcom: sm8350: add missing core_bi_pll_test_se GCC clock Date: Wed, 28 Dec 2022 12:24:55 +0100 Message-Id: <20221228112456.31348-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC bindings expect core_bi_pll_test_se clock input, even if it is optional: sm8350-mtp.dtb: clock-controller@100000: clock-names:2: 'core_bi_pll_test_se' was expected Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d473194c968d..d5747bb467e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -644,6 +644,7 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; clock-names = "bi_tcxo", "sleep_clk", + "core_bi_pll_test_se", "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_card_rx_symbol_0_clk", @@ -661,6 +662,7 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, + <0>, <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, From patchwork Wed Dec 28 11:24:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13082881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36A2CC3DA7C for ; Wed, 28 Dec 2022 11:25:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232960AbiL1LZG (ORCPT ); Wed, 28 Dec 2022 06:25:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229966AbiL1LZD (ORCPT ); Wed, 28 Dec 2022 06:25:03 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D5535F7C for ; Wed, 28 Dec 2022 03:25:02 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id z26so23226236lfu.8 for ; Wed, 28 Dec 2022 03:25:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wxQKtpqEKgNK0XIww8UA1aIJr9PXHMFG6enXL7OwExY=; b=X2yYaoQkwcf+fjR2y5L5/FMtbY5h8aX9N1N9MLHHS6HY/UL9kV694QTCF2e/AeMsh1 W7odb08NMLRXNkwpjJCN4tEui8RbViWxpaMly2HfR2hq6FtaijaHAwAFATmukD5WyWMw Lv4v5DgUgVGyOgT/EsIb6ApRJxFY0lQjnOLKrago59JiGtyFbwK7E/1GpbNP1x24BFLX L9AYsu5cFf82wc3ERKcY0XB75hdl2Lz84SAtn23ISgvWO7sh0wqpVcZQPFMoxcR/PMvK MQii8pX0WE6t98maJQDYf4f9wU+JuxOJ2fAM6l5Z4Sfi1dF93awz40P75S8+QvfcovFI h2Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wxQKtpqEKgNK0XIww8UA1aIJr9PXHMFG6enXL7OwExY=; b=LbIlkPQN45x3fqauELN8T4DZaoLQcFUd2ShRfa/l8wPC6Z9G+jr6Y+Pk+fkk1V+M5i t72ZLe7o+zU7VqgOTMeQI5u/vLqE4KQtEbbZODMlvP/vSVsIdOEqJHnItRXMvXuWBCQY SYt+L05FlM9kjzpeVQt6Y/hlCrPTO8hAKVK9rcHPSTQyBek3oSulMuRvKsYcDJvj0u2O 1TXMP2Gg/nxBGaTqAZmOBWyLYMpKohbzayENNXvNxX0USrYIK0thRKLHm7TGAMsDlfse YiMpRq62njuwP+TekY5bfvpUMjOfKKFcwl0NEOSOML9nqKWyVa+Xs2hHQ3qnT5D5/cO2 IEcQ== X-Gm-Message-State: AFqh2krmLTk8Z/W5ed7Nno8OtcZvEAw0TOg7GBp8VkAW/VPOOHFG4viD cs2mlHh4332+8SGYwol+6Ov0dw== X-Google-Smtp-Source: AMrXdXtCuX1JohTI75HT0EnQ6wennnb5DL6K2v/XA9356DTxwFDa+hJP9kdXWCba5ho8k6zebHlwIw== X-Received: by 2002:a05:6512:3589:b0:4b1:feb:a338 with SMTP id m9-20020a056512358900b004b10feba338mr6613067lfr.46.1672226700677; Wed, 28 Dec 2022 03:25:00 -0800 (PST) Received: from krzk-bin.NAT.warszawa.vectranet.pl (088156142067.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.67]) by smtp.gmail.com with ESMTPSA id y16-20020ac255b0000000b004cb0242704asm1627039lfg.255.2022.12.28.03.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 03:25:00 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] arm64: dts: qcom: sm8350-sony-xperia-sagami: specify which LDO modes are allowed Date: Wed, 28 Dec 2022 12:24:56 +0100 Message-Id: <20221228112456.31348-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221228112456.31348-1-krzysztof.kozlowski@linaro.org> References: <20221228112456.31348-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This board uses RPMH, specifies "regulator-allow-set-load" for LDOs, but doesn't specify any modes with "regulator-allowed-modes": sm8350-sony-xperia-sagami-pdx214.dtb: regulators-0: ldo5: 'regulator-allowed-modes' is a dependency of 'regulator-allow-set-load' Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 4862fd69413e..a403fabc8da7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -171,6 +171,8 @@ pm8350_l5: ldo5 { regulator-max-microvolt = <888000>; regulator-initial-mode = ; regulator-allow-set-load; + regulator-allowed-modes = ; }; pm8350_l6: ldo6 { @@ -179,6 +181,8 @@ pm8350_l6: ldo6 { regulator-max-microvolt = <1208000>; regulator-initial-mode = ; regulator-allow-set-load; + regulator-allowed-modes = ; }; pm8350_l7: ldo7 { @@ -187,6 +191,8 @@ pm8350_l7: ldo7 { regulator-max-microvolt = <3008000>; regulator-initial-mode = ; regulator-allow-set-load; + regulator-allowed-modes = ; }; /* L8 - lcx.lvl (ARC) */ @@ -197,6 +203,8 @@ pm8350_l9: ldo9 { regulator-max-microvolt = <1200000>; regulator-initial-mode = ; regulator-allow-set-load; + regulator-allowed-modes = ; }; };