From patchwork Sat Dec 31 10:47:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 429ECC3DA7A for ; Sat, 31 Dec 2022 10:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229486AbiLaKr5 (ORCPT ); Sat, 31 Dec 2022 05:47:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231761AbiLaKry (ORCPT ); Sat, 31 Dec 2022 05:47:54 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3F4E63E6 for ; Sat, 31 Dec 2022 02:47:52 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id x22so56349136ejs.11 for ; Sat, 31 Dec 2022 02:47:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MlxmeaIHk8OrzWPfE3cm09UY7yzoRBn0Uu2mQgPXmdk=; b=S+QfZYeGZv2u4Pj/RfMQHserifc6sZuTu+rOAN4eYOI89qwvHyEgnRIrVh8oBeeSgA y6kkfDGh4WOtOTFA4pXjUoEcJFaOLt48FlzmHzdxoHzDAbdtt+mGZ/NHSEtfJZWqC05o +Zr/ZptCwfmVuNOMQ4buPQs8qDjUQyV4k+GGU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MlxmeaIHk8OrzWPfE3cm09UY7yzoRBn0Uu2mQgPXmdk=; b=c8GHzpUf5WIIXRcnEpxkOTSCS0qhMmI1DenWrzS28XGHbeuzVmqaNoeowfpZlqr7ri 7v0NdHYvlI7qX1KsJAzORFGATlZx+A5akbClxLgOwu6Kxi7+AZJ1NS369FoP1kqNXAT2 vTW5+LEZUBJtOBncx8wuhN6lGJWBJYPWzgHzv6CqAnt7NTTI0nofOVyr6eLHk7DiEO2t dqyC6zSRpI6zvdI2ZM1pGFg1Buk1MuS2Egery6f7FkhGLKbQ/97qa2LxNkI4VFRgTxZv NkOOK4HAhGREksnBMKbnmbmfElYkd/d97koSnbC1nI0EEug3hAKk71aTBK7XdjQs+rzl EzHA== X-Gm-Message-State: AFqh2kp6C7iiEL/EIHByOBb6ZMG4CQTr0lECuuhB6IGBNeuJdUEgGCQq WZanzohIzDysRFNa9/cYImoHww== X-Google-Smtp-Source: AMrXdXssd4th2tQ+K3pikob5HvmOdLstBIM/Xz4rVcfK8ulWOXsUv0KvoKsIAwFQcCOjQNqi6CJzBw== X-Received: by 2002:a17:907:c296:b0:820:4046:1586 with SMTP id tk22-20020a170907c29600b0082040461586mr27687273ejc.12.1672483671115; Sat, 31 Dec 2022 02:47:51 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:50 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 01/11] clk: imx: add structure to extend register accesses Date: Sat, 31 Dec 2022 11:47:26 +0100 Message-Id: <20221231104736.12635-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The imx_clk_reg structure allows accessing both registers that belong to specific modules and those that are registered in syscon through the use of the regmap API. This is a preparation patch for the upcoming support to setup clocks directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 689b3ad927c0..86538c990a0d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -89,6 +89,18 @@ struct imx_fracn_gppll_clk { int flags; }; +/** + * struct imx_clk_reg - imx register declaration + * @base: the register base address + * @regmap: the register map + * @offset: the offset within @base or @regmap + */ +struct imx_clk_reg { + void __iomem *base; + struct regmap *regmap; + u16 offset; +}; + struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk); From patchwork Sat Dec 31 10:47:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4BCCC4708E for ; Sat, 31 Dec 2022 10:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231776AbiLaKr4 (ORCPT ); Sat, 31 Dec 2022 05:47:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229486AbiLaKrz (ORCPT ); Sat, 31 Dec 2022 05:47:55 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10C435FD8 for ; Sat, 31 Dec 2022 02:47:54 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id r26so28355012edc.5 for ; Sat, 31 Dec 2022 02:47:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9LiLmCOA0Z19dwC3ajYydNnRTh+WZFHl0GJOC3Tfb7Q=; b=dpGsl32H+NNVcVtEIx85ju9cr7IPOJOUIB3kqId8lldf1S2UdBpejzWuX5tcYFMVkC SphizhvcFMKwotnjfF3ENAJyHrLnQOw1+cZsYrMbqnDe+d8tEmLIyZILWJetG6yFygEE pMEWbfKZYxwJNhExR13BT9opcQBihG3SXXY2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9LiLmCOA0Z19dwC3ajYydNnRTh+WZFHl0GJOC3Tfb7Q=; b=vE50aT6uNqc9rvp4jyhelCC8QFZwNSjT6QiLqwvcWXtPVqRT2fwyN/+L3UDUGmrG37 TMZdeuGwjgIdA+4f01Ownxqgx63UMkmMfZ1meKf2rVRIAWetw61wqOZtLVUxA3zIELFc hpl0Uxt3Jyu6vVaxtHvzBCnnxcGCRDp+P7h1kq0aSwa1IuTBm79VJdFaPnNROjbDJaTH NDBZsJfmA6L8HU3cI919UVK5O48qbhrmM3kVNUSEWQ+h3k2KctZCMEny4zU3RX+s5Cxv 9kkkIj6SJeP1nkuZWlEUDXXMlptUx/lHxS1eB3wUqyfti2eZTSl7wZGLhGq1a9ngmMhf N0Rw== X-Gm-Message-State: AFqh2kp79gPS5GZIj/1JSBHARIOEul6Fayw04YKVD3Rb42t63W4CI1/T LYkQEp2ID2oOl8P/fjR/k8LR3g== X-Google-Smtp-Source: AMrXdXuh52WUWq6kR8l8ZywR9zEG9r0GqDzyIKcqeFwzq4G9eJcKVr/9ag8SH66WV0CFa3iTrqZ9Kg== X-Received: by 2002:a05:6402:f05:b0:45c:834b:f28c with SMTP id i5-20020a0564020f0500b0045c834bf28cmr31100958eda.9.1672483672554; Sat, 31 Dec 2022 02:47:52 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:52 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 02/11] clk: imx: add clk_hw based API imx_get_clk_hw_from_dt() Date: Sat, 31 Dec 2022 11:47:27 +0100 Message-Id: <20221231104736.12635-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Clock providers are recommended to use the struct clk_hw based API, so add an IMX provider helper to get clk_hw from device tree node name. This is a preparation patch for the upcoming support to setup clocks directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.c | 21 +++++++++++++++++++++ drivers/clk/imx/clk.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index b636cc099d96..6ae122ccd83e 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -68,6 +68,27 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) } EXPORT_SYMBOL_GPL(imx_check_clk_hws); +struct clk_hw *imx_get_clk_hw_from_dt(struct device_node *np, + const char *name) +{ + struct of_phandle_args clkspec; + struct clk *clk; + + clkspec.np = of_find_node_by_name(np, name); + if (clkspec.np) { + clk = of_clk_get_from_provider(&clkspec); + if (!IS_ERR(clk)) { + pr_debug("%s: got %s clock\n", __func__, name); + of_node_put(clkspec.np); + return __clk_get_hw(clk); + } + } + + pr_err("%s: failed to %s clock\n", __func__, name); + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(imx_get_clk_hw_from_dt); + static struct clk *imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 86538c990a0d..a0e6b8357eb7 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -294,6 +294,9 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); +struct clk_hw *imx_get_clk_hw_from_dt(struct device_node *np, + const char *name); + struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); From patchwork Sat Dec 31 10:47:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A05BC46467 for ; Sat, 31 Dec 2022 10:48:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231761AbiLaKr6 (ORCPT ); Sat, 31 Dec 2022 05:47:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231810AbiLaKr4 (ORCPT ); Sat, 31 Dec 2022 05:47:56 -0500 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70975645F for ; Sat, 31 Dec 2022 02:47:55 -0800 (PST) Received: by mail-ej1-x642.google.com with SMTP id x22so56349295ejs.11 for ; Sat, 31 Dec 2022 02:47:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IcEaICywm+0WRzTCyxMBWQ3K+HlDrikikPFrWzM/DaQ=; b=I8RIy1OktpVsbRpdmWg43bz4+D803jKtzwDbMPvBKSHl6gv9lqEPzvf83PEGNiR4ip BOL6wHstTxnQmvCBlZpt5d5k+RrlgFN8yHeZkUMOBhKX2gjyzxCF6CZx/CwMLwTqE7lX BYVEZc7LX2SORaTEAUwaSZsrJLkmVp3Bfm2qw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IcEaICywm+0WRzTCyxMBWQ3K+HlDrikikPFrWzM/DaQ=; b=M8MmHz2AN5ChsI9gl2QJpYvCVHGZVIQpC7FKVql9+T1JR8Y39QCUPJnzvhAwfDk5US 64jltUiLXmsm19rxdSEDdJTpLxhz2ORNebcgvafn94rqB1ltqHwt9KoXyPcfVJCgsXs9 Vw/8Pt7wp2Rz44B5a4jSS4SmmoundwvaUmirmTyP3KrYQYQCPIDznOXM6nqGKFtQSyHr B4W11pS7XqBTQsInW/52qs/ixJO/EstV4HjZ8jDZ6HGRIr8K/J+Zk3g8EcQt1dLwyHyi hZxWD1PbDJ5T9gfqHeNdRvoHVVVgC2hhQjSEPLeWZn/62wYYXL2hO9vj9U0jTTc80Za9 Fn+w== X-Gm-Message-State: AFqh2kpB8a8kAuBF7bprq0pGrAT6cZEw8OA6GoANHI4Z+QssHBHq/srA EISt3DFkBdISr3P91dE+MBwBTQ== X-Google-Smtp-Source: AMrXdXsZ1DnWXF3cwjmhe5cQIwc3pa88nJl+BqujUnRqk6Vxg2ufSDQ/pcYcfQVMlsRYJnlHQfgIOg== X-Received: by 2002:a17:907:8312:b0:7c1:bb4:ea20 with SMTP id mq18-20020a170907831200b007c10bb4ea20mr28492064ejc.71.1672483674014; Sat, 31 Dec 2022 02:47:54 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:53 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 03/11] clk: imx8mn: add gate driver Date: Sat, 31 Dec 2022 11:47:28 +0100 Message-Id: <20221231104736.12635-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch adds support for imx8mn gate clocks to be initialized directly from the device tree. Currently all i.MX gate clocks are initialized by legacy code with hardwired parameters. This approach has generated a proliferation of setup functions with unclear names: git grep "#define imx_clk_hw_gate" drivers/clk/imx/clk.h drivers/clk/imx/clk.h:#define imx_clk_hw_gate(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate_dis(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate3(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate4(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-gate.c | 156 +++++++++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+) create mode 100644 drivers/clk/imx/clk-gate.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index e8aacb0ee6ac..72e1f08d49dc 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -11,6 +11,7 @@ mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o mxc-clk-objs += clk-fixup-mux.o mxc-clk-objs += clk-frac-pll.o +mxc-clk-objs += clk-gate.o mxc-clk-objs += clk-gate2.o mxc-clk-objs += clk-gate-93.o mxc-clk-objs += clk-gate-exclusive.o diff --git a/drivers/clk/imx/clk-gate.c b/drivers/clk/imx/clk-gate.c new file mode 100644 index 000000000000..841ff9a37f30 --- /dev/null +++ b/drivers/clk/imx/clk-gate.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_gate(_hw) container_of(_hw, struct clk_imx_gate, hw) + +struct clk_imx_gate { + struct clk_hw hw; + struct imx_clk_reg reg; + u32 enable_mask; +}; + +static int imx_clk_gate_enable(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_reg *reg = &gate->reg; + + return regmap_update_bits(reg->regmap, reg->offset, gate->enable_mask, + gate->enable_mask); +} + +static void imx_clk_gate_disable(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_reg *reg = &gate->reg; + + regmap_update_bits(reg->regmap, reg->offset, gate->enable_mask, 0); +} + +static int imx_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_reg *reg = &gate->reg; + unsigned int val; + + if (regmap_read(reg->regmap, reg->offset, &val)) + return -EIO; + + return !!(val & gate->enable_mask); +} + +const struct clk_ops imx_clk_gate_ops = { + .enable = &imx_clk_gate_enable, + .disable = &imx_clk_gate_disable, + .is_enabled = &imx_clk_gate_is_enabled, +}; + +static void imx_clk_hw_unregister_gate(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + + clk_hw_unregister(hw); + kfree(gate); +} + +static struct clk_hw *imx_clk_hw_register_gate(struct device_node *node, + const char *name, + unsigned long flags, + struct imx_clk_reg *reg, + u8 enable_bit) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; + struct clk_imx_gate *gate; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_gate_ops; + init.parent_data = &pdata; + init.num_parents = 1; + + memcpy(&gate->reg, reg, sizeof(*reg)); + gate->enable_mask = BIT(enable_bit); + gate->hw.init = &init; + + hw = &gate->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_gate_clk_setup() - Setup function for imx gate clock + * @node: device node for the clock + */ +static void __init of_imx_gate_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg reg; + const char *name = node->name; + u8 enable_bit = 0; + u32 val; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (IS_ERR(reg.regmap)) { + pr_err("missing regmap for %pOFn\n", node); + return; + } + + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + enable_bit = val; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_gate(node, name, 0, ®, enable_bit); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_gate(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, enable-bit: %d\n", name, reg.offset, + enable_bit); +} +CLK_OF_DECLARE(fsl_imx8mn_gate_clk, "fsl,imx8mn-gate-clock", + of_imx_gate_clk_setup); From patchwork Sat Dec 31 10:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFF21C3DA7A for ; Sat, 31 Dec 2022 10:48:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231875AbiLaKsD (ORCPT ); Sat, 31 Dec 2022 05:48:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231862AbiLaKr7 (ORCPT ); Sat, 31 Dec 2022 05:47:59 -0500 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C3A5645F for ; Sat, 31 Dec 2022 02:47:57 -0800 (PST) Received: by mail-ej1-x642.google.com with SMTP id m18so56312859eji.5 for ; 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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 04/11] clk: imx8mn: add mux driver Date: Sat, 31 Dec 2022 11:47:29 +0100 Message-Id: <20221231104736.12635-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch adds support for imx8mn mux clocks to be initialized directly from the device tree. Currently all i.MX mux clocks are initialized by legacy code with hardwired parameters. This approach has generated setup functions with unclear names: git grep "#define imx_clk_hw_mux" drivers/clk/imx/clk.h drivers/clk/imx/clk.h:#define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-mux.c | 258 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 259 insertions(+) create mode 100644 drivers/clk/imx/clk-mux.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 72e1f08d49dc..1cffc5bebbe1 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -15,6 +15,7 @@ mxc-clk-objs += clk-gate.o mxc-clk-objs += clk-gate2.o mxc-clk-objs += clk-gate-93.o mxc-clk-objs += clk-gate-exclusive.o +mxc-clk-objs += clk-mux.o mxc-clk-objs += clk-pfd.o mxc-clk-objs += clk-pfdv2.o mxc-clk-objs += clk-pllv1.o diff --git a/drivers/clk/imx/clk-mux.c b/drivers/clk/imx/clk-mux.c new file mode 100644 index 000000000000..426738d25582 --- /dev/null +++ b/drivers/clk/imx/clk-mux.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_mux(_hw) container_of(_hw, struct clk_imx_mux, hw) + +struct clk_imx_mux { + struct clk_hw hw; + struct imx_clk_reg reg; + u32 mask; + u8 shift; + u8 saved_parent; +}; + +static int imx_clk_mux_write(const struct imx_clk_reg *reg, u32 val) +{ + int ret = 0; + + if (reg->base) { + writel(val, reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_write(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static int imx_clk_mux_read(const struct imx_clk_reg *reg, u32 *val) +{ + int ret = 0; + + if (reg->base) { + *val = readl(reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_read(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static u8 imx_clk_mux_get_parent(struct clk_hw *hw) +{ + + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + int num_parents = clk_hw_get_num_parents(hw); + unsigned int val; + int ret; + + ret = imx_clk_mux_read(&mux->reg, &val); + if (ret) + return ret; + + val = (val >> mux->shift) && mux->mask; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int imx_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + unsigned int val; + int ret; + + ret = imx_clk_mux_read(&mux->reg, &val); + if (ret) + return ret; + + val &= ~(mux->mask << mux->shift); + val |= index << mux->shift; + return imx_clk_mux_write(&mux->reg, val); +} + +/** + * imx_clk_mux_save_context - Save the parent selcted in the mux + * @hw: pointer struct clk_hw + * + * Save the parent mux value. + */ +static int imx_clk_mux_save_context(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + mux->saved_parent = imx_clk_mux_get_parent(hw); + return 0; +} + +/** + * imx_clk_mux_restore_context - Restore the parent in the mux + * @hw: pointer struct clk_hw + * + * Restore the saved parent mux value. + */ +static void imx_clk_mux_restore_context(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + imx_clk_mux_set_parent(hw, mux->saved_parent); +} + +const struct clk_ops imx_clk_mux_ops = { + .get_parent = imx_clk_mux_get_parent, + .set_parent = imx_clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, + .save_context = imx_clk_mux_save_context, + .restore_context = imx_clk_mux_restore_context, +}; + +static void imx_clk_hw_unregister_mux(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + clk_hw_unregister(hw); + kfree(mux); +} + +static struct clk_hw *imx_clk_hw_register_mux(struct device_node *node, + const char *name, + const char * const *parent_names, + u8 num_parents, + unsigned long flags, + struct imx_clk_reg *reg, u8 shift, + u32 mask) +{ + struct clk_init_data init = { NULL }; + struct clk_imx_mux *mux; + struct clk_hw *hw; + + int ret; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_mux_ops; + init.parent_names = parent_names; + init.num_parents = num_parents; + + /* struct clk_mux assignments */ + memcpy(&mux->reg, reg, sizeof(*reg)); + mux->hw.init = &init; + + hw = &mux->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(mux); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_mux_clk_setup() - Setup function for imx mux clock + * @node: device node for the clock + */ +static void __init of_imx_mux_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + unsigned int num_parents; + const char **parent_names; + const char *name = node->name; + struct imx_clk_reg reg = {}; + u32 shift = 0; + u32 flags = CLK_SET_RATE_NO_REPARENT; + u32 val; + u32 mask; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (!IS_ERR(reg.regmap)) { + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + } else { + reg.base = of_iomap(node, 0); + if (IS_ERR(reg.base)) { + pr_err("failed to get register address for %pOFn\n", + node); + return; + } + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%pOFn must have parents\n", node); + return; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return; + + of_clk_parent_fill(node, parent_names, num_parents); + + of_property_read_u32(node, "fsl,bit-shift", &shift); + + if (of_property_read_bool(node, "fsl,is-critical")) + flags |= CLK_IS_CRITICAL; + + if (of_property_read_bool(node, "fsl,ops-parent-enable")) + flags |= CLK_OPS_PARENT_ENABLE; + + if (of_property_read_bool(node, "fsl,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + /* Generate bit-mask based on parent info */ + mask = num_parents - 1; + mask = (1 << fls(mask)) - 1; + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_mux(node, name, parent_names, num_parents, + flags, ®, shift, mask); + if (IS_ERR(hw)) + goto free_parent_names; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_mux(hw); + goto free_parent_names; + } + + pr_debug("name: %s, offset: 0x%x, shift: %d, mask: 0x%x\n", name, + reg.offset, shift, mask); + +free_parent_names: + kfree(parent_names); +} +CLK_OF_DECLARE(fsl_imx8mn_mux_clk, "fsl,imx8mn-mux-clock", + of_imx_mux_clk_setup); From patchwork Sat Dec 31 10:47:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AAF1C3DA7A for ; Sat, 31 Dec 2022 10:48:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231920AbiLaKsH (ORCPT ); Sat, 31 Dec 2022 05:48:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231622AbiLaKsB (ORCPT ); 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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:57 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 05/11] clk: imx8mn: add divider driver Date: Sat, 31 Dec 2022 11:47:30 +0100 Message-Id: <20221231104736.12635-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch adds support for imx8mn divider clocks to be initialized directly from the device tree. Currently all i.MX divider clocks are initialized by legacy code with hardwired parameters. So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-divider.c | 235 ++++++++++++++++++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 drivers/clk/imx/clk-divider.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 1cffc5bebbe1..0e4337f0a020 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -7,6 +7,7 @@ mxc-clk-objs += clk-composite-8m.o mxc-clk-objs += clk-composite-93.o mxc-clk-objs += clk-fracn-gppll.o mxc-clk-objs += clk-cpu.o +mxc-clk-objs += clk-divider.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o mxc-clk-objs += clk-fixup-mux.o diff --git a/drivers/clk/imx/clk-divider.c b/drivers/clk/imx/clk-divider.c new file mode 100644 index 000000000000..4617aa906de4 --- /dev/null +++ b/drivers/clk/imx/clk-divider.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_divider(_hw) container_of(_hw, struct clk_imx_divider, hw) + +struct clk_imx_divider { + struct clk_hw hw; + struct imx_clk_reg reg; + u8 shift; + u8 width; +}; + +static int imx_clk_divider_write(const struct imx_clk_reg *reg, u32 val) +{ + int ret = 0; + + if (reg->base) { + writel(val, reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_write(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static int imx_clk_divider_read(const struct imx_clk_reg *reg, u32 *val) +{ + int ret = 0; + + if (reg->base) { + *val = readl(reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_read(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static unsigned long imx_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + unsigned int val; + int ret; + + ret = imx_clk_divider_read(÷r->reg, &val); + if (ret) + return 0; + + val >>= divider->shift; + val &= clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, NULL, 0, + divider->width); +} + +static long imx_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + return divider_round_rate(hw, rate, prate, NULL, divider->width, 0); +} + +static int imx_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + return divider_determine_rate(hw, req, NULL, divider->width, 0); +} + +static int imx_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + unsigned int val; + int div, ret; + + div = divider_get_val(rate, parent_rate, NULL, divider->width, 0); + if (div < 0) + return div; + + ret = imx_clk_divider_read(÷r->reg, &val); + if (ret) + return ret; + + val &= ~(clk_div_mask(divider->width) << divider->shift); + val |= div << divider->shift; + return imx_clk_divider_write(÷r->reg, val); +} + +const struct clk_ops imx_clk_divider_ops = { + .recalc_rate = imx_clk_divider_recalc_rate, + .round_rate = imx_clk_divider_round_rate, + .determine_rate = imx_clk_divider_determine_rate, + .set_rate = imx_clk_divider_set_rate, +}; + +static void imx_clk_hw_unregister_divider(struct clk_hw *hw) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + clk_hw_unregister(hw); + kfree(divider); +} + +static struct clk_hw *imx_clk_hw_register_divider(struct device_node *node, + const char *name, + unsigned long flags, + struct imx_clk_reg *reg, + u8 shift, u8 width) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; + struct clk_imx_divider *divider; + struct clk_hw *hw; + int ret; + + divider = kzalloc(sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_divider_ops; + init.parent_data = &pdata; + init.num_parents = 1; + + memcpy(÷r->reg, reg, sizeof(*reg)); + divider->shift = shift; + divider->width = width; + divider->hw.init = &init; + + hw = ÷r->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(divider); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_divider_clk_setup() - Setup function for imx gate clock + * @node: device node for the clock + */ +static void __init of_imx_divider_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg reg = {}; + const char *name = node->name; + u8 shift = 0; + u8 width; + u32 flags = 0; + u32 val; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (!IS_ERR(reg.regmap)) { + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + } else { + reg.base = of_iomap(node, 0); + if (IS_ERR(reg.base)) { + pr_err("failed to get register address for %pOFn\n", + node); + return; + } + } + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + shift = val; + + if (of_property_read_u32(node, "fsl,width", &val)) { + pr_err("missing width for %pOFn\n", node); + return; + + } + + width = val; + + if (of_property_read_bool(node, "fsl,ops-parent-enable")) + flags |= CLK_OPS_PARENT_ENABLE; + + if (of_property_read_bool(node, "fsl,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_divider(node, name, flags, ®, shift, width); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_divider(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, shift: %d, width: %d\n", name, + reg.offset, shift, width); +} +CLK_OF_DECLARE(fsl_imx8mn_divider_clk, "fsl,imx8mn-divider-clock", + of_imx_divider_clk_setup); From patchwork Sat Dec 31 10:47:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A57FBC4708E for ; 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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:58 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 06/11] clk: imx: pll14xx: add device tree support Date: Sat, 31 Dec 2022 11:47:31 +0100 Message-Id: <20221231104736.12635-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-pll14xx.c | 220 +++++++++++++++++++++++++++------- 1 file changed, 176 insertions(+), 44 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 828336873a98..6503005b885a 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -12,6 +12,10 @@ #include #include #include +#include +#include +#include +#include #include #include @@ -36,7 +40,9 @@ struct clk_pll14xx { struct clk_hw hw; - void __iomem *base; + struct imx_clk_reg gnrl_ctl; + struct imx_clk_reg div_ctl0; + struct imx_clk_reg div_ctl1; enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; @@ -90,6 +96,30 @@ struct imx_pll14xx_clk imx_1416x_pll = { }; EXPORT_SYMBOL_GPL(imx_1416x_pll); +static void imx_pll14xx_writel(u32 val, const struct imx_clk_reg *reg) +{ + if (reg->base) + writel_relaxed(val, reg->base + reg->offset); + else if (reg->regmap) + regmap_write(reg->regmap, reg->offset, val); + else + pr_err("%s: memory address not set\n", __func__); +} + +static u32 imx_pll14xx_readl(const struct imx_clk_reg *reg) +{ + u32 val = 0; + + if (reg->base) + val = readl_relaxed(reg->base + reg->offset); + else if (reg->regmap) + regmap_read(reg->regmap, reg->offset, &val); + else + pr_err("%s: memory address not set\n", __func__); + + return val; +} + static const struct imx_pll14xx_rate_table *imx_get_pll_settings( struct clk_pll14xx *pll, unsigned long rate) { @@ -161,11 +191,11 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat return; } - pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + pll_div_ctl1 = imx_pll14xx_readl(&pll->div_ctl1); /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */ rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); @@ -249,13 +279,13 @@ static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; - pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); if (pll->type == PLL_1443X) { - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + pll_div_ctl1 = imx_pll14xx_readl(&pll->div_ctl1); kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); } else { kdiv = 0; @@ -277,10 +307,22 @@ static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *ra static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { + struct imx_clk_reg *reg = &pll->gnrl_ctl; u32 val; - return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0, - LOCK_TIMEOUT_US); + if (reg->base) + return readl_poll_timeout(reg->base + reg->offset, val, + val & LOCK_STATUS, 0, + LOCK_TIMEOUT_US); + + if (reg->regmap) + return regmap_read_poll_timeout(reg->regmap, reg->offset, val, + val & LOCK_STATUS, 0, + LOCK_TIMEOUT_US); + + pr_err("%s: memory address not set\n", __func__); + + return -EIO; } static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, @@ -298,32 +340,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + DIV_CTL0); + tmp = imx_pll14xx_readl(&pll->div_ctl0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(tmp, pll->base + DIV_CTL0); + imx_pll14xx_writel(tmp, &pll->div_ctl0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl_relaxed(pll->base + GNRL_CTL); + tmp = imx_pll14xx_readl(&pll->gnrl_ctl); tmp |= LOCK_SEL_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Enable RST */ tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_val, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_val, &pll->div_ctl0); /* * According to SPEC, t3 - t2 need to be greater than @@ -335,7 +377,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -344,7 +386,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); return 0; } @@ -359,35 +401,35 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, imx_pll14xx_calc_settings(pll, drate, prate, &rate); - div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { /* only sdiv and/or kdiv changed - no need to RESET PLL */ div_ctl0 &= ~SDIV_MASK; div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_ctl0, &pll->div_ctl0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), - pll->base + DIV_CTL1); + imx_pll14xx_writel(FIELD_PREP(KDIV_MASK, rate.kdiv), + &pll->div_ctl1); return 0; } /* Enable RST */ - gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL); + gnrl_ctl = imx_pll14xx_readl(&pll->gnrl_ctl); gnrl_ctl &= ~RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); /* Enable BYPASS */ gnrl_ctl |= BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | FIELD_PREP(PDIV_MASK, rate.pdiv) | FIELD_PREP(SDIV_MASK, rate.sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_ctl0, &pll->div_ctl0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + imx_pll14xx_writel(FIELD_PREP(KDIV_MASK, rate.kdiv), &pll->div_ctl1); /* * According to SPEC, t3 - t2 need to be greater than @@ -399,7 +441,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ gnrl_ctl |= RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -408,7 +450,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ gnrl_ctl &= ~BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); return 0; } @@ -423,20 +465,20 @@ static int clk_pll14xx_prepare(struct clk_hw *hw) * RESETB = 1 from 0, PLL starts its normal * operation after lock time */ - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); if (val & RST_MASK) return 0; val |= BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); val |= RST_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); ret = clk_pll14xx_wait_lock(pll); if (ret) return ret; val &= ~BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); return 0; } @@ -446,7 +488,7 @@ static int clk_pll14xx_is_prepared(struct clk_hw *hw) struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 val; - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); return (val & RST_MASK) ? 1 : 0; } @@ -460,9 +502,9 @@ static void clk_pll14xx_unprepare(struct clk_hw *hw) * Set RST to 0, power down mode is enabled and * every digital block is reset */ - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); val &= ~RST_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); } static const struct clk_ops clk_pll1416x_ops = { @@ -487,13 +529,24 @@ static const struct clk_ops clk_pll1443x_ops = { .set_rate = clk_pll1443x_set_rate, }; -struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, - const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) +static void imx_clk_hw_unregister_pll14xx(struct clk_hw *hw) { + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + clk_hw_unregister(hw); + kfree(pll); +} + +static struct clk_hw * +imx_clk_hw_register_pll14xx(struct device_node *node, const char *name, + const char *parent_name, + struct imx_clk_reg *iomap, + const struct imx_pll14xx_clk *pll_clk) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; struct clk_pll14xx *pll; struct clk_hw *hw; - struct clk_init_data init; int ret; u32 val; @@ -503,7 +556,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, init.name = name; init.flags = pll_clk->flags; - init.parent_names = &parent_name; + init.parent_names = parent_name ? &parent_name : NULL; + init.parent_data = &pdata; init.num_parents = 1; switch (pll_clk->type) { @@ -522,19 +576,24 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return ERR_PTR(-EINVAL); } - pll->base = base; + memcpy(&pll->gnrl_ctl, iomap, sizeof(*iomap)); + pll->gnrl_ctl.offset += GNRL_CTL; + memcpy(&pll->div_ctl0, iomap, sizeof(*iomap)); + pll->div_ctl0.offset += DIV_CTL0; + memcpy(&pll->div_ctl1, iomap, sizeof(*iomap)); + pll->div_ctl1.offset += DIV_CTL1; + pll->hw.init = &init; pll->type = pll_clk->type; pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); val &= ~BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); hw = &pll->hw; - - ret = clk_hw_register(dev, hw); + ret = of_clk_hw_register(node, hw); if (ret) { pr_err("failed to register pll %s %d\n", name, ret); kfree(pll); @@ -543,4 +602,77 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } + +struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, + const char *parent_name, void __iomem *base, + const struct imx_pll14xx_clk *pll_clk) +{ + struct imx_clk_reg iomap = {}; + + iomap.base = base; + return imx_clk_hw_register_pll14xx(dev_of_node(dev), name, parent_name, + &iomap, pll_clk); +} EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +/** + * of_imx_pll14xx_clk_setup() - Setup function for imx pll14xx clock + * @node: device node for the clock + */ +static void __init of_imx_pll14xx_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg iomap = {}; + const char *name = node->name; + const struct imx_pll14xx_clk *pll_clk; + const char *pll_type; + u32 val; + + iomap.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (IS_ERR(iomap.regmap)) { + pr_err("missing regmap for %pOFn\n", node); + return; + } + + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + iomap.offset = val; + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + if (of_property_read_string(node, "fsl,type", &pll_type)) { + pr_err("missing 'fsl,type' for %pOFn\n", node); + return; + } + + if (!strcmp(pll_type, "1443x")) { + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + pll_clk = &imx_1443x_dram_pll; + else + pll_clk = &imx_1443x_pll; + } else if (!strcmp(pll_type, "1416x")) { + pll_clk = &imx_1416x_pll; + } else { + pr_err("failed to get pll clock for %pOFn\n", node); + return; + } + + hw = imx_clk_hw_register_pll14xx(node, name, NULL, &iomap, pll_clk); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_pll14xx(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, pll_type: %s\n", name, iomap.offset, + pll_type); +} +CLK_OF_DECLARE(fsl_pll14xx_clk, "fsl,pll14xx-clock", of_imx_pll14xx_clk_setup); From patchwork Sat Dec 31 10:47:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB9E8C46467 for ; Sat, 31 Dec 2022 10:48:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231648AbiLaKsJ (ORCPT ); Sat, 31 Dec 2022 05:48:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231854AbiLaKsD (ORCPT ); Sat, 31 Dec 2022 05:48:03 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 140A9D108 for ; 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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 07/11] clk: imx: composite-8m: add device tree support Date: Sat, 31 Dec 2022 11:47:32 +0100 Message-Id: <20221231104736.12635-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-composite-8m.c | 83 ++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..8c945d180318 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include "clk.h" @@ -25,6 +27,9 @@ #define PCG_CGC_SHIFT 28 +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -250,3 +255,81 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, return ERR_CAST(hw); } EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite); + +static void __init _of_imx_composite_clk_setup(struct device_node *node, + u32 type) +{ + void __iomem *reg; + struct clk_hw *hw; + const char *name = node->name; + unsigned int num_parents; + const char **parent_names; + unsigned long flags = IMX_COMPOSITE_CLK_FLAGS_DEFAULT; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%pOFn must have parents\n", node); + return; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return; + + of_clk_parent_fill(node, parent_names, num_parents); + of_property_read_string(node, "clock-output-names", &name); + + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + flags |= CLK_GET_RATE_NOCACHE; + + if (of_property_read_bool(node, "fsl,is-critical")) + flags |= CLK_IS_CRITICAL; + + hw = __imx8m_clk_hw_composite(name, parent_names, num_parents, reg, + type, flags); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + kfree(parent_names); +} + +/** + * of_imx_composite_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_CORE); +} +CLK_OF_DECLARE(fsl_composite_8m_clk, "fsl,imx8m-composite-clock", + of_imx_composite_clk_setup); + +/** + * of_imx_composite_bus_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_bus_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_BUS); +} +CLK_OF_DECLARE(fsl_composite_bus_8m_clk, "fsl,imx8m-composite-bus-clock", + of_imx_composite_bus_clk_setup); + +/** + * of_imx_composite_fw_managed_clk_setup() - Setup function for imx + * composite fw managed clock + * @node: device node for the clock + */ +void __init of_imx_composite_fw_managed_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_FW_MANAGED); +} +CLK_OF_DECLARE(fsl_composite_fw_managed_8m_clk, + "fsl,imx8m-composite-fw-managed-clock", + of_imx_composite_fw_managed_clk_setup); From patchwork Sat Dec 31 10:47:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56907C3DA7D for ; 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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:01 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 08/11] clk: imx: gate2: add device tree support Date: Sat, 31 Dec 2022 11:47:33 +0100 Message-Id: <20221231104736.12635-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-gate2.c | 86 +++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index f16c4019f402..b28150bf1ff6 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -12,9 +12,26 @@ #include #include #include +#include +#include #include #include "clk.h" +#define CLK_GATE2_CGR_DISABLED 0 +#define CLK_GATE2_CGR_RUN 1 +#define CLK_GATE2_CGR_RUN_WAIT 2 +#define CLK_GATE2_CGR_RUN_WAIT_STOP 3 +#define CLK_GATE2_CGR_MASK 3 + +#define CLK_GATE2_MAX_GROUPS 16 + +struct clk_gate2_group { + const char *name; + unsigned int share_count; +}; + +static struct clk_gate2_group clk_gate2_groups[CLK_GATE2_MAX_GROUPS]; + /** * DOC: basic gateable clock which can gate and ungate its output * @@ -175,3 +192,72 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(clk_hw_register_gate2); + +/** + * of_imx_gate2_clk_setup() - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_gate2_clk_setup(struct device_node *node) +{ + void __iomem *reg; + u8 i, bit_idx = 0; + u8 cgr_val = CLK_GATE2_CGR_RUN_WAIT_STOP; + u8 cgr_mask = CLK_GATE2_CGR_MASK; + unsigned long flags = CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT; + u8 gate2_flags = 0; + unsigned int *share_count = NULL; + const char *name = node->name, *parent_name; + const char *str; + struct clk_hw *hw; + u32 val; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + bit_idx = val; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + if (!of_property_read_string(node, "sharing-group", &str)) { + for (i = 0; clk_gate2_groups[i].name && + i < ARRAY_SIZE(clk_gate2_groups); i++) { + if (!strcmp(clk_gate2_groups[i].name, str)) { + share_count = &clk_gate2_groups[i].share_count; + break; + } + } + + if (i == ARRAY_SIZE(clk_gate2_groups)) { + pr_err("failed to get shared count for %pOFn\n", node); + return; + } + + if (!share_count) { + clk_gate2_groups[i].name = + kstrdup_const(str, GFP_KERNEL); + share_count = &clk_gate2_groups[i].share_count; + } + } + + parent_name = of_clk_get_parent_name(node, 0); + of_property_read_string(node, "clock-output-names", &name); + + hw = clk_hw_register_gate2(NULL, name, parent_name, flags, reg, bit_idx, + cgr_val, cgr_mask, gate2_flags, + &imx_ccm_lock, share_count); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, enable-bit: %d, flags: 0x%lx, gate2_flags: 0x%x\n", + name, parent_name, bit_idx, flags, gate2_flags); +} +CLK_OF_DECLARE(fsl_imx8mn_gate2_clk, "fsl,imx8mn-low-power-gate-clock", + of_imx_gate2_clk_setup); From patchwork Sat Dec 31 10:47:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F5ECC3DA7A for ; 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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:04 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 09/11] clk: imx: cpu: add device tree support Date: Sat, 31 Dec 2022 11:47:34 +0100 Message-Id: <20221231104736.12635-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-cpu.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index cb6ca4cf0535..28fb75c6ecea 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -106,3 +106,57 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, return hw; } EXPORT_SYMBOL_GPL(imx_clk_hw_cpu); + +/** + * of_imx_cpu_clk_setup - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_cpu_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct clk *parent_clk, *div, *mux, *pll, *step; + const char *name = node->name, *parent_name; + + parent_clk = of_clk_get_by_name(node, "fck"); + if (IS_ERR(parent_clk)) { + pr_err("failed to get parent clock for %pOFn\n", node); + return; + } + + div = of_clk_get_by_name(node, "div-clk"); + if (IS_ERR(div)) { + pr_err("failed to get div clock for %pOFn\n", node); + return; + } + + mux = of_clk_get_by_name(node, "mux-clk"); + if (IS_ERR(div)) { + pr_err("failed to get mux clock for %pOFn\n", node); + return; + } + + pll = of_clk_get_by_name(node, "pll-clk"); + if (IS_ERR(div)) { + pr_err("failed to get pll clock for %pOFn\n", node); + return; + } + + step = of_clk_get_by_name(node, "step-clk"); + if (IS_ERR(div)) { + pr_err("failed to get step clock for %pOFn\n", node); + return; + } + + parent_name = __clk_get_name(parent_clk); + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_cpu(name, parent_name, div, mux, pll, step); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, div: %s, mux: %s, pll: %s, step: %s\n", + name, parent_name, __clk_get_name(div), __clk_get_name(mux), + __clk_get_name(pll), __clk_get_name(step)); +} +CLK_OF_DECLARE(fsl_cpu_clk, "fsl,cpu-clock", of_imx_cpu_clk_setup); From patchwork Sat Dec 31 10:47:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DC74C3DA7A for ; Sat, 31 Dec 2022 10:48:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229638AbiLaKsh (ORCPT ); Sat, 31 Dec 2022 05:48:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231946AbiLaKsK (ORCPT ); Sat, 31 Dec 2022 05:48:10 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 178C0E0CC for ; Sat, 31 Dec 2022 02:48:08 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id s5so33552950edc.12 for ; Sat, 31 Dec 2022 02:48:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i4BAr3YDTtam7xHcR497eo7kHS6EX5vNVSsGQ3XZdVg=; b=ROLV5VC2YJKbZIZ4NSupPBjokbyz8XDtxDKZEsyZDegv7Y+nQwgg0Q77od8riAm9pN p43uc2oajTE0nu4DFsjAsTSe9BrclZmI8xi7O8Dl+xMukDXIX+mkHEGyIauIsItG+zUG LxA7cy/5n+BRZ4JdiD2454avSuVEdlMlUP+Js= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i4BAr3YDTtam7xHcR497eo7kHS6EX5vNVSsGQ3XZdVg=; b=NIQrOC/Ah8/FAIOgCkdKNTrKh9RHxnpi+DeBHOhTXG6pjWwJExQMOcYKWoUN9R60TZ XuNqsjfQ8foVVyu8MQ5JCAjYVjYGLAce6KcZ5ab08kRfzMO7dPCAO33QQ2PDAcUg5/K/ 3bKNAUAKMUrsM8SclZg2T/e/RL0W4GmQieTiROfWTIwsMmXQACqlXzSeVxla1833yWg5 kRn2YzbCr5mGWHJBMgbqkMbp3Lu6Ntr8wS2oFH2u7DkrGGjG0FbpbhNVQtU36njLFxeS jesimMDVBEFk5oPPDXWqtWUw1oU2XUGumzrgNncSEZ/Oq2IaMTcwgxsvduakOmnmuZ2x keNg== X-Gm-Message-State: AFqh2koxxYgJ7+T4FyUTaDXwesSqXlksYgfJZaPmf8KaMm1fn1LyrieJ aXysepDzOL398XOdKaxrEsAlFw== X-Google-Smtp-Source: AMrXdXu1wnYLFYK3qlYdujbtgm9DCm5pkd5o4YS26KynkC7DDnX2QN12NN+FZg2mjdguJa8CIhfhog== X-Received: by 2002:a05:6402:f05:b0:45c:834b:f28c with SMTP id i5-20020a0564020f0500b0045c834bf28cmr31101282eda.9.1672483686562; Sat, 31 Dec 2022 02:48:06 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:06 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Adam Ford , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Marek Vasut , Markus Niebel , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 10/11] arm64: dts: imx8mn: add dumy clock Date: Sat, 31 Dec 2022 11:47:35 +0100 Message-Id: <20221231104736.12635-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The dummy clock was the only fixed rate clock not initialized from the device tree. So let's add it to the device tree like we did for the others fixed rate clocks. This is a preparation patch for the upcoming support to setup all the clocks directly from the device tree. Signed-off-by: Dario Binacchi --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +++++++++-- drivers/clk/imx/clk-imx8mn.c | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b7d91df71cc2..1949db3e08f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -217,6 +217,13 @@ clk_ext4: clock-ext4 { clock-output-names = "clk_ext4"; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, <&clk_dummy>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "dummy"; assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index af256ade554f..e1f059dc5afa 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -331,7 +331,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMX8MN_CLK_END; hws = clk_hw_data->hws; - hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_CLK_DUMMY] = imx_get_clk_hw_by_name(np, "dummy"); hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");