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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:35 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v6 01/20] dt-bindings: thermal: tsens: add msm8956 compat Date: Sun, 1 Jan 2023 21:40:15 +0200 Message-Id: <20230101194034.831222-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When adding support for msm8976 it was thought that msm8956 would reuse the same compat. However checking the vendor kernel revealed that these two platforms use different slope values for calculating the calibration data. Add new compatible for the tsens on msm8956 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0231f187b097..f3660af0b3bf 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -37,6 +37,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens - const: qcom,tsens-v1 From patchwork Sun Jan 1 19:40:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4764BC54EBF for ; Sun, 1 Jan 2023 19:40:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229661AbjAATkm (ORCPT ); Sun, 1 Jan 2023 14:40:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230029AbjAATkk (ORCPT ); Sun, 1 Jan 2023 14:40:40 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 828FB10A2 for ; Sun, 1 Jan 2023 11:40:39 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id p36so38872762lfa.12 for ; Sun, 01 Jan 2023 11:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a2R1E7FKbzS0tXOIRc1V3iJlpTV21XWEY+jRsfjYJ6o=; b=InWyEUrJzk066ProOnMp49Vz9975UdgJFUUbYW+HKON5Z5DxI/MqCgC5aT9BY9/Q5o XEvxAK7g6EbBlk/pbW+PhvVdwz2Zes5ipROhsTy8Cc9FQ6vnTngi1rEWF54P3X/CnTQ9 56RHmeSXIpdvP0E3kGVHMCxwsOGu75Ym6XpGRfe4YDOqj8ChWtAuov7AgDl93cer3cYv xQt01gK4kqO0sqrFYZz84dGU2cmzmQxBCpWiSxR1H1BO6srs5S3hqxonDctBffaKYtuq 3zav8/ZIB371UQ4TQ/JAQj3sTrCpElxpbeE/r0veENowiFx/WolRXbDfKS7CAHgm5bAS RGRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a2R1E7FKbzS0tXOIRc1V3iJlpTV21XWEY+jRsfjYJ6o=; b=1QLbstV1pu2TkGDqNuibMGM31GamC8wT+NmN0DXG6nxp1x6I4mA/J6UB0bVVkmolBl wwP/pzrA8Cdit1zMnZeqnv5Cbis7jJJBeswuHly8g3PVIt8evphPeC9IMXJR1vjrQsg/ V4V4iPs8TXzSZhRMwJ6h7B7DpFWKuHRvx0HzWBor83qW80789aAz2259OClD8SZKG6H1 hEInrjpVW1bQ0lDXYCEyn+V9nB3d4wM4mJnk+C07pGYrU0JTJHh93vaEGLebXf/VLc8J evIGgzqHioOyWxOFx3F4iIvXvQJXj55DpHkRzalMiCGHYHwuBVsOO2PQ9D2f1FTAhIfE kK0A== X-Gm-Message-State: AFqh2krei1wL5Hfp15lb6lVcrg6LBbA80yMwMlSZ3zV7biwyhK8IOGvg 7BsGkdj8asYBBlUBO1VtC78K0Q== X-Google-Smtp-Source: AMrXdXvHOiLE8gu/Jk1Zqwmj0Vpx+502enLW0ksTiN+oCaSvNF5lp5Pd2QyGBv1pAlLjo2F8x5GM+Q== X-Received: by 2002:a05:6512:22c3:b0:4b5:76a2:8ad4 with SMTP id g3-20020a05651222c300b004b576a28ad4mr12009564lfu.0.1672602037889; Sun, 01 Jan 2023 11:40:37 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 02/20] dt-bindings: thermal: tsens: support per-sensor calibration cells Date: Sun, 1 Jan 2023 21:40:16 +0200 Message-Id: <20230101194034.831222-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow specifying the exact calibration mode and calibration data as nvmem cells, rather than specifying just a single calibration data blob. Note, unlike the vendor kernel the calibration data uses hw_ids rather than software sensor indices (to match actual tsens usage in thermal zones). Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/thermal/qcom-tsens.yaml | 94 +++++++++++++++++-- 1 file changed, 84 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index f3660af0b3bf..878e1d1bf6c5 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -81,18 +81,62 @@ properties: maxItems: 2 nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Reference to an nvmem node for the calibration data + oneOf: + - minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + - minItems: 5 + maxItems: 35 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor nvmem-cell-names: - minItems: 1 - items: - - const: calib - - enum: - - calib_backup - - calib_sel + oneOf: + - minItems: 1 + items: + - const: calib + - enum: + - calib_backup + - calib_sel + - minItems: 5 + items: + - const: mode + - const: base1 + - const: base2 + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' "#qcom,sensors": description: @@ -221,6 +265,36 @@ examples: }; }; + - | + #include + // Example 1 (new calbiration data: for pre v1 IP): + thermal-sensor@900000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; + + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + - | #include // Example 1 (legacy: for pre v1 IP): From patchwork Sun Jan 1 19:40:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6444BC54EF0 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:38 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v6 03/20] dt-bindings: thermal: tsens: add per-sensor cells for msm8974 Date: Sun, 1 Jan 2023 21:40:17 +0200 Message-Id: <20230101194034.831222-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The msm8974 platform uses two sets of calibration data, add a special case to handle both of them. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-tsens.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 878e1d1bf6c5..926e9c51c93c 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -91,6 +91,11 @@ properties: description: | Reference to nvmem cells for the calibration mode, two calibration bases and two cells per each sensor + # special case for msm8974 / apq8084 + - maxItems: 51 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor, main and backup copies, plus use_backup cell nvmem-cell-names: oneOf: @@ -137,6 +142,59 @@ properties: - pattern: '^s[0-9]+_p2$' - pattern: '^s[0-9]+_p1$' - pattern: '^s[0-9]+_p2$' + # special case for msm8974 / apq8084 + - items: + - const: mode + - const: base1 + - const: base2 + - const: use_backup + - const: mode_backup + - const: base1_backup + - const: base2_backup + - const: s0_p1 + - const: s0_p2 + - const: s1_p1 + - const: s1_p2 + - const: s2_p1 + - const: s2_p2 + - const: s3_p1 + - const: s3_p2 + - const: s4_p1 + - const: s4_p2 + - const: s5_p1 + - const: s5_p2 + - const: s6_p1 + - const: s6_p2 + - const: s7_p1 + - const: s7_p2 + - const: s8_p1 + - const: s8_p2 + - const: s9_p1 + - const: s9_p2 + - const: s10_p1 + - const: s10_p2 + - const: s0_p1_backup + - const: s0_p2_backup + - const: s1_p1_backup + - const: s1_p2_backup + - const: s2_p1_backup + - const: s2_p2_backup + - const: s3_p1_backup + - const: s3_p2_backup + - const: s4_p1_backup + - const: s4_p2_backup + - const: s5_p1_backup + - const: s5_p2_backup + - const: s6_p1_backup + - const: s6_p2_backup + - const: s7_p1_backup + - const: s7_p2_backup + - const: s8_p1_backup + - const: s8_p2_backup + - const: s9_p1_backup + - const: s9_p2_backup + - const: s10_p1_backup + - const: s10_p2_backup "#qcom,sensors": description: From patchwork Sun Jan 1 19:40:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BFA5C46467 for ; Sun, 1 Jan 2023 19:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230281AbjAATkn (ORCPT ); Sun, 1 Jan 2023 14:40:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229955AbjAATkm (ORCPT ); Sun, 1 Jan 2023 14:40:42 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C14E1082 for ; Sun, 1 Jan 2023 11:40:41 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id m6so28506508lfj.11 for ; Sun, 01 Jan 2023 11:40:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4MW0phKWlXpbBUcPLtblyJtyFj83QhXQn2uWltgLH9s=; b=K/vMnmFPEoP693iqYSFlxNIFxirPcbw/wqqmBE3eLksb2iOhBj7PB6WwPLMi6zuY3j EQ+wE+I9IekjASLCIrvnOixGz0qi0uucyu/KRXEcm6LvM/fYo7AxlH4X1QkGgmmPAP0+ tTJPZdmzWhUqd7bRBgu8rTXHfbbh+5j1iwhZkr5NaFjOTrl1+Byx9p/1k1Hebfc77jo5 3Gkv9+g/xbeL27fd1DyHoWs42mZoWk3pb7pRLpKAolnaFc6uBzW8IlbL61R0gG6TFWz6 TSceKqzASE976cZ1AKM1sYtxvXRjjwDoK6qJ4HcWcRz7TDDP2If9KGWAjxgyscTwt1Ob 800Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4MW0phKWlXpbBUcPLtblyJtyFj83QhXQn2uWltgLH9s=; b=LZJQzKicCIe171cLQ1zuEyc2GWp1HHt/+mQyiiTVHfNkfio62JtAK0LT4uuoFeH9kV 5IuqeUHIq6Pe5UII8SJPeftiQLu+OsP9Rot/zYaQlJpkn/RNJUZfid03/M5YfwbsO9dj MIKHCInk/QllAR2/dUz+43HewzHcAn45vtT8iVTUV7vpjvTUMnxaePnUmlEavc60PIbn v+afb7REChQjJ6zRZeOYp/KSr2PQ4qZxfQ3hZ0spmmSc0dig6qosc6B1k+TlDecLhnIP XBxzQxfAwg4IF2QZuVnAmVIl75XMv9DyhtMEOhB3p7B0i0geMpDw1nDs/d0558F7rwWd QUug== X-Gm-Message-State: AFqh2kooDyCKVw4QV1q/TH6FTSSC8N9Xhl3849IqoTC8lRvIdNylOWdb U4w0mmv+zwKXkG/Aha0p+BiG3g== X-Google-Smtp-Source: AMrXdXt2u58LDrUIgeOWm0spBNs/KsvzM4h25a2A/aKFETYpr5/ckl0VmDfJM/EOHSYQMfyve4jQ4Q== X-Received: by 2002:a05:6512:3a8f:b0:4c8:5f19:ccb8 with SMTP id q15-20020a0565123a8f00b004c85f19ccb8mr11769465lfu.48.1672602039566; Sun, 01 Jan 2023 11:40:39 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:39 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 04/20] thermal/drivers/tsens: Drop unnecessary hw_ids Date: Sun, 1 Jan 2023 21:40:18 +0200 Message-Id: <20230101194034.831222-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The tsens driver defaults to using hw_id equal to the index of the sensor. Thus it is superfluous to declare such hw_id arrays. Drop such arrays from mdm9607 and msm8976 data. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 1 - drivers/thermal/qcom/tsens-v1.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 04d012e4f728..0bc4e5cec184 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -635,7 +635,6 @@ static const struct tsens_ops ops_9607 = { struct tsens_plat_data data_9607 = { .num_sensors = 5, .ops = &ops_9607, - .hw_ids = (unsigned int []){ 0, 1, 2, 3, 4 }, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, }; diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 1d7f8a80bd13..96ef12d47bff 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -387,7 +387,6 @@ static const struct tsens_ops ops_8976 = { struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, - .hw_ids = (unsigned int[]){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; From patchwork Sun Jan 1 19:40:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 195EBC63705 for ; Sun, 1 Jan 2023 19:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230188AbjAATkp (ORCPT ); Sun, 1 Jan 2023 14:40:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230201AbjAATkn (ORCPT ); Sun, 1 Jan 2023 14:40:43 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37E9210AF for ; Sun, 1 Jan 2023 11:40:42 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id bf43so38893209lfb.6 for ; Sun, 01 Jan 2023 11:40:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FlcwXoa9Z1Zub33BGG0XBB+zLvZVGpO/Coytg4v1lJY=; b=SDqkxDlDL+GygwSeARvDRp57SXFiWrze7Y1D45ROj0ydxpgybJT87aIiDonEsVDkRs 2pDlPlbz18w1BuuqLs31QhP0VGVOCkVMsu21sWM0UqBdhwJCX2etdBUFWBYEuF0WzlZW lWSopJVw2WRmqvnK4y/14eSbZ+bSFj12u7t72HNN++frkHnTqt7uF0ymaTZvfc9EGeiS 3JgefkbmItiPSApDZ1Y+ZRFXeooWA4DI/5a6qFtoAAg9dU+KcfJvZVw2n01kmxmcxJFX NiGKBOL9HHj41+RPhN1afljQ+0mmrFQOA3MqhCLSrHa7XGeH08o9trJwJ1qFaETi71UO Ir5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FlcwXoa9Z1Zub33BGG0XBB+zLvZVGpO/Coytg4v1lJY=; b=Fb+g3MkiERnJqK38z824yS44sFB5+WrQGN+6GqR9RNMieYlbVMhZmqE5fJRA031y7p fECQdDkG0cllMRDSjtUm5psmxSNOpr7XHmeTPdnkh0v3E7sBixN1M++0I36+sVoHavTu /S7Z1zuP8UpvOqMuiyYmAMUWdq62xlNj65JqyrutY7xsxnk4RYjkHJEhaiOr/3hnOSlu X9sRvGxFC1ucM7aF5WvhwH8nZHCNRMH1Qr+BuP+idFOl30NvooAQVFueysUfxs+2SPLZ L0em6HImYgT+gU/Puy+O5wLSPQUk3Bx45533ni2nk/EhLMzIPmAk3hkKrFp9E3Xdj51u +0Nw== X-Gm-Message-State: AFqh2kpRX11phmWxri37LIDHyJdVYZarVonMQMvxcI0tQtayWqtHepuJ +SCu+Eaz/C1hmJXK796WBpWi5g== X-Google-Smtp-Source: AMrXdXvV6q1pi6fVP69X0degnRtUtgfPef8Z4BiP2r24SThja+jtExZwCox096GQWwYjJV7PsgNH9w== X-Received: by 2002:a05:6512:21c6:b0:4b5:83b8:2c49 with SMTP id d6-20020a05651221c600b004b583b82c49mr10173890lft.1.1672602040577; Sun, 01 Jan 2023 11:40:40 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:40 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v6 05/20] thermal/drivers/tsens: Drop msm8976-specific defines Date: Sun, 1 Jan 2023 21:40:19 +0200 Message-Id: <20230101194034.831222-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop msm8976-specific defines, which duplicate generic ones. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 96ef12d47bff..a7f53966156b 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -78,11 +78,6 @@ #define MSM8976_CAL_SEL_MASK 0x3 -#define MSM8976_CAL_DEGC_PT1 30 -#define MSM8976_CAL_DEGC_PT2 120 -#define MSM8976_SLOPE_FACTOR 1000 -#define MSM8976_SLOPE_DEFAULT 3200 - /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -160,8 +155,8 @@ static void compute_intercept_slope_8976(struct tsens_priv *priv, priv->sensor[10].slope = 3286; for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) - - (MSM8976_CAL_DEGC_PT1 * + priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - + (CAL_DEGC_PT1 * priv->sensor[i].slope); } } From patchwork Sun Jan 1 19:40:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78E62C54E76 for ; Sun, 1 Jan 2023 19:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231617AbjAATk5 (ORCPT ); Sun, 1 Jan 2023 14:40:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231318AbjAATks (ORCPT ); Sun, 1 Jan 2023 14:40:48 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0998010E2 for ; Sun, 1 Jan 2023 11:40:43 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id f34so38853537lfv.10 for ; Sun, 01 Jan 2023 11:40:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H+QyReNeKQ7VChfSL5c4X0M1KNpysUipua99JNIB2DI=; b=kjkiBXtyWNd/HybSMFlvQ3+bLJel7+AOdDzcLs0zuWzT+XsR0MTk6QgitEHceeig6n X/MBjcAEj10JkMfT1ndcGrwU+LVrHV2+vijOhxGjIjp6TTTc0JminSGAS4SyJi0rZHr/ CGo46JN39vyERjWqLFE8+GdEK0pU7pOA9CWR0XFtr4YYwgi10ny87i/n3mViCVTp4yjl zHBEC+1a5ZxfKd7JUS6R+6zIJTf5L9rP7guq4UdQgARPCES9cZPvsgG3pgiBGwr4jbpr j85IgDsjwv2x2UqL4VfYeB5BQ49ve+2YvmVfbmT1ytkEXRAkTU/QKAhugY+kF3ERLgJH exRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H+QyReNeKQ7VChfSL5c4X0M1KNpysUipua99JNIB2DI=; b=Ls1q5ckdtWy16VcqrhOuGpryqTC1Jb9B/+w9csRfQekKdMKtiEg+d0px54ZPRZsyiJ QiFDnCM1FRLYYnlWLs4308vpRZqFh1kX/j/bitWuNT/895dkXPw/D6QD3w+oYmtliMa0 BYZm5erQayAMXrFJ9ucA4F+UAd5437nCjB6AFDNGdjCBJ3ioPft+5XUUXwkcWcRIpbXL 2jydxSXhssRte1GuhXOyo/GgI+WUG/lT+P38hkEqSwF56mB+bRFH8GEb2NtjACZyXXrD Bx9kuLJgvHFuP/o1zsL8iC/FqimMSUQ9y3ehoi8MCZabe3wG9wx4nB01yJo/iQpwdX4D rUVA== X-Gm-Message-State: AFqh2kqJUwU8G/KGKhcaC2SsJwpnz0t9wU4Uk/bECiEIhtnEJXawGEwF CXfeOIk6OKjZjQD/la663w8TiA== X-Google-Smtp-Source: AMrXdXtCRZ1tvIzmUTXEI03LgsxKCO8RWTE4LM7KFgc63Ns9t2p+NvKdtUDEj1290/Q0rkaMpWnRsQ== X-Received: by 2002:a05:6512:3d1f:b0:4a4:68b8:f4d0 with SMTP id d31-20020a0565123d1f00b004a468b8f4d0mr12341737lfv.22.1672602041392; Sun, 01 Jan 2023 11:40:41 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:40 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v6 06/20] thermal/drivers/tsens: Sort out msm8976 vs msm8956 data Date: Sun, 1 Jan 2023 21:40:20 +0200 Message-Id: <20230101194034.831222-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Tsens driver mentions that msm8976 data should be used for both msm8976 and msm8956 SoCs. This is not quite correct, as according to the vendor kernels, msm8976 should use standard slope values (3200), while msm8956 really uses the slope values found in the driver. Add separate compatibility string for msm8956, move slope value overrides to the corresponding init function and use the standard compute_intercept_slope() function for both platforms. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Cc: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 56 ++++++++++++++++++--------------- drivers/thermal/qcom/tsens.c | 3 ++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a7f53966156b..83c2853546d0 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -137,30 +137,6 @@ #define CAL_SEL_MASK 7 #define CAL_SEL_SHIFT 0 -static void compute_intercept_slope_8976(struct tsens_priv *priv, - u32 *p1, u32 *p2, u32 mode) -{ - int i; - - priv->sensor[0].slope = 3313; - priv->sensor[1].slope = 3275; - priv->sensor[2].slope = 3320; - priv->sensor[3].slope = 3246; - priv->sensor[4].slope = 3279; - priv->sensor[5].slope = 3257; - priv->sensor[6].slope = 3234; - priv->sensor[7].slope = 3269; - priv->sensor[8].slope = 3255; - priv->sensor[9].slope = 3239; - priv->sensor[10].slope = 3286; - - for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - - (CAL_DEGC_PT1 * - priv->sensor[i].slope); - } -} - static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -286,7 +262,7 @@ static int calibrate_8976(struct tsens_priv *priv) break; } - compute_intercept_slope_8976(priv, p1, p2, mode); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); return 0; @@ -360,6 +336,22 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int __init init_8956(struct tsens_priv *priv) { + priv->sensor[0].slope = 3313; + priv->sensor[1].slope = 3275; + priv->sensor[2].slope = 3320; + priv->sensor[3].slope = 3246; + priv->sensor[4].slope = 3279; + priv->sensor[5].slope = 3257; + priv->sensor[6].slope = 3234; + priv->sensor[7].slope = 3269; + priv->sensor[8].slope = 3255; + priv->sensor[9].slope = 3239; + priv->sensor[10].slope = 3286; + + return init_common(priv); +} + static const struct tsens_ops ops_generic_v1 = { .init = init_common, .calibrate = calibrate_v1, @@ -372,13 +364,25 @@ struct tsens_plat_data data_tsens_v1 = { .fields = tsens_v1_regfields, }; +static const struct tsens_ops ops_8956 = { + .init = init_8956, + .calibrate = calibrate_8976, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8956 = { + .num_sensors = 11, + .ops = &ops_8956, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; + static const struct tsens_ops ops_8976 = { .init = init_common, .calibrate = calibrate_8976, .get_temp = get_temp_tsens_valid, }; -/* Valid for both MSM8956 and MSM8976. */ struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5b136ff323f..b191e19df93d 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -983,6 +983,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8939-tsens", .data = &data_8939, + }, { + .compatible = "qcom,msm8956-tsens", + .data = &data_8956, }, { .compatible = "qcom,msm8960-tsens", .data = &data_8960, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 899af128855f..7dd5fc246894 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -594,7 +594,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; From patchwork Sun Jan 1 19:40:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52CD0C5479D for ; Sun, 1 Jan 2023 19:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231593AbjAATkw (ORCPT ); Sun, 1 Jan 2023 14:40:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231180AbjAATkr (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:41 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 07/20] thermal/drivers/tsens: fix slope values for msm8939 Date: Sun, 1 Jan 2023 21:40:21 +0200 Message-Id: <20230101194034.831222-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to the vendor kernels (msm-3.10, 3.14 and 3.18), msm8939 uses non-standard slope values for calibrating the sensors. Fill them accordingly. Fixes: 332bc8ebab2c ("thermal: qcom: tsens-v0_1: Add support for MSM8939") Cc: Bryan O'Donoghue Cc: Shawn Guo Reviewed-by: Konrad Dybcio Acked-by: Shawn Guo Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue --- drivers/thermal/qcom/tsens-v0_1.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 0bc4e5cec184..6645c98ff56c 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -534,6 +534,21 @@ static int calibrate_9607(struct tsens_priv *priv) return 0; } +static int __init init_8939(struct tsens_priv *priv) { + priv->sensor[0].slope = 2911; + priv->sensor[1].slope = 2789; + priv->sensor[2].slope = 2906; + priv->sensor[3].slope = 2763; + priv->sensor[4].slope = 2922; + priv->sensor[5].slope = 2867; + priv->sensor[6].slope = 2833; + priv->sensor[7].slope = 2838; + priv->sensor[8].slope = 2840; + priv->sensor[9].slope = 2852; + + return init_common(priv); +} + /* v0.1: 8916, 8939, 8974, 9607 */ static struct tsens_features tsens_v0_1_feat = { @@ -599,7 +614,7 @@ struct tsens_plat_data data_8916 = { }; static const struct tsens_ops ops_8939 = { - .init = init_common, + .init = init_8939, .calibrate = calibrate_8939, .get_temp = get_temp_common, }; From patchwork Sun Jan 1 19:40:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A07A1C5479D for ; Sun, 1 Jan 2023 19:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231464AbjAATkt (ORCPT ); Sun, 1 Jan 2023 14:40:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230424AbjAATkq (ORCPT ); Sun, 1 Jan 2023 14:40:46 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 622EB10F1 for ; Sun, 1 Jan 2023 11:40:43 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id bq39so31102702lfb.0 for ; Sun, 01 Jan 2023 11:40:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GJJvPLhDlr0mcMF02RxftzoZxCEBah7KzEF7SzcrMSo=; b=D1kALFWycy5Ln/j5PvZz9aaPQs/dHiRUPXswMEZ7TPYVVriOh0PnzkbVNt4l4eIjqE ulX/kVxB1OSmlOTz6DLHcfzrEg2lKAOVW3L3CXKQz1bSttC4at6u1wcZfxsU6HRVHhVv k1EBZ178n0RpmA6qxXfyiG16ONMwDXyMe7+lX+BEneWLOm40+UBeZwYQUAzaXW42IH+x ONeMmh7BGHWlVCCY0ODsBBXFS8MpUaWRsHwJASYNJZi4kdklHBGYsFb0nEBqNqJNwCfc tInzUSAMFAEmYRgB9zQ9PsUOiD9YLThbElTY0cBANJ1cM8pjGyfh5cfpuMJ3YcDhVGem 1R2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GJJvPLhDlr0mcMF02RxftzoZxCEBah7KzEF7SzcrMSo=; b=xgOuyUKCb8SmWY7SO1sCkm+5jA6kRKH9ZInlckhQJX+DhnvUVPS5BMqwdg1baT5PLq jQ/mnsFOj/rZnE7KSeKdWbJyA1ipR7qnpzXhuC6XgzkSDDKEDrcR/ghBvXO8+uJ25zdD +oWf4k5cXLfaClspy1MfseYFySX3rtxkLK3Pa3Qtpiz+9pyqJbuw1q3TodM5wZesI8sD E1CRq5Vl0R4sWpGikElFdcLqOIRt6X8ZVrKFecYpgOMa9bVCR3oiyEWiJ2wx6m1R8Ykw ZpeRNpcZj2PW0r5Zo+J/KxbjF7Jy2ViQVPQiBcgEeRYGSJvdyz69p/OySFDqKujdgO2O 5SlA== X-Gm-Message-State: AFqh2kp95K0WQKxRlbX11ahG0r9C9ksxDZvNZaRmlaBIpc3nYmTLsdaM 1Q9d9DnDggTpv/BWrPqFn64NfQ== X-Google-Smtp-Source: AMrXdXsZT1TKVpVkVnw1pxFqvpcR27kL8UM0hDlbbUVoY4pSkZpBty0hYEou/QaXFBWxnOkOEXfFzA== X-Received: by 2002:a05:6512:3f26:b0:4a4:68b9:66bf with SMTP id y38-20020a0565123f2600b004a468b966bfmr12811732lfa.10.1672602042943; Sun, 01 Jan 2023 11:40:42 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:42 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 08/20] thermal/drivers/tsens: limit num_sensors to 9 for msm8939 Date: Sun, 1 Jan 2023 21:40:22 +0200 Message-Id: <20230101194034.831222-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On msm8939 last (hwid=10) sensor was added in the hw revision 3.0. Calibration data for it was placed outside of the main calibration data blob, so it is not accessible by the current blob-parsing code. Moreover data for the sensor's p2 is not contiguous in the fuses. This makes it hard to use nvmem_cell API to parse calibration data in a generic way. Since the sensor doesn't seem to be actually used by the existing hardware, disable the sensor for now. Fixes: 332bc8ebab2c ("thermal: qcom: tsens-v0_1: Add support for MSM8939") Cc: Bryan O'Donoghue Cc: Shawn Guo Acked-by: Shawn Guo Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue --- drivers/thermal/qcom/tsens-v0_1.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6645c98ff56c..579028ea48f4 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -285,7 +285,7 @@ static int calibrate_8939(struct tsens_priv *priv) u32 p1[10], p2[10]; int mode = 0; u32 *qfprom_cdata; - u32 cdata[6]; + u32 cdata[4]; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -296,8 +296,6 @@ static int calibrate_8939(struct tsens_priv *priv) cdata[1] = qfprom_cdata[13]; cdata[2] = qfprom_cdata[0]; cdata[3] = qfprom_cdata[1]; - cdata[4] = qfprom_cdata[22]; - cdata[5] = qfprom_cdata[21]; mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT; dev_dbg(priv->dev, "calibration mode is %d\n", mode); @@ -314,8 +312,6 @@ static int calibrate_8939(struct tsens_priv *priv) p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT; p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT; p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT; - p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4; - p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5; for (i = 0; i < priv->num_sensors; i++) p2[i] = (base1 + p2[i]) << 2; fallthrough; @@ -331,7 +327,6 @@ static int calibrate_8939(struct tsens_priv *priv) p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT; p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT; p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT; - p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT; for (i = 0; i < priv->num_sensors; i++) p1[i] = ((base0) + p1[i]) << 2; break; @@ -544,7 +539,7 @@ static int __init init_8939(struct tsens_priv *priv) { priv->sensor[6].slope = 2833; priv->sensor[7].slope = 2838; priv->sensor[8].slope = 2840; - priv->sensor[9].slope = 2852; + /* priv->sensor[9].slope = 2852; */ return init_common(priv); } @@ -620,9 +615,9 @@ static const struct tsens_ops ops_8939 = { }; struct tsens_plat_data data_8939 = { - .num_sensors = 10, + .num_sensors = 9, .ops = &ops_8939, - .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 }, + .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, /* 10 */ }, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, From patchwork Sun Jan 1 19:40:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 207F9C3DA7D for ; Sun, 1 Jan 2023 19:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231580AbjAATkv (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:43 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 09/20] thermal/drivers/tsens: Support using nvmem cells for calibration data Date: Sun, 1 Jan 2023 21:40:23 +0200 Message-Id: <20230101194034.831222-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a unified function using nvmem cells for parsing the calibration data rather than parsing the calibration blob manually. Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 15 ++++++ drivers/thermal/qcom/tsens-v1.c | 11 ++++- drivers/thermal/qcom/tsens.c | 76 +++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 5 ++ 4 files changed, 106 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 579028ea48f4..6c9e491f9559 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -229,6 +229,11 @@ static int calibrate_8916(struct tsens_priv *priv) u32 p1[5], p2[5]; int mode = 0; u32 *qfprom_cdata, *qfprom_csel; + int ret; + + ret = tsens_calibrate_nvmem(priv, 3); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -286,6 +291,11 @@ static int calibrate_8939(struct tsens_priv *priv) int mode = 0; u32 *qfprom_cdata; u32 cdata[4]; + int ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -486,6 +496,11 @@ static int calibrate_9607(struct tsens_priv *priv) u32 p1[5], p2[5]; int mode = 0; u32 *qfprom_cdata; + int ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 83c2853546d0..5bba75a845c5 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -143,7 +143,11 @@ static int calibrate_v1(struct tsens_priv *priv) u32 p1[10], p2[10]; u32 mode = 0, lsb = 0, msb = 0; u32 *qfprom_cdata; - int i; + int i, ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -209,6 +213,11 @@ static int calibrate_8976(struct tsens_priv *priv) u32 p1[11], p2[11]; int mode = 0, tmp = 0; u32 *qfprom_cdata; + int ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b191e19df93d..ce568a68de4a 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -70,6 +70,82 @@ char *qfprom_read(struct device *dev, const char *cname) return ret; } +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +{ + u32 mode; + u32 base1, base2; + u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; + char name[] = "sXX_pY"; /* s10_p1 */ + int i, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base2", &base2); + if (ret < 0) + return ret; + + for (i = 0; i < priv->num_sensors; i++) { + ret = snprintf(name, sizeof(name), "s%d_p1", priv->sensor[i].hw_id); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p1[i]); + if (ret) + return ret; + + ret = snprintf(name, sizeof(name), "s%d_p2", priv->sensor[i].hw_id); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p2[i]); + if (ret) + return ret; + } + + switch (mode) { + case ONE_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = p1[i] + (base1 << shift); + break; + case TWO_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p2[i] = (p2[i] + base2) << shift; + fallthrough; + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (p1[i] + base1) << shift; + break; + default: + dev_dbg(priv->dev, "calibrationless mode\n"); + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + +int tsens_calibrate_common(struct tsens_priv *priv) +{ + return tsens_calibrate_nvmem(priv, 2); +} + /* * Use this function on devices where slope and offset calculations * depend on calibration data read from qfprom. On others the slope diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 7dd5fc246894..645ae02438fa 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -6,6 +6,7 @@ #ifndef __QCOM_TSENS_H__ #define __QCOM_TSENS_H__ +#define NO_PT_CALIB 0x0 #define ONE_PT_CALIB 0x1 #define ONE_PT_CALIB2 0x2 #define TWO_PT_CALIB 0x3 @@ -17,6 +18,8 @@ #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 +#define MAX_SENSORS 16 + #include #include #include @@ -582,6 +585,8 @@ struct tsens_priv { }; char *qfprom_read(struct device *dev, const char *cname); +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); +int tsens_calibrate_common(struct tsens_priv *priv); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp); From patchwork Sun Jan 1 19:40:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62F06C53210 for ; Sun, 1 Jan 2023 19:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231609AbjAATkx (ORCPT ); Sun, 1 Jan 2023 14:40:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231247AbjAATkr (ORCPT ); Sun, 1 Jan 2023 14:40:47 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F86018B for ; Sun, 1 Jan 2023 11:40:45 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id j17so29401665lfr.3 for ; Sun, 01 Jan 2023 11:40:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bqICWi6TbRJ1t8BdhHT518ktWAE9yqx7ZrlpL4AUbPY=; b=tyMerOVf8yYtBLxZekiae+ryJeQ+4WTJ5318fzJa314kOSSTpEO3yhELJsePY4Emft pPd1Y+pgxJpY5u9VyL7PLiWpdPm/u0fCErczI4ixi/IZgjCdutDQZCaGzjvU6O+mzWSH 08e6Sy57h+Jx5rBZoNiWTZHvyFExwBqQFk6I0n9mLLzEC5Onnt8WEIJkGEKe5cgam6du 6MjcYti3E90Tfp0eHLQ2mFKvYzx9K8mdByUrjJnIqoAtqjAhBc58KMOWrw9fHhoOMPaU ZkheuBTjNjv/NHM+E4lSo7KvlBjx7AAlY7rLddsdCrXUtoX7Ul4G4E4bd39NuyN29MP6 FBSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bqICWi6TbRJ1t8BdhHT518ktWAE9yqx7ZrlpL4AUbPY=; b=oVbPeHYRPs6HcsfX62J7fyww8JU5JkQK9kgQCYPITjzv4XXH0btJTTUPjUdLuYVqsd NiJu7aS1y9oRyWhycExbzYLNNxX+kc95A3px2LvTRTGPxfme4dydmvhe4nENOqisBhVi Hb2c3YT3NaGYjFPViSrFWe6HO/PqwtfAyof/DkwS1nw6tWWQNbOdKH8+7kZQoAWrwmQR 1Csxq5Fg8HT9Z8SYpSa7LT4zgBUJslUfhwkzKmfLrpXYaX/OjU+w9tvSyghu9yJ1PXnU 5QtiyfUVAI1eRDuqzOCNATlo6/aul46B6hAYUGjBWnoYE41zlwnnwI826tBNHbDhfn3N vCvw== X-Gm-Message-State: AFqh2kqCOLyFlZwwv+2ZnwMZRZgHT0o15g3UWC3xUdU53jzHPlG84TAr VvZHuoplVgPbOEIOgnSYst3uTw== X-Google-Smtp-Source: AMrXdXv3k5t6OiQlGkhgs+fMBeP9hlSDHbnFg6srgK45vSYDxcpbeboWk/x5DtkVVb5qXWIDPnvHyQ== X-Received: by 2002:ac2:498f:0:b0:4a4:86ff:9562 with SMTP id f15-20020ac2498f000000b004a486ff9562mr11805458lfl.38.1672602044701; Sun, 01 Jan 2023 11:40:44 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:44 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 10/20] thermal/drivers/tsens: Support using nvmem cells for msm8974 calibration Date: Sun, 1 Jan 2023 21:40:24 +0200 Message-Id: <20230101194034.831222-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8974 has two sets of calibration data: main one and backup. Add support for parsing both sets of calibration data from nvmem cells. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 50 +++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 41 ++++++++++++++++++++----- drivers/thermal/qcom/tsens.h | 1 + 3 files changed, 84 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6c9e491f9559..3c08ad640940 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include "tsens.h" @@ -354,6 +355,50 @@ static int calibrate_8939(struct tsens_priv *priv) return 0; } +static int calibrate_8974_nvmem(struct tsens_priv *priv) +{ + int i, ret, mode; + u32 p1[11], p2[11]; + u32 backup; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "use_backup", &backup); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + mode = tsens_read_calibration(priv, 2, p1, p2, backup == BKP_SEL); + if (mode < 0) + return mode; + + if (mode == NO_PT_CALIB) { + p1[0] += 2; + p1[1] += 9; + p1[2] += 3; + p1[3] += 9; + p1[4] += 5; + p1[5] += 9; + p1[6] += 7; + p1[7] += 10; + p1[8] += 8; + p1[9] += 9; + p1[10] += 8; + } else { + for (i = 0; i < priv->num_sensors; i++) { + /* + * ONE_PT_CALIB requires using addition here instead of + * using OR operation. + */ + p1[i] += BIT_APPEND; + p2[i] += BIT_APPEND; + } + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + static int calibrate_8974(struct tsens_priv *priv) { int base1 = 0, base2 = 0, i; @@ -361,6 +406,11 @@ static int calibrate_8974(struct tsens_priv *priv) int mode = 0; u32 *calib, *bkp; u32 calib_redun_sel; + int ret; + + ret = calibrate_8974_nvmem(priv); + if (ret == 0) + return 0; calib = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(calib)) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index ce568a68de4a..6facdb0246a5 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -70,18 +70,21 @@ char *qfprom_read(struct device *dev, const char *cname) return ret; } -int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup) { u32 mode; u32 base1, base2; - u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; - char name[] = "sXX_pY"; /* s10_p1 */ + char name[] = "sXX_pY_backup"; /* s10_p1_backup */ int i, ret; if (priv->num_sensors > MAX_SENSORS) return -EINVAL; - ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + ret = snprintf(name, sizeof(name), "mode%s", backup ? "_backup" : ""); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); if (ret == -ENOENT) dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); if (ret < 0) @@ -89,16 +92,25 @@ int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) dev_dbg(priv->dev, "calibration mode is %d\n", mode); - ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + ret = snprintf(name, sizeof(name), "base1%s", backup ? "_backup" : ""); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); + if (ret < 0) + return ret; + + ret = snprintf(name, sizeof(name), "base2%s", backup ? "_backup" : ""); if (ret < 0) return ret; - ret = nvmem_cell_read_variable_le_u32(priv->dev, "base2", &base2); + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base2); if (ret < 0) return ret; for (i = 0; i < priv->num_sensors; i++) { - ret = snprintf(name, sizeof(name), "s%d_p1", priv->sensor[i].hw_id); + ret = snprintf(name, sizeof(name), "s%d_p1%s", priv->sensor[i].hw_id, + backup ? "_backup" : ""); if (ret < 0) return ret; @@ -106,7 +118,8 @@ int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) if (ret) return ret; - ret = snprintf(name, sizeof(name), "s%d_p2", priv->sensor[i].hw_id); + ret = snprintf(name, sizeof(name), "s%d_p2%s", priv->sensor[i].hw_id, + backup ? "_backup" : ""); if (ret < 0) return ret; @@ -136,6 +149,18 @@ int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) } } + return mode; +} + +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +{ + u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; + int mode; + + mode = tsens_read_calibration(priv, shift, p1, p2, false); + if (mode < 0) + return mode; + compute_intercept_slope(priv, p1, p2, mode); return 0; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 645ae02438fa..a9ae8df9f810 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -585,6 +585,7 @@ struct tsens_priv { }; char *qfprom_read(struct device *dev, const char *cname); +int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup); int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); int tsens_calibrate_common(struct tsens_priv *priv); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); From patchwork Sun Jan 1 19:40:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 832C4C46467 for ; Sun, 1 Jan 2023 19:41:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231422AbjAATlC (ORCPT ); Sun, 1 Jan 2023 14:41:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231298AbjAATkw (ORCPT ); Sun, 1 Jan 2023 14:40:52 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53F17BB1 for ; Sun, 1 Jan 2023 11:40:47 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id j17so29401708lfr.3 for ; Sun, 01 Jan 2023 11:40:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dGyTSulvaKjPEZiY77IpLwagE5A3412rOxjmhJUBt5Q=; b=oVt70NCbf7OMeDFg7FCq282VJYctrKe1QNWkyhhMgo2Mf7vh1cjQTQ9E9ZgeUdit0U JMgsGYxAJ0OKRgeTqE2Rbbl1+8T/B9U9+vqah6zS8C7qbJfBCkyVW3ucYbJV3okWxkD9 2hDLPd3f83G//7MwIcDyYFtSNCeDySzZW0BQD+1pKlcfyq1tnsd0KNwbq4QwLBn9UCum 3yHhlQNiKuJOGAdPZymW9jbNu8VLIZI3Z1nMlft6KCXHbypedZxGglnaBD1EY3uwroSi B17jG/o6/h7opxxLka8A/lAShXQRdrZSgLwNYDTiJ4OnIiLHhnW3rR0XoWJcIvIhSNk6 dzbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGyTSulvaKjPEZiY77IpLwagE5A3412rOxjmhJUBt5Q=; b=rxcMG/3mSNZW9kAsuqXlNTAuT7TxOdL2se6RF/uzoAB8ao3E64YxzKqPwnQi/EOwnw zgNG0VgJhVLOq34WsPzxzIIObCPAmPPjKHR3zGozHQ/cPd6a09qh68+kkMDMHkWuUY6W P9ph0p7i76/PDuCnNfLCR/MmfPJU/dVo4Fx3yrrGcM+PlQbT04bpuomsm7+bOQ1tDNtp lOCsBMUvzSLs6jMnBWBCxW+CiEJP8TioxJ9gtj9XiO+EBM+6UFXePIYRx8/o1oksr7Gi 3qSgxN1qSuSiXIO0zrle5aNajS+L8ge2AWzt9A6goDVDAxtCQUXPD1A9f0LoeKrPejL+ FQtw== X-Gm-Message-State: AFqh2kqWDd8dxP5biAOmZXb7nmAbA+X0jge3wD+WyLEJUO1hEWTIbqGS 1n/hUKcZj/PHvEx1OxvcSl4b4A== X-Google-Smtp-Source: AMrXdXuOU7XrKAbqZ2ERilRoNeVf0zSXM8sExSSK8UbAEoR2ntbJmqT9knskqjkjvYRoXxcpb+xp1g== X-Received: by 2002:a05:6512:150b:b0:4ca:e66e:43c8 with SMTP id bq11-20020a056512150b00b004cae66e43c8mr10692651lfb.14.1672602045515; Sun, 01 Jan 2023 11:40:45 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:45 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, kernel test robot Subject: [PATCH v6 11/20] thermal/drivers/tsens: Rework legacy calibration data parsers Date: Sun, 1 Jan 2023 21:40:25 +0200 Message-Id: <20230101194034.831222-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework existing calibration parsing code to use simple data structure describing data layout. This allows us to drop all the mask & shift values, replacing them with data tables. The code for msm8974 is not reworked, as it has separate calibration and backup data. Reported-by: kernel test robot Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 591 ++++++++---------------------- drivers/thermal/qcom/tsens-v1.c | 266 +++----------- drivers/thermal/qcom/tsens.c | 64 ++++ drivers/thermal/qcom/tsens.h | 38 ++ 4 files changed, 297 insertions(+), 662 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 3c08ad640940..f8b50bf14190 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include "tsens.h" @@ -16,221 +17,113 @@ #define TM_Sn_STATUS_OFF 0x0030 #define TM_TRDY_OFF 0x005c -/* eeprom layout data for 8916 */ -#define MSM8916_BASE0_MASK 0x0000007f -#define MSM8916_BASE1_MASK 0xfe000000 -#define MSM8916_BASE0_SHIFT 0 -#define MSM8916_BASE1_SHIFT 25 - -#define MSM8916_S0_P1_MASK 0x00000f80 -#define MSM8916_S1_P1_MASK 0x003e0000 -#define MSM8916_S2_P1_MASK 0xf8000000 -#define MSM8916_S3_P1_MASK 0x000003e0 -#define MSM8916_S4_P1_MASK 0x000f8000 - -#define MSM8916_S0_P2_MASK 0x0001f000 -#define MSM8916_S1_P2_MASK 0x07c00000 -#define MSM8916_S2_P2_MASK 0x0000001f -#define MSM8916_S3_P2_MASK 0x00007c00 -#define MSM8916_S4_P2_MASK 0x01f00000 - -#define MSM8916_S0_P1_SHIFT 7 -#define MSM8916_S1_P1_SHIFT 17 -#define MSM8916_S2_P1_SHIFT 27 -#define MSM8916_S3_P1_SHIFT 5 -#define MSM8916_S4_P1_SHIFT 15 - -#define MSM8916_S0_P2_SHIFT 12 -#define MSM8916_S1_P2_SHIFT 22 -#define MSM8916_S2_P2_SHIFT 0 -#define MSM8916_S3_P2_SHIFT 10 -#define MSM8916_S4_P2_SHIFT 20 - -#define MSM8916_CAL_SEL_MASK 0xe0000000 -#define MSM8916_CAL_SEL_SHIFT 29 - -/* eeprom layout data for 8939 */ -#define MSM8939_BASE0_MASK 0x000000ff -#define MSM8939_BASE1_MASK 0xff000000 -#define MSM8939_BASE0_SHIFT 0 -#define MSM8939_BASE1_SHIFT 24 - -#define MSM8939_S0_P1_MASK 0x000001f8 -#define MSM8939_S1_P1_MASK 0x001f8000 -#define MSM8939_S2_P1_MASK_0_4 0xf8000000 -#define MSM8939_S2_P1_MASK_5 0x00000001 -#define MSM8939_S3_P1_MASK 0x00001f80 -#define MSM8939_S4_P1_MASK 0x01f80000 -#define MSM8939_S5_P1_MASK 0x00003f00 -#define MSM8939_S6_P1_MASK 0x03f00000 -#define MSM8939_S7_P1_MASK 0x0000003f -#define MSM8939_S8_P1_MASK 0x0003f000 -#define MSM8939_S9_P1_MASK 0x07e00000 - -#define MSM8939_S0_P2_MASK 0x00007e00 -#define MSM8939_S1_P2_MASK 0x07e00000 -#define MSM8939_S2_P2_MASK 0x0000007e -#define MSM8939_S3_P2_MASK 0x0007e000 -#define MSM8939_S4_P2_MASK 0x7e000000 -#define MSM8939_S5_P2_MASK 0x000fc000 -#define MSM8939_S6_P2_MASK 0xfc000000 -#define MSM8939_S7_P2_MASK 0x00000fc0 -#define MSM8939_S8_P2_MASK 0x00fc0000 -#define MSM8939_S9_P2_MASK_0_4 0xf8000000 -#define MSM8939_S9_P2_MASK_5 0x00002000 - -#define MSM8939_S0_P1_SHIFT 3 -#define MSM8939_S1_P1_SHIFT 15 -#define MSM8939_S2_P1_SHIFT_0_4 27 -#define MSM8939_S2_P1_SHIFT_5 0 -#define MSM8939_S3_P1_SHIFT 7 -#define MSM8939_S4_P1_SHIFT 19 -#define MSM8939_S5_P1_SHIFT 8 -#define MSM8939_S6_P1_SHIFT 20 -#define MSM8939_S7_P1_SHIFT 0 -#define MSM8939_S8_P1_SHIFT 12 -#define MSM8939_S9_P1_SHIFT 21 - -#define MSM8939_S0_P2_SHIFT 9 -#define MSM8939_S1_P2_SHIFT 21 -#define MSM8939_S2_P2_SHIFT 1 -#define MSM8939_S3_P2_SHIFT 13 -#define MSM8939_S4_P2_SHIFT 25 -#define MSM8939_S5_P2_SHIFT 14 -#define MSM8939_S6_P2_SHIFT 26 -#define MSM8939_S7_P2_SHIFT 6 -#define MSM8939_S8_P2_SHIFT 18 -#define MSM8939_S9_P2_SHIFT_0_4 27 -#define MSM8939_S9_P2_SHIFT_5 13 - -#define MSM8939_CAL_SEL_MASK 0x7 -#define MSM8939_CAL_SEL_SHIFT 0 - -/* eeprom layout data for 8974 */ -#define BASE1_MASK 0xff -#define S0_P1_MASK 0x3f00 -#define S1_P1_MASK 0xfc000 -#define S2_P1_MASK 0x3f00000 -#define S3_P1_MASK 0xfc000000 -#define S4_P1_MASK 0x3f -#define S5_P1_MASK 0xfc0 -#define S6_P1_MASK 0x3f000 -#define S7_P1_MASK 0xfc0000 -#define S8_P1_MASK 0x3f000000 -#define S8_P1_MASK_BKP 0x3f -#define S9_P1_MASK 0x3f -#define S9_P1_MASK_BKP 0xfc0 -#define S10_P1_MASK 0xfc0 -#define S10_P1_MASK_BKP 0x3f000 -#define CAL_SEL_0_1 0xc0000000 -#define CAL_SEL_2 0x40000000 -#define CAL_SEL_SHIFT 30 -#define CAL_SEL_SHIFT_2 28 - -#define S0_P1_SHIFT 8 -#define S1_P1_SHIFT 14 -#define S2_P1_SHIFT 20 -#define S3_P1_SHIFT 26 -#define S5_P1_SHIFT 6 -#define S6_P1_SHIFT 12 -#define S7_P1_SHIFT 18 -#define S8_P1_SHIFT 24 -#define S9_P1_BKP_SHIFT 6 -#define S10_P1_SHIFT 6 -#define S10_P1_BKP_SHIFT 12 - -#define BASE2_SHIFT 12 -#define BASE2_BKP_SHIFT 18 -#define S0_P2_SHIFT 20 -#define S0_P2_BKP_SHIFT 26 -#define S1_P2_SHIFT 26 -#define S2_P2_BKP_SHIFT 6 -#define S3_P2_SHIFT 6 -#define S3_P2_BKP_SHIFT 12 -#define S4_P2_SHIFT 12 -#define S4_P2_BKP_SHIFT 18 -#define S5_P2_SHIFT 18 -#define S5_P2_BKP_SHIFT 24 -#define S6_P2_SHIFT 24 -#define S7_P2_BKP_SHIFT 6 -#define S8_P2_SHIFT 6 -#define S8_P2_BKP_SHIFT 12 -#define S9_P2_SHIFT 12 -#define S9_P2_BKP_SHIFT 18 -#define S10_P2_SHIFT 18 -#define S10_P2_BKP_SHIFT 24 - -#define BASE2_MASK 0xff000 -#define BASE2_BKP_MASK 0xfc0000 -#define S0_P2_MASK 0x3f00000 -#define S0_P2_BKP_MASK 0xfc000000 -#define S1_P2_MASK 0xfc000000 -#define S1_P2_BKP_MASK 0x3f -#define S2_P2_MASK 0x3f -#define S2_P2_BKP_MASK 0xfc0 -#define S3_P2_MASK 0xfc0 -#define S3_P2_BKP_MASK 0x3f000 -#define S4_P2_MASK 0x3f000 -#define S4_P2_BKP_MASK 0xfc0000 -#define S5_P2_MASK 0xfc0000 -#define S5_P2_BKP_MASK 0x3f000000 -#define S6_P2_MASK 0x3f000000 -#define S6_P2_BKP_MASK 0x3f -#define S7_P2_MASK 0x3f -#define S7_P2_BKP_MASK 0xfc0 -#define S8_P2_MASK 0xfc0 -#define S8_P2_BKP_MASK 0x3f000 -#define S9_P2_MASK 0x3f000 -#define S9_P2_BKP_MASK 0xfc0000 -#define S10_P2_MASK 0xfc0000 -#define S10_P2_BKP_MASK 0x3f000000 - +/* extra data for 8974 */ #define BKP_SEL 0x3 #define BKP_REDUN_SEL 0xe0000000 -#define BKP_REDUN_SHIFT 29 #define BIT_APPEND 0x3 -/* eeprom layout data for mdm9607 */ -#define MDM9607_BASE0_MASK 0x000000ff -#define MDM9607_BASE1_MASK 0x000ff000 -#define MDM9607_BASE0_SHIFT 0 -#define MDM9607_BASE1_SHIFT 12 - -#define MDM9607_S0_P1_MASK 0x00003f00 -#define MDM9607_S1_P1_MASK 0x03f00000 -#define MDM9607_S2_P1_MASK 0x0000003f -#define MDM9607_S3_P1_MASK 0x0003f000 -#define MDM9607_S4_P1_MASK 0x0000003f - -#define MDM9607_S0_P2_MASK 0x000fc000 -#define MDM9607_S1_P2_MASK 0xfc000000 -#define MDM9607_S2_P2_MASK 0x00000fc0 -#define MDM9607_S3_P2_MASK 0x00fc0000 -#define MDM9607_S4_P2_MASK 0x00000fc0 - -#define MDM9607_S0_P1_SHIFT 8 -#define MDM9607_S1_P1_SHIFT 20 -#define MDM9607_S2_P1_SHIFT 0 -#define MDM9607_S3_P1_SHIFT 12 -#define MDM9607_S4_P1_SHIFT 0 - -#define MDM9607_S0_P2_SHIFT 14 -#define MDM9607_S1_P2_SHIFT 26 -#define MDM9607_S2_P2_SHIFT 6 -#define MDM9607_S3_P2_SHIFT 18 -#define MDM9607_S4_P2_SHIFT 6 - -#define MDM9607_CAL_SEL_MASK 0x00700000 -#define MDM9607_CAL_SEL_SHIFT 20 +struct tsens_legacy_calibration_format tsens_8916_nvmem = { + .base_len = 7, + .base_shift = 3, + .sp_len = 5, + .mode = { 0, 29, 1 }, + .invalid = { 0, 31, 1 }, + .base = { { 0, 0 }, { 1, 25 } }, + .sp = { + { { 0, 7 }, { 0, 12 } }, + { { 0, 17 }, { 0, 22 } }, + { { 0, 27 }, { 1, 0 } }, + { { 1, 5 }, { 1, 10 } }, + { { 1, 15 }, { 1, 20 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8939_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 12, 0 }, + .invalid = { 12, 2 }, + .base = { { 0, 0 }, { 1, 24 } }, + .sp = { + { { 12, 3 }, { 12, 9 } }, + { { 12, 15 }, { 12, 21 } }, + { { 12, 27 }, { 13, 1 } }, + { { 13, 7 }, { 13, 13 } }, + { { 13, 19 }, { 13, 25 } }, + { { 0, 8 }, { 0, 14 } }, + { { 0, 20 }, { 0, 26 } }, + { { 1, 0 }, { 1, 6 } }, + { { 1, 12 }, { 1, 18 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8974_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 1, 30 }, + .invalid = { 3, 30 }, + .base = { { 0, 0 }, { 2, 12 } }, + .sp = { + { { 0, 8 }, { 2, 20 } }, + { { 0, 14 }, { 2, 26 } }, + { { 0, 20 }, { 3, 0 } }, + { { 0, 26 }, { 3, 6 } }, + { { 1, 0 }, { 3, 12 } }, + { { 1, 6 }, { 3, 18 } }, + { { 1, 12 }, { 3, 24 } }, + { { 1, 18 }, { 4, 0 } }, + { { 1, 24 }, { 4, 6 } }, + { { 2, 0 }, { 4, 12 } }, + { { 2, 6 }, { 4, 18 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8974_backup_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 4, 30, 1 }, + .invalid = { 5, 30, 1 }, + .base = { { 0, 0 }, { 2, 18 } }, + .sp = { + { { 0, 8 }, { 2, 26 } }, + { { 0, 14 }, { 3, 0 } }, + { { 0, 20 }, { 3, 6 } }, + { { 0, 26 }, { 3, 12 } }, + { { 1, 0 }, { 3, 18 } }, + { { 1, 6 }, { 3, 24, 1 } }, + { { 1, 12 }, { 4, 0, 1 } }, + { { 1, 18 }, { 4, 6, 1 } }, + { { 2, 0 }, { 4, 12, 1 } }, + { { 2, 6 }, { 4, 18, 1 } }, + { { 2, 12 }, { 4, 24, 1 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_9607_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 2, 20 }, + .invalid = { 2, 22 }, + .base = { { 0, 0 }, { 2, 12 } }, + .sp = { + { { 0, 8 }, { 0, 14 } }, + { { 0, 20 }, { 0, 26 } }, + { { 1, 0 }, { 1, 6 } }, + { { 1, 12 }, { 1, 18 } }, + { { 2, 0 }, { 2, 6 } }, + }, +}; static int calibrate_8916(struct tsens_priv *priv) { - int base0 = 0, base1 = 0, i; u32 p1[5], p2[5]; - int mode = 0; u32 *qfprom_cdata, *qfprom_csel; - int ret; + int mode, ret; ret = tsens_calibrate_nvmem(priv, 3); if (!ret) @@ -246,37 +139,9 @@ static int calibrate_8916(struct tsens_priv *priv) return PTR_ERR(qfprom_csel); } - mode = (qfprom_csel[0] & MSM8916_CAL_SEL_MASK) >> MSM8916_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[1] & MSM8916_BASE1_MASK) >> MSM8916_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MSM8916_S0_P2_MASK) >> MSM8916_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MSM8916_S1_P2_MASK) >> MSM8916_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MSM8916_S2_P2_MASK) >> MSM8916_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MSM8916_S3_P2_MASK) >> MSM8916_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[1] & MSM8916_S4_P2_MASK) >> MSM8916_S4_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 3); - fallthrough; - case ONE_PT_CALIB2: - base0 = (qfprom_cdata[0] & MSM8916_BASE0_MASK); - p1[0] = (qfprom_cdata[0] & MSM8916_S0_P1_MASK) >> MSM8916_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MSM8916_S1_P1_MASK) >> MSM8916_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[0] & MSM8916_S2_P1_MASK) >> MSM8916_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MSM8916_S3_P1_MASK) >> MSM8916_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[1] & MSM8916_S4_P1_MASK) >> MSM8916_S4_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 3); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_8916_nvmem, + p1, p2, + qfprom_cdata, qfprom_csel); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); @@ -287,12 +152,9 @@ static int calibrate_8916(struct tsens_priv *priv) static int calibrate_8939(struct tsens_priv *priv) { - int base0 = 0, base1 = 0, i; u32 p1[10], p2[10]; - int mode = 0; u32 *qfprom_cdata; - u32 cdata[4]; - int ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -302,52 +164,9 @@ static int calibrate_8939(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - /* Mapping between qfprom nvmem and calibration data */ - cdata[0] = qfprom_cdata[12]; - cdata[1] = qfprom_cdata[13]; - cdata[2] = qfprom_cdata[0]; - cdata[3] = qfprom_cdata[1]; - - mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT; - p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT; - p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT; - p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT; - p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT; - p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT; - p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT; - p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT; - p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT; - p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = (base1 + p2[i]) << 2; - fallthrough; - case ONE_PT_CALIB2: - base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT; - p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT; - p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT; - p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4; - p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5; - p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT; - p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT; - p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT; - p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT; - p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT; - p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base0) + p1[i]) << 2; - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_8939_nvmem, + p1, p2, + qfprom_cdata, NULL); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); @@ -355,21 +174,9 @@ static int calibrate_8939(struct tsens_priv *priv) return 0; } -static int calibrate_8974_nvmem(struct tsens_priv *priv) +static void fixup_8974_points(int mode, u32 *p1, u32 *p2) { - int i, ret, mode; - u32 p1[11], p2[11]; - u32 backup; - - ret = nvmem_cell_read_variable_le_u32(priv->dev, "use_backup", &backup); - if (ret == -ENOENT) - dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); - if (ret < 0) - return ret; - - mode = tsens_read_calibration(priv, 2, p1, p2, backup == BKP_SEL); - if (mode < 0) - return mode; + int i; if (mode == NO_PT_CALIB) { p1[0] += 2; @@ -384,7 +191,7 @@ static int calibrate_8974_nvmem(struct tsens_priv *priv) p1[9] += 9; p1[10] += 8; } else { - for (i = 0; i < priv->num_sensors; i++) { + for (i = 0; i < 11; i++) { /* * ONE_PT_CALIB requires using addition here instead of * using OR operation. @@ -394,6 +201,26 @@ static int calibrate_8974_nvmem(struct tsens_priv *priv) } } +} + +static int calibrate_8974_nvmem(struct tsens_priv *priv) +{ + u32 p1[11], p2[11]; + u32 backup; + int ret, mode; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "use_backup", &backup); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + mode = tsens_read_calibration(priv, 2, p1, p2, backup == BKP_SEL); + if (mode < 0) + return mode; + + fixup_8974_points(mode, p1, p2); + compute_intercept_slope(priv, p1, p2, mode); return 0; @@ -401,12 +228,10 @@ static int calibrate_8974_nvmem(struct tsens_priv *priv) static int calibrate_8974(struct tsens_priv *priv) { - int base1 = 0, base2 = 0, i; u32 p1[11], p2[11]; - int mode = 0; u32 *calib, *bkp; u32 calib_redun_sel; - int ret; + int mode, ret; ret = calibrate_8974_nvmem(priv); if (ret == 0) @@ -422,116 +247,18 @@ static int calibrate_8974(struct tsens_priv *priv) return PTR_ERR(bkp); } - calib_redun_sel = bkp[1] & BKP_REDUN_SEL; - calib_redun_sel >>= BKP_REDUN_SHIFT; - - if (calib_redun_sel == BKP_SEL) { - mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT; - p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT; - p2[1] = (bkp[3] & S1_P2_BKP_MASK); - p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT; - p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT; - p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT; - p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT; - p2[6] = (calib[5] & S6_P2_BKP_MASK); - p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT; - p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT; - p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT; - p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT; - fallthrough; - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = bkp[0] & BASE1_MASK; - p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (bkp[1] & S4_P1_MASK); - p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT; - p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT; - p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT; - break; - } - } else { - mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT; - p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT; - p2[2] = (calib[3] & S2_P2_MASK); - p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT; - p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT; - p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT; - p2[7] = (calib[4] & S7_P2_MASK); - p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT; - p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT; - p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT; - fallthrough; - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = calib[0] & BASE1_MASK; - p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (calib[1] & S4_P1_MASK); - p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT; - p1[9] = (calib[2] & S9_P1_MASK); - p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT; - break; - } - } + calib_redun_sel = FIELD_GET(BKP_REDUN_SEL, bkp[1]); - switch (mode) { - case ONE_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) - p1[i] += (base1 << 2) | BIT_APPEND; - break; - case TWO_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) { - p2[i] += base2; - p2[i] <<= 2; - p2[i] |= BIT_APPEND; - } - fallthrough; - case ONE_PT_CALIB2: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] += base1; - p1[i] <<= 2; - p1[i] |= BIT_APPEND; - } - break; - default: - for (i = 0; i < priv->num_sensors; i++) - p2[i] = 780; - p1[0] = 502; - p1[1] = 509; - p1[2] = 503; - p1[3] = 509; - p1[4] = 505; - p1[5] = 509; - p1[6] = 507; - p1[7] = 510; - p1[8] = 508; - p1[9] = 509; - p1[10] = 508; - break; - } + if (calib_redun_sel == BKP_SEL) + mode = tsens_read_calibration_legacy(priv, &tsens_8974_backup_nvmem, + p1, p2, + bkp, calib); + else + mode = tsens_read_calibration_legacy(priv, &tsens_8974_nvmem, + p1, p2, + calib, NULL); + + fixup_8974_points(mode, p1, p2); compute_intercept_slope(priv, p1, p2, mode); kfree(calib); @@ -542,11 +269,9 @@ static int calibrate_8974(struct tsens_priv *priv) static int calibrate_9607(struct tsens_priv *priv) { - int base, i; u32 p1[5], p2[5]; - int mode = 0; u32 *qfprom_cdata; - int ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -556,37 +281,9 @@ static int calibrate_9607(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - mode = (qfprom_cdata[2] & MDM9607_CAL_SEL_MASK) >> MDM9607_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base = (qfprom_cdata[2] & MDM9607_BASE1_MASK) >> MDM9607_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MDM9607_S0_P2_MASK) >> MDM9607_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MDM9607_S1_P2_MASK) >> MDM9607_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MDM9607_S2_P2_MASK) >> MDM9607_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MDM9607_S3_P2_MASK) >> MDM9607_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MDM9607_S4_P2_MASK) >> MDM9607_S4_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base = (qfprom_cdata[0] & MDM9607_BASE0_MASK); - p1[0] = (qfprom_cdata[0] & MDM9607_S0_P1_MASK) >> MDM9607_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MDM9607_S1_P1_MASK) >> MDM9607_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MDM9607_S2_P1_MASK) >> MDM9607_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MDM9607_S3_P1_MASK) >> MDM9607_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MDM9607_S4_P1_MASK) >> MDM9607_S4_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_9607_nvmem, + p1, p2, + qfprom_cdata, NULL); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 5bba75a845c5..6d1ea430f90b 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -21,129 +21,54 @@ #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 -/* eeprom layout data for msm8956/76 (v1) */ -#define MSM8976_BASE0_MASK 0xff -#define MSM8976_BASE1_MASK 0xff -#define MSM8976_BASE1_SHIFT 8 - -#define MSM8976_S0_P1_MASK 0x3f00 -#define MSM8976_S1_P1_MASK 0x3f00000 -#define MSM8976_S2_P1_MASK 0x3f -#define MSM8976_S3_P1_MASK 0x3f000 -#define MSM8976_S4_P1_MASK 0x3f00 -#define MSM8976_S5_P1_MASK 0x3f00000 -#define MSM8976_S6_P1_MASK 0x3f -#define MSM8976_S7_P1_MASK 0x3f000 -#define MSM8976_S8_P1_MASK 0x1f8 -#define MSM8976_S9_P1_MASK 0x1f8000 -#define MSM8976_S10_P1_MASK 0xf8000000 -#define MSM8976_S10_P1_MASK_1 0x1 - -#define MSM8976_S0_P2_MASK 0xfc000 -#define MSM8976_S1_P2_MASK 0xfc000000 -#define MSM8976_S2_P2_MASK 0xfc0 -#define MSM8976_S3_P2_MASK 0xfc0000 -#define MSM8976_S4_P2_MASK 0xfc000 -#define MSM8976_S5_P2_MASK 0xfc000000 -#define MSM8976_S6_P2_MASK 0xfc0 -#define MSM8976_S7_P2_MASK 0xfc0000 -#define MSM8976_S8_P2_MASK 0x7e00 -#define MSM8976_S9_P2_MASK 0x7e00000 -#define MSM8976_S10_P2_MASK 0x7e - -#define MSM8976_S0_P1_SHIFT 8 -#define MSM8976_S1_P1_SHIFT 20 -#define MSM8976_S2_P1_SHIFT 0 -#define MSM8976_S3_P1_SHIFT 12 -#define MSM8976_S4_P1_SHIFT 8 -#define MSM8976_S5_P1_SHIFT 20 -#define MSM8976_S6_P1_SHIFT 0 -#define MSM8976_S7_P1_SHIFT 12 -#define MSM8976_S8_P1_SHIFT 3 -#define MSM8976_S9_P1_SHIFT 15 -#define MSM8976_S10_P1_SHIFT 27 -#define MSM8976_S10_P1_SHIFT_1 0 - -#define MSM8976_S0_P2_SHIFT 14 -#define MSM8976_S1_P2_SHIFT 26 -#define MSM8976_S2_P2_SHIFT 6 -#define MSM8976_S3_P2_SHIFT 18 -#define MSM8976_S4_P2_SHIFT 14 -#define MSM8976_S5_P2_SHIFT 26 -#define MSM8976_S6_P2_SHIFT 6 -#define MSM8976_S7_P2_SHIFT 18 -#define MSM8976_S8_P2_SHIFT 9 -#define MSM8976_S9_P2_SHIFT 21 -#define MSM8976_S10_P2_SHIFT 1 - -#define MSM8976_CAL_SEL_MASK 0x3 - -/* eeprom layout data for qcs404/405 (v1) */ -#define BASE0_MASK 0x000007f8 -#define BASE1_MASK 0x0007f800 -#define BASE0_SHIFT 3 -#define BASE1_SHIFT 11 - -#define S0_P1_MASK 0x0000003f -#define S1_P1_MASK 0x0003f000 -#define S2_P1_MASK 0x3f000000 -#define S3_P1_MASK 0x000003f0 -#define S4_P1_MASK 0x003f0000 -#define S5_P1_MASK 0x0000003f -#define S6_P1_MASK 0x0003f000 -#define S7_P1_MASK 0x3f000000 -#define S8_P1_MASK 0x000003f0 -#define S9_P1_MASK 0x003f0000 - -#define S0_P2_MASK 0x00000fc0 -#define S1_P2_MASK 0x00fc0000 -#define S2_P2_MASK_1_0 0xc0000000 -#define S2_P2_MASK_5_2 0x0000000f -#define S3_P2_MASK 0x0000fc00 -#define S4_P2_MASK 0x0fc00000 -#define S5_P2_MASK 0x00000fc0 -#define S6_P2_MASK 0x00fc0000 -#define S7_P2_MASK_1_0 0xc0000000 -#define S7_P2_MASK_5_2 0x0000000f -#define S8_P2_MASK 0x0000fc00 -#define S9_P2_MASK 0x0fc00000 - -#define S0_P1_SHIFT 0 -#define S0_P2_SHIFT 6 -#define S1_P1_SHIFT 12 -#define S1_P2_SHIFT 18 -#define S2_P1_SHIFT 24 -#define S2_P2_SHIFT_1_0 30 - -#define S2_P2_SHIFT_5_2 0 -#define S3_P1_SHIFT 4 -#define S3_P2_SHIFT 10 -#define S4_P1_SHIFT 16 -#define S4_P2_SHIFT 22 - -#define S5_P1_SHIFT 0 -#define S5_P2_SHIFT 6 -#define S6_P1_SHIFT 12 -#define S6_P2_SHIFT 18 -#define S7_P1_SHIFT 24 -#define S7_P2_SHIFT_1_0 30 - -#define S7_P2_SHIFT_5_2 0 -#define S8_P1_SHIFT 4 -#define S8_P2_SHIFT 10 -#define S9_P1_SHIFT 16 -#define S9_P2_SHIFT 22 - -#define CAL_SEL_MASK 7 -#define CAL_SEL_SHIFT 0 +struct tsens_legacy_calibration_format tsens_qcs404_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 4, 0 }, + .invalid = { 4, 2 }, + .base = { { 4, 3 }, { 4, 11 } }, + .sp = { + { { 0, 0 }, { 0, 6 } }, + { { 0, 12 }, { 0, 18 } }, + { { 0, 24 }, { 0, 30 } }, + { { 1, 4 }, { 1, 10 } }, + { { 1, 16 }, { 1, 22 } }, + { { 2, 0 }, { 2, 6 } }, + { { 2, 12 }, { 2, 18 } }, + { { 2, 24 }, { 2, 30 } }, + { { 3, 4 }, { 3, 10 } }, + { { 3, 16 }, { 3, 22 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8976_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 4, 0 }, + .invalid = { 4, 2 }, + .base = { { 0, 0 }, { 2, 8 } }, + .sp = { + { { 0, 8 }, { 0, 14 } }, + { { 0, 20 }, { 0, 26 } }, + { { 1, 0 }, { 1, 6 } }, + { { 1, 12 }, { 1, 18 } }, + { { 2, 8 }, { 2, 14 } }, + { { 2, 20 }, { 2, 26 } }, + { { 3, 0 }, { 3, 6 } }, + { { 3, 12 }, { 3, 18 } }, + { { 4, 2 }, { 4, 9 } }, + { { 4, 14 }, { 4, 21 } }, + { { 4, 26 }, { 5, 1 } }, + }, +}; static int calibrate_v1(struct tsens_priv *priv) { - u32 base0 = 0, base1 = 0; u32 p1[10], p2[10]; - u32 mode = 0, lsb = 0, msb = 0; u32 *qfprom_cdata; - int i, ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -153,53 +78,9 @@ static int calibrate_v1(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; - /* This value is split over two registers, 2 bits and 4 bits */ - lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; - msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; - p2[2] = msb << 2 | lsb; - p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; - p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; - p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; - /* This value is split over two registers, 2 bits and 4 bits */ - lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; - msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; - p2[7] = msb << 2 | lsb; - p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; - p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; - p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; - p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; - p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_qcs404_nvmem, + p1, p2, + qfprom_cdata, NULL); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); @@ -209,11 +90,9 @@ static int calibrate_v1(struct tsens_priv *priv) static int calibrate_8976(struct tsens_priv *priv) { - int base0 = 0, base1 = 0, i; u32 p1[11], p2[11]; - int mode = 0, tmp = 0; u32 *qfprom_cdata; - int ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -223,53 +102,10 @@ static int calibrate_8976(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK); - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT; - p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT; - p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT; - p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT; - p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT; - p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT; - p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT; - - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK; - p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT; - p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT; - p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT; - p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT; - p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT; - p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT; - p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT; - tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1; - p1[10] |= tmp; - - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_8976_nvmem, + p1, p2, + qfprom_cdata, NULL); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 6facdb0246a5..6d785ffe8fac 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -171,6 +171,70 @@ int tsens_calibrate_common(struct tsens_priv *priv) return tsens_calibrate_nvmem(priv, 2); } +static u32 tsens_read_cell(const struct tsens_single_value *cell, u8 len, u32 *data0, u32 *data1) +{ + u32 val; + u32 *data = cell->blob ? data1 : data0; + + if (cell->shift + len <= 32) { + val = data[cell->idx] >> cell->shift; + } else { + u8 part = 32 - cell->shift; + + val = data[cell->idx] >> cell->shift; + val |= data[cell->idx + 1] << part; + } + + return val & ((1 << len) - 1); +} + +int tsens_read_calibration_legacy(struct tsens_priv *priv, + const struct tsens_legacy_calibration_format *format, + u32 *p1, u32 *p2, + u32 *cdata0, u32 *cdata1) +{ + u32 mode, invalid; + u32 base1, base2; + int i; + + mode = tsens_read_cell(&format->mode, 2, cdata0, cdata1); + invalid = tsens_read_cell(&format->invalid, 1, cdata0, cdata1); + if (invalid) + mode = NO_PT_CALIB; + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + base1 = tsens_read_cell(&format->base[0], format->base_len, cdata0, cdata1); + base2 = tsens_read_cell(&format->base[1], format->base_len, cdata0, cdata1); + + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = tsens_read_cell(&format->sp[i][0], format->sp_len, cdata0, cdata1); + p2[i] = tsens_read_cell(&format->sp[i][1], format->sp_len, cdata0, cdata1); + } + + switch (mode) { + case ONE_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = p1[i] + (base1 << format->base_shift); + break; + case TWO_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p2[i] = (p2[i] + base2) << format->base_shift; + fallthrough; + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (p1[i] + base1) << format->base_shift; + break; + default: + dev_dbg(priv->dev, "calibrationless mode\n"); + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + } + + return mode; +} + /* * Use this function on devices where slope and offset calculations * depend on calibration data read from qfprom. On others the slope diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index a9ae8df9f810..dba9cd38f637 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -584,7 +584,45 @@ struct tsens_priv { struct tsens_sensor sensor[]; }; +/** + * struct tsens_single_value - internal representation of a single field inside nvmem calibration data + * @idx: index into the u32 data array + * @shift: the shift of the first bit in the value + * @blob: index of the data blob to use for this cell + */ +struct tsens_single_value { + u8 idx; + u8 shift; + u8 blob; +}; + +/** + * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob + * @base_len: the length of the base fields inside calibration data + * @base_shift: the shift to be applied to base data + * @sp_len: the length of the sN_pM fields inside calibration data + * @mode: descriptor of the calibration mode field + * @invalid: descriptor of the calibration mode invalid field + * @base: descriptors of the base0 and base1 fields + * @sp: descriptors of the sN_pM fields + */ +struct tsens_legacy_calibration_format { + unsigned int base_len; + unsigned int base_shift; + unsigned int sp_len; + /* just two bits */ + struct tsens_single_value mode; + /* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */ + struct tsens_single_value invalid; + struct tsens_single_value base[2]; + struct tsens_single_value sp[][2]; +}; + char *qfprom_read(struct device *dev, const char *cname); +int tsens_read_calibration_legacy(struct tsens_priv *priv, + const struct tsens_legacy_calibration_format *format, + u32 *p1, u32 *p2, + u32 *cdata, u32 *csel); int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup); int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); int tsens_calibrate_common(struct tsens_priv *priv); From patchwork Sun Jan 1 19:40:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0916FC54EBF for ; Sun, 1 Jan 2023 19:41:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231748AbjAATlB (ORCPT ); Sun, 1 Jan 2023 14:41:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231422AbjAATkt (ORCPT ); Sun, 1 Jan 2023 14:40:49 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A17C92F1 for ; Sun, 1 Jan 2023 11:40:46 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id f34so38853688lfv.10 for ; Sun, 01 Jan 2023 11:40:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ic31fMG7ujfaKO2qUrY+ZPMHyXpn2xzjXgAqSzwYmrU=; b=j4Ansk434Cvyy6VUVHqPhjvuKEufxrjUsfHPCRkjeoP0TCCXSX5y+rlx2UDPV+E8nn Z0l6TeK6OnVnBx+4T4XzZBbErffosG+MKd1Xhvc9+LLT+CC8SB2CVX6SKvQEOKuwxe/h f4oA82ilO+ekD4We/rctOzq90RcIOUVwqObPKB1EQVclcCr9afrTqw+VlbPh/Qu3ZrrY QI3OXiQj5nzAq8tXOqX7QqxXWnFt77AkoYuEoXu5SNYQA2j1ZtaDioy68jPxga1NeDVK dwQjfx6W+DBrsZ4VW6Ooc4PBL85oUzypNFJzc68f1yx9Qyi891efugxYwsAgLFPBfLp/ vQGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ic31fMG7ujfaKO2qUrY+ZPMHyXpn2xzjXgAqSzwYmrU=; b=bKks+JlehGBDPckOkGTBRIao8KcvVsdmOSvB6JA2rjTKKFchumK3EiARGkcXe0tKrQ 0w82ZW7jiQs2J64NDy23oa8IudCEysbo1bZS0arb0q/nKhy9GBDtoGhdvdrYm4hxh0Ip V//Eho/momiD3BOxCCHZLGXcuqRcG77ZiozJ4gskb4znba+mO3KeWpBSHM5aZ/Dfzh5J shIHvY7Co3sx9sEAY86o+ZmhgUtnhJrADjfC0zLqbOq5ZCcVOT/Qn88B5ncZh1m3+nn8 e4moG1Q4Cwnp4qyCmZkkLXP2ghbDsm8eVx2c0JyNSml2tfNesTg+OwRQfz5HLOehQM8W LV8Q== X-Gm-Message-State: AFqh2koNeP14netJWpmK0bTqgHxCFWH7KAhUKRCKNZ9MsII4JJXhJXDW /kW+QG1h2l72HEog24dufhVZWw== X-Google-Smtp-Source: AMrXdXvfC4NLVIogW3uOyLNGTP7y+bTTjFwqJN4CZTvV5lmGW2BoHHkR2jlFLLfqGepuXyK0goGcPQ== X-Received: by 2002:a05:6512:31d6:b0:4b5:7817:419d with SMTP id j22-20020a05651231d600b004b57817419dmr12657322lfe.41.1672602046207; Sun, 01 Jan 2023 11:40:46 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:45 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 12/20] thermal/drivers/tsens: Drop single-cell code for mdm9607 Date: Sun, 1 Jan 2023 21:40:26 +0200 Message-Id: <20230101194034.831222-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for mdm9607 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on mdm9607. Cc: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 38 ++++++------------------------- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index f8b50bf14190..9488416b568c 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -267,30 +267,6 @@ static int calibrate_8974(struct tsens_priv *priv) return 0; } -static int calibrate_9607(struct tsens_priv *priv) -{ - u32 p1[5], p2[5]; - u32 *qfprom_cdata; - int mode, ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = tsens_read_calibration_legacy(priv, &tsens_9607_nvmem, - p1, p2, - qfprom_cdata, NULL); - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - static int __init init_8939(struct tsens_priv *priv) { priv->sensor[0].slope = 2911; priv->sensor[1].slope = 2789; @@ -355,6 +331,12 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static const struct tsens_ops ops_v0_1 = { + .init = init_common, + .calibrate = tsens_calibrate_common, + .get_temp = get_temp_common, +}; + static const struct tsens_ops ops_8916 = { .init = init_common, .calibrate = calibrate_8916, @@ -398,15 +380,9 @@ struct tsens_plat_data data_8974 = { .fields = tsens_v0_1_regfields, }; -static const struct tsens_ops ops_9607 = { - .init = init_common, - .calibrate = calibrate_9607, - .get_temp = get_temp_common, -}; - struct tsens_plat_data data_9607 = { .num_sensors = 5, - .ops = &ops_9607, + .ops = &ops_v0_1, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, }; From patchwork Sun Jan 1 19:40:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53EC4C54EBD for ; Sun, 1 Jan 2023 19:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231534AbjAATlE (ORCPT ); Sun, 1 Jan 2023 14:41:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231559AbjAATku (ORCPT ); Sun, 1 Jan 2023 14:40:50 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5D6AC6D for ; Sun, 1 Jan 2023 11:40:47 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id y25so38891189lfa.9 for ; Sun, 01 Jan 2023 11:40:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wt9qF2p4XV3UcntcRwMREXcr64MEVdaJRIf7w8TkGqg=; b=fAHb4vfOg6yVNKEGLNvpXBkuRYnXYROhkq3UvltOqfNlLGJzFICONebpMGsA+uDX3b VM8yOs/O1aGzqqDqvSarPnTuirSI8i2liBiwLjMxpBC5/jK4xppmJ6N2Zc1WiaXG306Z SLFGYcef/UWGg64ggayXXg99kXFWlHAEMrhOLr9bTab/WNq/336/SrXTiXkIyqTYNQq5 QMGJ63DqHu5fz0phR865Q6ODUFMzRkmA5uMbbp+x3JuCMTzZiGe7pRDD0hoRCp3S5XmO I/S6UniANcdvAcrCrDXVoFs2WR4m35D2mTbLE96n6apfZX8mngNSresJ7s0tvHfLiBMx P/vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wt9qF2p4XV3UcntcRwMREXcr64MEVdaJRIf7w8TkGqg=; b=4PnzZWBHDr02Sb6bSzd0yr0h9DXWLWag54jw6rCSYdD6i/xx+7zU7VUEGa9i1itGnL WEIiZeOM4dhRtOs+p5p3pYH7ate0vq8SJI94Rf4XDIft12wzI+pXaGXJWz8JPv4UL3cp vXZKbcm4Dvb1d4DpOhhLzCQDSluFh23NYIAu0i3CT56PtIgDu/9StM/GiwxgEF9gwTWh 01PV+oTEdRy3vLmZPamRPEfCpYZ0G1MPqaV/xayOQ36/cFulgSmaN3TEptHDWiDL194H SJ2haAgDnuzJz+rzzuayz+9jy93R/s7CluXS/cWTRfUl3Rw81JnpreHIUSZvCe91j/F/ h3wQ== X-Gm-Message-State: AFqh2kqzdScd+fzEXZE6jcc7y4wDq1bT28AKF0HgCM1Z60Y2wWsR9uOn ZfmNO2AMvAOC5lvwAS90DyvO5A== X-Google-Smtp-Source: AMrXdXvbdbMuCebo3Of93Q9x1IBW1OOWRb3oS3VGR2JzaBJKVjKsPpwjpWybdeF3LUBRiwvFOV/8Qg== X-Received: by 2002:a05:6512:3f1b:b0:4cb:2aa:9e58 with SMTP id y27-20020a0565123f1b00b004cb02aa9e58mr7769977lfa.13.1672602047401; Sun, 01 Jan 2023 11:40:47 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:46 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 13/20] thermal/drivers/tsens: Drop single-cell code for msm8939 Date: Sun, 1 Jan 2023 21:40:27 +0200 Message-Id: <20230101194034.831222-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for msm8939 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8939. Cc: Shawn Guo Cc: Bryan O'Donoghue Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Acked-by: Shawn Guo Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue --- drivers/thermal/qcom/tsens-v0_1.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 9488416b568c..e89c6f39a3ae 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -150,30 +150,6 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } -static int calibrate_8939(struct tsens_priv *priv) -{ - u32 p1[10], p2[10]; - u32 *qfprom_cdata; - int mode, ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = tsens_read_calibration_legacy(priv, &tsens_8939_nvmem, - p1, p2, - qfprom_cdata, NULL); - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - static void fixup_8974_points(int mode, u32 *p1, u32 *p2) { int i; @@ -354,7 +330,7 @@ struct tsens_plat_data data_8916 = { static const struct tsens_ops ops_8939 = { .init = init_8939, - .calibrate = calibrate_8939, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_common, }; From patchwork Sun Jan 1 19:40:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45CB2C54EF1 for ; Sun, 1 Jan 2023 19:41:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231298AbjAATlD (ORCPT ); Sun, 1 Jan 2023 14:41:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbjAATk4 (ORCPT ); Sun, 1 Jan 2023 14:40:56 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEDD31009 for ; Sun, 1 Jan 2023 11:40:48 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id cf42so38888529lfb.1 for ; Sun, 01 Jan 2023 11:40:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zvBs74YfpWC4BlnlrgIGPtcDViBoUL8HTEcoEwvCBA8=; b=H5B7N3z5HmbvnUAap8b+0J9g19cmjTXFDe7f80d/0ogLbfCPP/mph6SISOuV/8zP9D vyVIbiLA1HqpeoyNuuTRqfTMQMKO6lqjA3+/Ya3qySMaFxbujQry3h/gWCKgcFdijhQt 4RyFMLZBM7rh7sEhXm/FK9CEN75Em2FIJX+aMbsWJgrPEpIn+D2IfGqgWm0Q4tXUKu/I Rji3QvECGDbOMh75rGWj4VeeD3yORX3gfbvOXFWXG9nJJWeWXhuP1YUYNj5vk3f9kASS Gj2FrAnwJyG2TvsScH1d9EkEFGtcEvfTbV669mIkjkbXc0/uZWvNAYkviKLvnGpE0Vx5 USWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zvBs74YfpWC4BlnlrgIGPtcDViBoUL8HTEcoEwvCBA8=; b=LlWYb7sKiX7/RnZWBAJAvHdtNm7noSaaUVrHB5ZoURDJljYzW/Xm4rp4Bi/BTMC3VN yRJH2kFOAxD42andj+yrBsqovbfbkTOX2+Lid37YDoB7DD0Fp+kLk6fz+tzvBJWiROcP QgJtxXpnhJkgNLigIvfVPyVyVvmZk4LuIY4w0j0+hkOGXtLy3g3/maqx1h1Jien8yaTj BnoiwTHFdczm6UWH8eVafVQXbnrn+05ZfHbPAyRwql6Ki7cqY/NmzEcJPlaZqdeO9Wll iMQyn0E1cDoAnWk5XnYsserpJbGjG4mxUy5BDmDMufX9AVYmSEEgbq5Oc5ZX3qM2+Brx G9gg== X-Gm-Message-State: AFqh2koK2xlj0c5/tIhcxgI8ZuAzC1RcOEqvxqtrY59fVwQvtdXDwz/M IcsymdSQsQj5NBWZBZJNQs3r0Q== X-Google-Smtp-Source: AMrXdXue3QJH27rRQHt1kNxFyvrmcDGwWgd5top/bBUbSdiiizljPqJMh73IKaKZiEBzf+cd85HAQA== X-Received: by 2002:a05:6512:3f16:b0:4ca:f97f:4a21 with SMTP id y22-20020a0565123f1600b004caf97f4a21mr9460201lfa.37.1672602048431; Sun, 01 Jan 2023 11:40:48 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:47 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v6 14/20] thermal/drivers/tsens: Drop single-cell code for msm8976/msm8956 Date: Sun, 1 Jan 2023 21:40:28 +0200 Message-Id: <20230101194034.831222-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for msm8976 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8976. Cc: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/qcom/tsens-v1.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 6d1ea430f90b..b822a426066d 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -88,31 +88,6 @@ static int calibrate_v1(struct tsens_priv *priv) return 0; } -static int calibrate_8976(struct tsens_priv *priv) -{ - u32 p1[11], p2[11]; - u32 *qfprom_cdata; - int mode, ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = tsens_read_calibration_legacy(priv, &tsens_8976_nvmem, - p1, p2, - qfprom_cdata, NULL); - - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - /* v1.x: msm8956,8976,qcs404,405 */ static struct tsens_features tsens_v1_feat = { @@ -211,7 +186,7 @@ struct tsens_plat_data data_tsens_v1 = { static const struct tsens_ops ops_8956 = { .init = init_8956, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; @@ -224,7 +199,7 @@ struct tsens_plat_data data_8956 = { static const struct tsens_ops ops_8976 = { .init = init_common, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; From patchwork Sun Jan 1 19:40:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AF10C4167B for ; Sun, 1 Jan 2023 19:41:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbjAATlL (ORCPT ); Sun, 1 Jan 2023 14:41:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231737AbjAATlB (ORCPT ); Sun, 1 Jan 2023 14:41:01 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E10E9135 for ; Sun, 1 Jan 2023 11:40:49 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id bq39so31102906lfb.0 for ; Sun, 01 Jan 2023 11:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5ZBrWGsgyNha7RW/93aBTXd8U+HviEYa+gXS5auCDeY=; b=WXFj8kiF8wjeKgfs/iuZBoFg/xKb0CYaYlNtA+zqP64hC2+AtxjgEcyzNP1AU3ZXCH XHTYBdGke3qpI8CLEV4EGd0DvEwith5f872E7/8OUbY575zGlRhwPAucSli4fi/zqzED xjl+4FOrM+o5oQs/3Sz/iFZPnkoZfyM1vhdJDkbJDqgN/4/Sm3HmOKLK7AfoCp9VubnL FFkdB42U7+Cmm2cza1V0N+p9C5wqV4KVUiuLlIlUWMyF4LxGz9E6nlOTeyYHFPmKbZWH TpJj1dt5ytmhUvQRWMbcYQJg4DfIZVQyi3mu1XMzx8AsNxL3iGPPLz6CW1Tte9RVHhpg mArA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5ZBrWGsgyNha7RW/93aBTXd8U+HviEYa+gXS5auCDeY=; b=fynbeOPUeRjhEBNHO6vvYrfzxj8Bo3v4xdXeREiwXrsgSii6ZWrrGA2rbH3UbfOF7T frCPaCv9IJYZgvjBMscc5w9amg1Dd66G4mDgWz48PRgzBTQfrgDOmXcT8K3sYgQtQqZ4 0dQA4Orb9OWg+Sr1J8X397cpMctTJtOWCtADiH9TigsltdquzpBe/qbieJTiIoxP15Gg Zfs8l90mysvdsEQnGc8YJmheuyeyd+M1g0L38sDQ7aQPy/c7SI9q6sQb1USXQxMZWbcE HEt39FZmBNRyfG8+lO8McqGL3+3ocBAsb0i7VgvGXM1fO5DrasY+rF2pw5dV1jrq/U0L 2RRA== X-Gm-Message-State: AFqh2kprKDwPjiO5JdyQW2E8hVXJE5yvAZI4uwfw3i9xiAJ+Lmllz+Wk ArYXwuMJcPCEk/QJM9Ui7q9XFcc4lPQor0I+ X-Google-Smtp-Source: AMrXdXsnmPW7gHWrbB6yajAVaDxCZJZqZWU8PHoSXYkHSMAbHLDj1tSumJs0lEhHhVxU2aw3XFCnHQ== X-Received: by 2002:ac2:5604:0:b0:4b5:8507:9ae6 with SMTP id v4-20020ac25604000000b004b585079ae6mr9708657lfd.2.1672602049399; Sun, 01 Jan 2023 11:40:49 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:49 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 15/20] arm64: dts: qcom: msm8956: use SoC-specific compat for tsens Date: Sun, 1 Jan 2023 21:40:29 +0200 Message-Id: <20230101194034.831222-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The slope values used during tsens calibration differ between msm8976 and msm8956 SoCs. Use SoC-specific compat value for the msm8956 SoC. Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index e432512d8716..668e05185c21 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -12,6 +12,10 @@ &pmu { interrupts = ; }; +&tsens { + compatible = "qcom,msm8956-tsens", "qcom,tsens-v1"; +}; + /* * You might be wondering.. why is it so empty out there? * Well, the SoCs are almost identical. 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:49 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 16/20] arm64: dts: qcom: msm8916: specify per-sensor calibration cells Date: Sun, 1 Jan 2023 21:40:30 +0200 Message-Id: <20230101194034.831222-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2ca8e977fc2a..2ae21c5ade03 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,70 @@ qfprom: qfprom@5c000 { reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + + // no tsens with hw_id 3 + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + + tsens_s4_p2: s4-p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + + tsens_s5_p1: s5-p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + + tsens_s5_p2: s5-p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +532,22 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + + // no hw_id 3 + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; #qcom,sensors = <5>; interrupts = ; interrupt-names = "uplow"; From patchwork Sun Jan 1 19:40:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2952FC54EF0 for ; Sun, 1 Jan 2023 19:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231624AbjAATlJ (ORCPT ); Sun, 1 Jan 2023 14:41:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231318AbjAATlB (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:50 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 17/20] arm64: dts: qcom: msm8976: specify per-sensor calibration cells Date: Sun, 1 Jan 2023 21:40:31 +0200 Message-Id: <20230101194034.831222-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 153 +++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 05dcb30b0779..2d360d05aa5e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -481,8 +481,129 @@ qfprom: qfprom@a4000 { #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@218 { - reg = <0x218 0x18>; + tsens_base1: base1@218 { + reg = <0x218 1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@219 { + reg = <0x219 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@219 { + reg = <0x219 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@21a { + reg = <0x21a 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@21b { + reg = <0x21b 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@21c { + reg = <0x21c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@21c { + reg = <0x21c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@21d { + reg = <0x21d 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@21e { + reg = <0x21e 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@220 { + reg = <0x220 1>; + bits = <0 8>; + }; + + tsens_s4_p1: s4-p1@221 { + reg = <0x221 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@221 { + reg = <0x221 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@222 { + reg = <0x222 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@223 { + reg = <0x224 0x1>; + bits = <2 6>; + }; + + tsens_s6_p1: s6-p1@224 { + reg = <0x224 0x1>; + bits = <0 6>; + }; + + tsens_s6_p2: s6-p2@224 { + reg = <0x224 0x2>; + bits = <6 6>; + }; + + tsens_s7_p1: s7-p1@225 { + reg = <0x225 0x2>; + bits = <4 6>; + }; + + tsens_s7_p2: s7-p2@226 { + reg = <0x226 0x2>; + bits = <2 6>; + }; + + tsens_mode: mode@228 { + reg = <0x228 1>; + bits = <0 3>; + }; + + tsens_s8_p1: s8-p1@228 { + reg = <0x228 0x2>; + bits = <3 6>; + }; + + tsens_s8_p2: s8-p2@229 { + reg = <0x229 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@229 { + reg = <0x229 0x2>; + bits = <7 6>; + }; + + tsens_s9_p2: s9-p2@22a { + reg = <0x22a 0x2>; + bits = <5 6>; + }; + + tsens_s10_p1: s10-p1@22b { + reg = <0x22b 0x2>; + bits = <3 6>; + }; + + tsens_s10_p2: s10-p2@22c { + reg = <0x22c 0x1>; + bits = <1 6>; }; }; @@ -492,8 +613,32 @@ tsens: thermal-sensor@4a9000 { <0x004a8000 0x1000>; /* SROT */ interrupts = ; interrupt-names = "uplow"; - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; From patchwork Sun Jan 1 19:40:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7886EC54EBE for ; Sun, 1 Jan 2023 19:41:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231604AbjAATlI (ORCPT ); Sun, 1 Jan 2023 14:41:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231688AbjAATk7 (ORCPT ); Sun, 1 Jan 2023 14:40:59 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D86DC1111 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:51 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 18/20] arm64: dts: qcom: qcs404: specify per-sensor calibration cells Date: Sun, 1 Jan 2023 21:40:32 +0200 Message-Id: <20230101194034.831222-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 145 ++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..84ff9df2b904 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -366,13 +366,126 @@ qfprom: qfprom@a4000 { reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + + tsens_s0_p1: s0-p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + + tsens_s9_p1: s9-p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; + cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -447,8 +560,30 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; #qcom,sensors = <10>; interrupts = ; interrupt-names = "uplow"; From patchwork Sun Jan 1 19:40:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E444C54EBC for ; Sun, 1 Jan 2023 19:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbjAATlJ (ORCPT ); Sun, 1 Jan 2023 14:41:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231670AbjAATk7 (ORCPT ); Sun, 1 Jan 2023 14:40:59 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7614B3 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:52 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 19/20] ARM: dts: qcom-msm8974: specify per-sensor calibration cells Date: Sun, 1 Jan 2023 21:40:33 +0200 Message-Id: <20230101194034.831222-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8974.dtsi | 313 +++++++++++++++++++++++++++- 1 file changed, 307 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8d216a3c0851..e28e7a66cf97 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1119,8 +1119,60 @@ tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow"; @@ -1137,11 +1189,260 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; From patchwork Sun Jan 1 19:40:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13086470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13FBCC3DA7D for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w11-20020a056512098b00b004a100c21eaesm4228013lft.97.2023.01.01.11.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 11:40:53 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 20/20] ARM: dts: qcom-apq8084: specify per-sensor calibration cells Date: Sun, 1 Jan 2023 21:40:34 +0200 Message-Id: <20230101194034.831222-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> References: <20230101194034.831222-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8084.dtsi | 313 +++++++++++++++++++++++++++- 1 file changed, 307 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fe30abfff90a..400f865b0ebe 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -249,11 +249,260 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -261,8 +510,60 @@ tsens: thermal-sensor@fc4a8000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow";