From patchwork Tue Jan 3 21:03:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73401C4708E for ; Tue, 3 Jan 2023 21:04:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 58D5FC43396; Tue, 3 Jan 2023 21:04:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DAFADC4339B; Tue, 3 Jan 2023 21:04:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779863; bh=ppRajYsT/OkWemwsA6MQ9TF4kq9Xu8/VtdPDy+LZ+1E=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=btqUvpWk0jN8E0FQWXtS5yhvcKWEsbBwbme7+8TaK/EZQznLECO2SRcJ2qLmQMUql 8dnwoLUx+n+XtT8gEFx9M8b8dcfjEvTwiieT9shrOWLeq33qmunnD7ohDyjGIwq9R5 Xdq8dgoWUY2PX0ox0mwLi9x1CF0+OkobOL2XWQkMdL5lHGQTTVYvfliv/V6g5Zqf5y JoCbGNJp+YlwvYqwguEnRBNoPyRPW5ea+tQWftx+h+miukQJbeZaWjLtJGgGusxwiR oZuIfcrzneC+gt3WCPNFZV0eWB/dgo1YcZ7540J3MRtAuRHxSglnD4EPJ6mTx2NpoY DBK5mcbJrrOMw== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org, Heiko Stuebner Subject: [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Date: Tue, 3 Jan 2023 21:03:53 +0000 Message-Id: <20230103210400.3500626-2-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5020; i=conor.dooley@microchip.com; h=from:subject; bh=JKUr3UqrXzYF8otetDw2MSRIpTRoFJbXZCf7mQF+Ggc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZlhc5+auLbi4Ucsj+8QDsSemPfERCYF/TsY4B71m7N7h mPOvo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABNx+cbIsNz3o8+h1283Gxcttn575X fFy/fsf4Uq7hVO25gYYZ/CLMXwh7/4BrdH0ZdLS+U6rCZGNHtmz2Ji3TJF7nU362mub78qmAE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Lad Prabhakar Introduce ALTERNATIVE_3() macro. A vendor wants to replace an old_content, but another vendor has used ALTERNATIVE_2() to patch its customized content at the same location. In this case, this vendor can use macro ALTERNATIVE_3() and then replace ALTERNATIVE_2() with ALTERNATIVE_3() to append its customized content. While at it update comment above ALTERNATIVE_2() macro and make it generic so that the comment holds good for any new addition of ALTERNATIVE_X() macros. Signed-off-by: Lad Prabhakar Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/include/asm/alternative-macros.h | 46 ++++++++++++++++++--- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 7226e2462584..a5b4691520da 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -50,8 +50,17 @@ ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2 .endm +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ + new_c_2, vendor_id_2, errata_id_2, enable_2, \ + new_c_3, vendor_id_3, errata_id_3, enable_3 + ALTERNATIVE_CFG_2 \old_c, \new_c_1, \vendor_id_1, \errata_id_1, \enable_1, \ + \new_c_2, \vendor_id_2, \errata_id_2, \enable_2 + ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3 +.endm + #define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__ #define __ALTERNATIVE_CFG_2(...) ALTERNATIVE_CFG_2 __VA_ARGS__ +#define __ALTERNATIVE_CFG_3(...) ALTERNATIVE_CFG_3 __VA_ARGS__ #else /* !__ASSEMBLY__ */ @@ -98,6 +107,13 @@ __ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1) \ ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2) +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ + new_c_2, vendor_id_2, errata_id_2, enable_2, \ + new_c_3, vendor_id_3, errata_id_3, enable_3) \ + __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ + new_c_2, vendor_id_2, errata_id_2, enable_2) \ + ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3) + #endif /* __ASSEMBLY__ */ #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ @@ -108,6 +124,13 @@ __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1), \ new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2)) +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \ + new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2, \ + new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3) \ + __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1), \ + new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2), \ + new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3)) + #else /* CONFIG_RISCV_ALTERNATIVE */ #ifdef __ASSEMBLY__ @@ -152,15 +175,28 @@ _ALTERNATIVE_CFG(old_content, new_content, vendor_id, errata_id, CONFIG_k) /* - * A vendor wants to replace an old_content, but another vendor has used - * ALTERNATIVE() to patch its customized content at the same location. In - * this case, this vendor can create a new macro ALTERNATIVE_2() based - * on the following sample code and then replace ALTERNATIVE() with - * ALTERNATIVE_2() to append its customized content. + * ALTERNATIVE_x macros allow providing multiple replacement options + * for an ALTERNATIVE code section. This is helpful if multiple + * implementation variants for the same functionality exist for + * different cpu cores. + * + * Usage: + * ALTERNATIVE_x(old_content, + * new_content1, vendor_id1, errata_id1, CONFIG_k1, + * new_content2, vendor_id2, errata_id2, CONFIG_k2, + * ... + * new_contentx, vendor_idx, errata_idx, CONFIG_kx) */ #define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \ new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2) \ _ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \ new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2) +#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \ + new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2, \ + new_content_3, vendor_id_3, errata_id_3, CONFIG_k_3) \ + _ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1, \ + new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2, \ + new_content_3, vendor_id_3, errata_id_3, CONFIG_k_3) + #endif From patchwork Tue Jan 3 21:03:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16B08C3DA7D for ; Tue, 3 Jan 2023 21:04:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id ED93AC433D2; Tue, 3 Jan 2023 21:04:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ADADDC433F0; Tue, 3 Jan 2023 21:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779868; bh=QSwhmc0AtnN+kg4QEPChJJlwqa5GiZOtsjO1T4tiafU=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=gahn5TXp0pv4DADwXee6Mn+jsEOVYGhnzhvjpsra92mG3INiwY1WpAmFmlQujmQgx dwJ4x0Zq3xsP0dxq6pQoIK7G3EYzi0tb525LaNoDs+Ukxde/PugsXMRSAEb9JDUGA8 EkuYeL2/yBlFO8QM5dUAZ1CoyfXQamVmNv4EhItxTC3Zy3SyxN7f9jXOQb3DvyhvJT +y9Qayp/RfPJtI4TZ+h8gsRmIm+twuKu7HuGXDnujLzgWsIgZcvjpqOjo8Ocr52Q1o EkPo5ZZrRQPzTL8QYqzH7G5JdVC0yoUyb70M5zs1FCt2XI7ZibUV0nHfCBYQ35xxUz h5xL3I5wlMZFA== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Date: Tue, 3 Jan 2023 21:03:54 +0000 Message-Id: <20230103210400.3500626-3-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=786; i=conor.dooley@microchip.com; h=from:subject; bh=Osu6oqnweQTcBtWUqRBfzd67X6PnKxWx7JZhKp2CLGI=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZljM3J3wZI23c0fvxVt/3Xz+p6/+FiJb931jSsBejlWP 560+01HKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJdGYzMjQtPv2679FSl/WSy18sKF aQLSq3P2Sxa6uFalkLn+qnaeqMDNc4xE5pSqiv2Jf1otuxTuL0bKPHEVmJfGXLta5VfmA15wYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Lad Prabhakar Add Andes Technology to the vendors list. Signed-off-by: Lad Prabhakar Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/include/asm/vendorid_list.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index cb89af3f0704..e55407ace0c3 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -5,6 +5,7 @@ #ifndef ASM_VENDOR_LIST_H #define ASM_VENDOR_LIST_H +#define ANDESTECH_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 From patchwork Tue Jan 3 21:03:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0BEFC3DA7D for ; Tue, 3 Jan 2023 21:04:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 97AD4C433F0; Tue, 3 Jan 2023 21:04:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F9F7C4339B; Tue, 3 Jan 2023 21:04:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779874; bh=Dprtt2wF+NQ6SFZu7LTN8Uj8OXvpK3xyWL0QoGrvAoA=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=oFgdGWiLzkHWlvMjV80WzM61DUgIBEyOssLRzqjVpdgrVPratzuquppyS3iPHjiTj L1v/1cNQg8ioGIEEhtQrs+UyTDl7iHjmZax/+N0RD397I5kTsUssLJESJJX/RAqgJr ITtf4JHnfnMkJPyQzO5Qmq0Z5f8882pf7hA81Hrep1Db2TvAskKh6YEWpMP61XqUBC 2HnUS+gGNNkZkbL5nT3C4q7OaPSS6qTEIiytUu37kXkeKPP4bKc351Aq+uVb4ts4Gq /sGZh5ub00hYneBh50DUoTK2Awh92M40bhthQnPSjAnGUg8hRGUMqsEqMi91aoaw+b qZ3AIVa/W31fA== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Date: Tue, 3 Jan 2023 21:03:55 +0000 Message-Id: <20230103210400.3500626-4-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7075; i=conor.dooley@microchip.com; h=from:subject; bh=00UtI+q6z/vXb7iVXyA4KCXaUC3/5LYAlPRoaCVv1lk=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZljo5gX2i5jl/jPZcS35vcjC0xHtLQHlesdMuk+t/Oj9 V0+oo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABO5eonhf25+BPuXvd+Of5katHr9zq pgToWa6Ydq4pa9FrPaNFF/fgvD/9KjDvtOJJSnznni2Hrud4/U31VNZc91tlr3LulZa9HWxwAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Lad Prabhakar Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.erratas | 22 +++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 93 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/errata_list.h | 5 ++ arch/riscv/kernel/alternative.c | 5 ++ 7 files changed, 130 insertions(+) create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 69621ae6d647..f0f0c1abd52b 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,5 +1,27 @@ menu "CPU errata selection" +config ERRATA_ANDES + bool "Andes AX45MP errata" + depends on !XIP_KERNEL + select RISCV_ALTERNATIVE + help + All Andes errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all Andes errata. Please say "Y" + here if your platform uses Andes CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_ANDES_CMO + bool "Apply Andes cache management errata" + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on Andes cores. + + If you don't know what to do here, say "Y". + config ERRATA_SIFIVE bool "SiFive errata" depends on !XIP_KERNEL diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index a1055965fbee..6f1c693af92d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_ERRATA_ANDES) += andes/ obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ obj-$(CONFIG_ERRATA_THEAD) += thead/ diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Makefile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/andes/Makefile @@ -0,0 +1 @@ +obj-y += errata.o diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c new file mode 100644 index 000000000000..3d04f15df8d5 --- /dev/null +++ b/arch/riscv/errata/andes/errata.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for Andes CPU cores + * + * Copyright (C) 2022 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDESTECH_AX45MP_MIMPID 0x500UL +#define ANDESTECH_SBI_EXT_ANDES 0x0900031E + +#define RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND 0 + +static long ax45mp_iocp_sw_workaround(void) +{ + struct sbiret ret; + + ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND, + 0, 0, 0, 0, 0, 0); + + return ret.error ? 0 : ret.value; +} + +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) + return false; + + if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) + return false; + + if (!ax45mp_iocp_sw_workaround()) + return false; + + /* Set this just to make core cbo code happy */ + riscv_cbom_block_size = 1; + riscv_noncoherent_supported(); + + return true; +} + +static u32 andes_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) +{ + u32 cpu_req_errata = 0; + + /* + * In the absence of the I/O Coherency Port, access to certain peripherals + * requires vendor specific DMA handling. + */ + if (errata_probe_iocp(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_ANDESTECH_NO_IOCP); + + return cpu_req_errata; +} + +void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + u32 cpu_req_errata = andes_errata_probe(stage, archid, impid); + struct alt_entry *alt; + u32 tmp; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt = begin; alt < end; alt++) { + if (alt->vendor_id != ANDESTECH_VENDOR_ID) + continue; + if (alt->errata_id >= ERRATA_ANDESTECH_NUMBER) + continue; + + tmp = BIT(alt->errata_id); + if (cpu_req_errata & tmp) { + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + + riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, + alt->old_ptr - alt->alt_ptr); + } + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 1bd4027d34ca..e3a8e603eb5a 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -43,6 +43,9 @@ struct errata_checkfunc_id { bool (*func)(struct alt_entry *alt); }; +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 4180312d2a70..2ba7e6e74540 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -9,6 +9,11 @@ #include #include +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDESTECH_NO_IOCP 0 +#define ERRATA_ANDESTECH_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_SIFIVE #define ERRATA_SIFIVE_CIP_453 0 #define ERRATA_SIFIVE_CIP_1200 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 6212ea0eed72..d7027a977ee6 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -40,6 +40,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(struct cpu_manufacturer_inf #endif switch (cpu_mfr_info->vendor_id) { +#ifdef CONFIG_ERRATA_ANDES + case ANDESTECH_VENDOR_ID: + cpu_mfr_info->patch_func = andes_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func = sifive_errata_patch_func; From patchwork Tue Jan 3 21:03:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51A70C3DA7D for ; Tue, 3 Jan 2023 21:04:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 3A560C433D2; Tue, 3 Jan 2023 21:04:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC7F1C433EF; Tue, 3 Jan 2023 21:04:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779880; bh=bttnpUl6BCbE/q8KnOj1xu1MAvPXwKnVgzNXk3Zdw1U=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=ehLSXd8BDiBlDNlrSH0ntTP5uuxPr/+QIyBR2Sb4rQbPOQO9IOKFWmRY5fjcxgeJs nOKybp0XvjxJTOMcOTF714uDtv8Fw0SkqRthGiEZVQUIm44LnrcxLmXiKfVpcpLUan QqC66vdlmlBaRD/LBx8NEOd13h99It7Y3jfouf1pI97RjLTaN9rVwPE2zvviT4ly4O ha0RJj6bmrMr4Ibe5bOPXtL/hT0+xllulYtG5yPjk+9PXIYnspqxqHLfdpvgiXF8Uq QW+pE8sdSVm3yYwCuXL3Xcv2wSwcGfNMnC8Weq27qGNat91z+1mQgju5fRnIeEJ8J7 UsSdaoizTp1vg== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Date: Tue, 3 Jan 2023 21:03:56 +0000 Message-Id: <20230103210400.3500626-5-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4711; i=conor.dooley@microchip.com; h=from:subject; bh=5zfzekcxdW4CVPyyS9wITNvNNLsIZnhw4rmXAoz+xFo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZlgkO0Rd3O8yMSrsS+iOuE3fPmR9s34mIGRxxD6Ku1Z7 5bmkjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzk4ktGhl81R/Q4Lv/2/rs57ZJQvr VOwcmDsvXXkueY8125c3ya6ESGv4KXtp571sCyKcpi8ifvSeddPPm//b288Uv2w3M7BDvbN3MCAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Lad Prabhakar Pass direction and operation to ALT_CMO_OP() macro. Vendors might want to perform different operations based on the direction and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/ arch_dma_prep_coherent) so to handle such cases pass the direction and operation to ALT_CMO_OP() macro. This is in preparation for adding errata for the Andes CPU core. Signed-off-by: Lad Prabhakar [Conor: blindy & incorrectly "fixed" pmem compilation. I've not even tried to use the defines.] Signed-off-by: Conor Dooley --- arch/riscv/include/asm/cacheflush.h | 4 ++++ arch/riscv/include/asm/errata_list.h | 8 ++++++-- arch/riscv/mm/dma-noncoherent.c | 15 ++++++++++----- arch/riscv/mm/pmem.c | 4 ++-- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 03e3b95ae6da..e22019668b9e 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -8,6 +8,10 @@ #include +#define NON_COHERENT_SYNC_DMA_FOR_DEVICE 0 +#define NON_COHERENT_SYNC_DMA_FOR_CPU 1 +#define NON_COHERENT_DMA_PREP 2 + static inline void local_flush_icache_all(void) { asm volatile ("fence.i" ::: "memory"); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 2ba7e6e74540..48e899a8e7a9 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \ #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ asm volatile(ALTERNATIVE_2( \ __nops(6), \ "mv a0, %1\n\t" \ @@ -146,7 +146,11 @@ asm volatile(ALTERNATIVE_2( \ ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ - "r"((unsigned long)(_start) + (_size)) \ + "r"((unsigned long)(_start) + (_size)), \ + "r"((unsigned long)(_start)), \ + "r"((unsigned long)(_size)), \ + "r"((unsigned long)(_dir)), \ + "r"((unsigned long)(_ops)) \ : "a0") #define THEAD_C9XX_RV_IRQ_PMU 17 diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d919efab6eba..e2b82034f504 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -19,13 +19,16 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, switch (dir) { case DMA_TO_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); break; case DMA_FROM_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); break; case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE); break; default: break; @@ -42,7 +45,8 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, break; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size, + dir, NON_COHERENT_SYNC_DMA_FOR_CPU); break; default: break; @@ -53,7 +57,8 @@ void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size, + 0, NON_COHERENT_DMA_PREP); } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c index 089df92ae876..4233e28d8611 100644 --- a/arch/riscv/mm/pmem.c +++ b/arch/riscv/mm/pmem.c @@ -10,12 +10,12 @@ void arch_wb_cache_pmem(void *addr, size_t size) { - ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size, 0, 0); } EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); void arch_invalidate_pmem(void *addr, size_t size) { - ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); + ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size, 0, 0); } EXPORT_SYMBOL_GPL(arch_invalidate_pmem); From patchwork Tue Jan 3 21:03:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C2F0C4708E for ; Tue, 3 Jan 2023 21:04:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 054E1C433D2; Tue, 3 Jan 2023 21:04:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90EE1C4339B; Tue, 3 Jan 2023 21:04:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779885; bh=TeAvLOxoTQn0nEJ8uC/RQuHSguklAU7dAQ8PGikIe1k=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=MhUPuJn/Xjsx8N902zoaJrDyyq63z0xd8hZ3ieh/ygqPuVkviZArgP2PlH79lxrO0 pnVofL6HYScy4RthNjLTbcwliMDmfgfq73fwC/i2ax/E+ux9sedQg/ZniVAGryAnd2 n2q9oB3tdYS7+sYLhoqldZkGQFeP1Lo/4v1Xc0wf52XzcsLrdu38+HSCqcdda/XcNJ /MJJ2IW55CwUSUN1g7VA3j606iFUUy64slgH7Osts6lgEazFPxjAzI3KLrt/6LXqgH qxB5UpYDSFsg19xmOJKrBCmc8umTngQZTRvkc7dgQjMotIzhZ6MMe1xhlUOsqTzoCS mzX/LbQLB+qLA== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org, Rob Herring Subject: [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Date: Tue, 3 Jan 2023 21:03:57 +0000 Message-Id: <20230103210400.3500626-6-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2784; i=conor.dooley@microchip.com; h=from:subject; bh=ojZMybQ173ye6s1UxliDW9zuCUAcQZtR9biIzGoAxqw=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZlgwK0gqekWu0U6fXJT9YNpboQQfub5VkpsjrFsWlzMa hG3uKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwEQUOhj+SrXZeYbtvG116jZr7aHWE+ bRCXy2uQxtOgHcf4uj0r6vYWS4fTXBwVzVsyXUjOt34vUDIY8U1ffcv8nzyKyAwcHg/gQeAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Lad Prabhakar Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Signed-off-by: Conor Dooley --- .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9f0be4835ad7 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a large amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include + + cache-controller@2010000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x13400000 0x100000>; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + }; From patchwork Tue Jan 3 21:03:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1B68C3DA7D for ; Tue, 3 Jan 2023 21:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 98F1FC433F2; Tue, 3 Jan 2023 21:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BAA1C433EF; Tue, 3 Jan 2023 21:04:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779891; bh=gbW76aZ9HGuqGjsmnFp+/NvAvQvLy+7M6AdSPdrCtKo=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=LcC0yCDwMR7PZS0esb/VHxJezgq0SJORsh+B/QxOrs3kw816IdMvDu4g1/v2jnudn PJFoGUxSYfNCCVmNuurLtMNHvExWnzAExsIY1sQ4WN7x7l5Ow/xMdLdZdeTt2kP37z SkzzgyceMgfJqgdtlUv2Xhw7Kd5GCaXn+8mIjhty3L9C70/HR+X5F5cmTOCpnGlYSL lTixXFvNVUNFjenqZzqmge8fiEeS+/7Y1XZDvO7qg4SmlP2ISTcoeVYnwGCKPj4GoZ UFsWy1wrxHFLM+3vRptn992u2cyIVPRp/DYbzsL2oSJIsMQBsbyYsPAMQlrSGI8U8d xkPP8eBdsMFxA== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Date: Tue, 3 Jan 2023 21:03:58 +0000 Message-Id: <20230103210400.3500626-7-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5910; i=conor.dooley@microchip.com; h=from:subject; bh=HN4eTseXEkj6xdKUBkDIWyi7p3BRkjUx7UVap+uWM7c=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZlimT2H/ufuDGW9yvuhPtqefzqla/Ul4EaH8kj/1YmVy 3v+ujlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExE4h3Df79W78b81JfScx0W2/bemn 71WZxH6gq1Bb9mP1awWFgblMDwP6nidsr+W37aDXOL5MyfTkidEsV19VzQFGnX3BWyEb5inAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The Zicbo* set of extensions for cache maintenance arrived too late & several SoCs exist without them that require non-coherent DMA. As things stand, the StarFive JH7100, Microchip PolarFire SoC & Renesas RZ/Five all require cache maintenance and lack instructions for this purpose. Create a subsystem for cache drivers so that vendor specific behaviour can be isolated from arch code, but keep the interfaces etc consistent. Move the existing SiFive CCache driver to create drivers/cache. Signed-off-by: Conor Dooley --- MAINTAINERS | 15 ++++++++------- drivers/Kconfig | 2 ++ drivers/Makefile | 2 ++ drivers/{soc/sifive => cache}/Kconfig | 8 +++++++- drivers/{soc/sifive => cache}/Makefile | 0 drivers/{soc/sifive => cache}/sifive_ccache.c | 2 +- drivers/edac/sifive_edac.c | 2 +- drivers/soc/Kconfig | 1 - drivers/soc/Makefile | 1 - include/{soc/sifive => cache}/sifive_ccache.h | 0 10 files changed, 21 insertions(+), 12 deletions(-) rename drivers/{soc/sifive => cache}/Kconfig (56%) rename drivers/{soc/sifive => cache}/Makefile (100%) rename drivers/{soc/sifive => cache}/sifive_ccache.c (99%) rename include/{soc/sifive => cache}/sifive_ccache.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..4437e96a657b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19054,13 +19054,6 @@ S: Maintained F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml F: drivers/dma/sf-pdma/ -SIFIVE SOC DRIVERS -M: Conor Dooley -L: linux-riscv@lists.infradead.org -S: Maintained -T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ -F: drivers/soc/sifive/ - SILEAD TOUCHSCREEN DRIVER M: Hans de Goede L: linux-input@vger.kernel.org @@ -19873,6 +19866,14 @@ S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git F: drivers/staging/ +STANDALONE CACHE CONTROLLER DRIVERS +M: Conor Dooley +L: linux-riscv@lists.infradead.org +S: Maintained +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: drivers/cache +F: include/cache + STARFIRE/DURALAN NETWORK DRIVER M: Ion Badulescu S: Odd Fixes diff --git a/drivers/Kconfig b/drivers/Kconfig index 968bd0a6fd78..e592ba5276ae 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -241,4 +241,6 @@ source "drivers/peci/Kconfig" source "drivers/hte/Kconfig" +source "drivers/cache/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index bdf1c66141c9..6ff60cf21823 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -38,6 +38,8 @@ obj-y += clk/ # really early. obj-$(CONFIG_DMADEVICES) += dma/ +obj-y += cache/ + # SOC specific infrastructure drivers. obj-y += soc/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/cache/Kconfig similarity index 56% rename from drivers/soc/sifive/Kconfig rename to drivers/cache/Kconfig index ed4c571f8771..bc852f005c10 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/cache/Kconfig @@ -1,9 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 -if SOC_SIFIVE +menuconfig CACHE_CONTROLLER + bool "Cache controller driver support" + default y if RISCV + +if CACHE_CONTROLLER config SIFIVE_CCACHE bool "Sifive Composable Cache controller" + depends on RISCV + default y help Support for the composable cache controller on SiFive platforms. diff --git a/drivers/soc/sifive/Makefile b/drivers/cache/Makefile similarity index 100% rename from drivers/soc/sifive/Makefile rename to drivers/cache/Makefile diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/cache/sifive_ccache.c similarity index 99% rename from drivers/soc/sifive/sifive_ccache.c rename to drivers/cache/sifive_ccache.c index 3684f5b40a80..47e7d6557f85 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 #define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index b844e2626fd5..9276839d58c2 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -10,7 +10,7 @@ #include #include #include "edac_module.h" -#include +#include #define DRVNAME "sifive_edac" diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 5dbb09f843f7..240455963565 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -21,7 +21,6 @@ source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" -source "drivers/soc/sifive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index fff513bd522d..9ed2e27bbb64 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -27,7 +27,6 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ -obj-$(CONFIG_SOC_SIFIVE) += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/include/soc/sifive/sifive_ccache.h b/include/cache/sifive_ccache.h similarity index 100% rename from include/soc/sifive/sifive_ccache.h rename to include/cache/sifive_ccache.h From patchwork Tue Jan 3 21:03:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 506A5C3DA7D for ; Tue, 3 Jan 2023 21:04:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 39CA4C433D2; Tue, 3 Jan 2023 21:04:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EEE0DC4339C; Tue, 3 Jan 2023 21:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779897; bh=NVIPLNYadwmjyO6vDZQxAZdtNdwO+ess1cn15D0qw2s=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=SkkSGtF1vkXkWTJNQJm22SXWH2CUOczc5Mshw5+BvXm1WkFJukw4CKrnQeaYHDbCI 9Fg59EwtsGD2Bo+bMqf4Dt3vFOQlLTBa8UCxS6uDVkfEbE7qj0SkUbPhwtoSQHHM9x xFowfTASYWM9JB/kuYwuDXFsGzna1YItCCGeCGEr/sYAivnXJ4X4XGZeFy+F3Rv4Qc bIX+JN2ytWpJgsONwursvqauYalnaNgemd2NGju6nCoz6+co4qTAQUGekm00Y64GKP wQrxGcS0Q0xO9TS1NvqG9UA7dHhXNTjDmbDHPap/cNtmNPTYJhVErrSlWpRUBXEMnb 9RCahHg6uXXvQ== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 7/9] RISC-V: create a function based cache management interface Date: Tue, 3 Jan 2023 21:03:59 +0000 Message-Id: <20230103210400.3500626-8-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3722; i=conor.dooley@microchip.com; h=from:subject; bh=KCrSQFVyUXaCXRh9Hgy+cOwp3MiY7fZYkk/trWQ+OXo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZljaNOUW+m1dw/mg+7tU0rLz1xoOTOQuj1Pu4E9ZXdDG 9mF3RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYSY8/I0HvvZ8td23t/0yZHTVzx3V bzz+yTr4o1P2uIfprRkR8ec4aRoVGVy+hDQsWL0LRp2lOmqtT7fFG8smWjaPRGh/bihdOvsQEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The Zicbo* set of extensions for cache maintenance arrived too late & several SoCs exist without them that require non-coherent DMA. As things stand, the StarFive JH7100, Microchip PolarFire SoC & Renesas RZ/Five all require cache maintenance and lack instructions for this purpose. Similar to the interface already used by the SiFive CCache driver to add cacheinfo_ops, create an interface for registering cache management functions for a given cache controller. Signed-off-by: Conor Dooley --- Yes, I made the cmo_patchfunc() __maybe_unused to escape LKP complaints. The other option that Prabhakar mentioned was having explicit functions for each of the operations, in which case I cmo_patchfunc() would go away. I don't particularly like the name of that function, so any suggestions there would be great! --- arch/riscv/Kconfig.erratas | 4 ++++ arch/riscv/include/asm/cacheflush.h | 19 +++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 21 +++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index f0f0c1abd52b..b8542e6e8f18 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,5 +1,8 @@ menu "CPU errata selection" +config ERRATA_CMO_FUNC + bool + config ERRATA_ANDES bool "Andes AX45MP errata" depends on !XIP_KERNEL @@ -14,6 +17,7 @@ config ERRATA_ANDES config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select ERRATA_CMO_FUNC select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index e22019668b9e..795205ec2028 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -62,6 +62,25 @@ void riscv_noncoherent_supported(void); static inline void riscv_noncoherent_supported(void) {} #endif +struct riscv_cache_maint_ops { + void (*cmo_patchfunc) (unsigned int cache_size, void *vaddr, + size_t size, int dir, int ops); +}; + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops); +#else +static void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops) {} +#endif + +#ifdef CONFIG_ERRATA_CMO_FUNC +asmlinkage void cmo_patchfunc(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops); +#else +__maybe_unused static void cmo_patchfunc(unsigned int cache_size, void *vaddr, + size_t size, int dir, int ops) {} +#endif + /* * Bits in sys_riscv_flush_icache()'s flags argument. */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index e2b82034f504..2f4f147ea0b9 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -83,3 +83,24 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +static struct riscv_cache_maint_ops *rv_cache_maint_ops; +static DEFINE_STATIC_KEY_FALSE(cmo_patchfunc_present); + +void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops) +{ + rv_cache_maint_ops = ops; + static_branch_enable(&cmo_patchfunc_present); +} +EXPORT_SYMBOL_GPL(riscv_set_cache_maint_ops); + +#ifdef CONFIG_ERRATA_CMO_FUNC +asmlinkage void cmo_patchfunc(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops) +{ + if (!static_branch_unlikely(&cmo_patchfunc_present)) + return; + + rv_cache_maint_ops->cmo_patchfunc(cache_size, vaddr, size, dir, ops); +} +#endif From patchwork Tue Jan 3 21:04:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E896EC3DA7D for ; Tue, 3 Jan 2023 21:05:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id CFEC5C43392; Tue, 3 Jan 2023 21:05:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90B55C433EF; Tue, 3 Jan 2023 21:04:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779902; bh=JSvers6ooGj7S89bt0SV5sdIoChbgErqxdTQvu7gK5U=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=GebX3SAxQluwud3ZPlEcg0kkeorC+KoKK01hemyEScmZJ45JBQM06Lj5XsCBVB+tI cQAMScwqzcuAnjO4e3shm7Z9/lek8237K6YQIr3bblOy2XnGKt0ySwNLuxZG/YKBWQ p8QUXXHmPKl83jPsfGe2RsvTWofd5XvoxdYA+crJz172IiCj/x/+ZXn0QnblIaNM+R mpZCkPlbJ/giCK3SpU2ykIJK3zKr4xtawCwaQ1PTxHVZ6PD5R/U7+WrG5XluQOkRsm QsN2uEawFZIo2fzoA9vE0+Ri7I90BAp0kqMQSFeZfjvA4JsM/uQwzqeU9MctMED5OM bapMqpu5x015A== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Date: Tue, 3 Jan 2023 21:04:00 +0000 Message-Id: <20230103210400.3500626-9-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=13665; i=conor.dooley@microchip.com; h=from:subject; bh=UgbJwiazn4htwD36u3aLhV+P7EIpC/n0AX0SnME6DEg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZlhuqry5P+Xl8Xcf+VVk5h874LB3YpNVk0+piOXB2BIb Q7NvHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhI/iRGhm2m8jeEtvZ5Phe4/WK9pl 9ApnTMad2G/up+EZ6GNfbR2Qz/FB+YCbq/EfGe+GY1m3lfdePZyIvWryuSal78m+WnxXeQAQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Lad Prabhakar I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar [Conor: moved the driver to drivers/cache] Signed-off-by: Conor Dooley --- arch/riscv/include/asm/errata_list.h | 28 ++- drivers/cache/Kconfig | 9 + drivers/cache/Makefile | 2 + drivers/cache/ax45mp_cache.c | 253 +++++++++++++++++++++++++++ drivers/soc/renesas/Kconfig | 4 + 5 files changed, 290 insertions(+), 6 deletions(-) create mode 100644 drivers/cache/ax45mp_cache.c diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 48e899a8e7a9..7636b83c1ecb 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -125,8 +125,8 @@ asm volatile(ALTERNATIVE( \ #define THEAD_SYNC_S ".long 0x0190000b" #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ -asm volatile(ALTERNATIVE_2( \ - __nops(6), \ +asm volatile(ALTERNATIVE_3( \ + __nops(14), \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ @@ -134,7 +134,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + __nops(9), 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ @@ -142,8 +142,24 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - THEAD_SYNC_S, THEAD_VENDOR_ID, \ - ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ + THEAD_SYNC_S "\n\t" \ + __nops(8), THEAD_VENDOR_ID, \ + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO, \ + "addi sp,sp,-16\n\t" \ + "sd s0,0(sp)\n\t" \ + "sd ra,8(sp)\n\t" \ + "addi s0,sp,16\n\t" \ + "mv a4,%6\n\t" \ + "mv a3,%5\n\t" \ + "mv a2,%4\n\t" \ + "mv a1,%3\n\t" \ + "mv a0,%0\n\t" \ + "call cmo_patchfunc\n\t" \ + "ld ra,8(sp)\n\t" \ + "ld s0,0(sp)\n\t" \ + "addi sp,sp,16\n\t", \ + ANDESTECH_VENDOR_ID, ERRATA_ANDESTECH_NO_IOCP, \ + CONFIG_ERRATA_ANDES_CMO) \ : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ "r"((unsigned long)(_start) + (_size)), \ @@ -151,7 +167,7 @@ asm volatile(ALTERNATIVE_2( \ "r"((unsigned long)(_size)), \ "r"((unsigned long)(_dir)), \ "r"((unsigned long)(_ops)) \ - : "a0") + : "a0", "a1", "a2", "a3", "a4", "memory") #define THEAD_C9XX_RV_IRQ_PMU 17 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index bc852f005c10..e3309a668d1b 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -6,6 +6,15 @@ menuconfig CACHE_CONTROLLER if CACHE_CONTROLLER +config AX45MP_L2_CACHE + bool "Andes Technology AX45MP L2 Cache controller" + depends on RISCV + depends on RISCV_SBI + default y + help + Support for the L2 cache controller on Andes Technology AX45MP + platforms. + config SIFIVE_CCACHE bool "Sifive Composable Cache controller" depends on RISCV diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 1f5dc339bf82..f175d16d8611 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c new file mode 100644 index 000000000000..a488b85b9eea --- /dev/null +++ b/drivers/cache/ax45mp_cache.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * non-coherent cache functions for Andes AX45MP + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +#include +#include + +/* L2 cache registers */ +#define AX45MP_L2C_REG_CTL_OFFSET 0x8 + +#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40 +#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48 +#define AX45MP_L2C_REG_STATUS_OFFSET 0x80 + +/* D-cache operation */ +#define AX45MP_CCTL_L1D_VA_INVAL 0 +#define AX45MP_CCTL_L1D_VA_WB 1 + +/* L2 CCTL status */ +#define AX45MP_CCTL_L2_STATUS_IDLE 0 + +/* L2 CCTL status cores mask */ +#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf + +/* L2 cache operation */ +#define AX45MP_CCTL_L2_PA_INVAL 0x8 +#define AX45MP_CCTL_L2_PA_WB 0x9 + +#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10 +#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4 + +#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \ + (AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET)) +#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \ + (AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET)) +#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \ + (AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET)) + +#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b +#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c + +#define AX45MP_CACHE_LINE_SIZE 64 + +struct ax45mp_priv { + void __iomem *l2c_base; + u32 ax45mp_cache_line_size; +}; + +static struct ax45mp_priv *ax45mp_priv; +static struct riscv_cache_maint_ops ax45mp_cmos; + +/* L2 Cache operations */ +static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void) +{ + return readl(ax45mp_priv->l2c_base + AX45MP_L2C_REG_STATUS_OFFSET); +} + +/* + * Software trigger CCTL operation (cache maintenance operations) by writing + * to ucctlcommand and ucctlbeginaddr registers and write-back an L2 cache + * entry. + */ +static void ax45mp_cpu_dcache_wb_range(void *start, void *end, int line_size) +{ + void __iomem *base = ax45mp_priv->l2c_base; + int mhartid = smp_processor_id(); + unsigned long pa; + + while (end > start) { + csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start); + csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, AX45MP_CCTL_L1D_VA_WB); + + pa = virt_to_phys(start); + writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid)); + writel(AX45MP_CCTL_L2_PA_WB, + base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid)); + while ((ax45mp_cpu_l2c_get_cctl_status() & + AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) != + AX45MP_CCTL_L2_STATUS_IDLE) + ; + + start += line_size; + } +} + +/* + * Software trigger CCTL operation by writing to ucctlcommand and ucctlbeginaddr + * registers and invalidate the L2 cache entry. + */ +static void ax45mp_cpu_dcache_inval_range(void *start, void *end, int line_size) +{ + void __iomem *base = ax45mp_priv->l2c_base; + int mhartid = smp_processor_id(); + unsigned long pa; + + while (end > start) { + csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start); + csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, AX45MP_CCTL_L1D_VA_INVAL); + + pa = virt_to_phys(start); + writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid)); + writel(AX45MP_CCTL_L2_PA_INVAL, + base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid)); + while ((ax45mp_cpu_l2c_get_cctl_status() & + AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) != + AX45MP_CCTL_L2_STATUS_IDLE) + ; + + start += line_size; + } +} + +static void ax45mp_cpu_dma_inval_range(void *vaddr, size_t size) +{ + char cache_buf[2][AX45MP_CACHE_LINE_SIZE]; + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; + unsigned long old_start = start; + unsigned long old_end = end; + unsigned long line_size; + unsigned long flags; + + if (unlikely(start == end)) + return; + + line_size = ax45mp_priv->ax45mp_cache_line_size; + + memset(&cache_buf, 0x0, sizeof(cache_buf)); + start = start & (~(line_size - 1)); + end = ((end + line_size - 1) & (~(line_size - 1))); + + local_irq_save(flags); + if (unlikely(start != old_start)) + memcpy(&cache_buf[0][0], (void *)start, line_size); + + if (unlikely(end != old_end)) + memcpy(&cache_buf[1][0], (void *)(old_end & (~(line_size - 1))), line_size); + + ax45mp_cpu_dcache_inval_range(vaddr, (void *)end, line_size); + + if (unlikely(start != old_start)) + memcpy((void *)start, &cache_buf[0][0], (old_start & (line_size - 1))); + + local_irq_restore(flags); +} + +static void ax45mp_cpu_dma_wb_range(void *vaddr, size_t size) +{ + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; + unsigned long line_size; + unsigned long flags; + + line_size = ax45mp_priv->ax45mp_cache_line_size; + local_irq_save(flags); + start = start & (~(line_size - 1)); + ax45mp_cpu_dcache_wb_range(vaddr, (void *)end, line_size); + local_irq_restore(flags); +} + +static void ax45mp_no_iocp_cmo(unsigned int cache_size, void *vaddr, size_t size, int dir, int ops) +{ + if (ops == NON_COHERENT_DMA_PREP) + return; + + if (ops == NON_COHERENT_SYNC_DMA_FOR_DEVICE) { + switch (dir) { + case DMA_FROM_DEVICE: + ax45mp_cpu_dma_inval_range(vaddr, size); + break; + case DMA_TO_DEVICE: + case DMA_BIDIRECTIONAL: + ax45mp_cpu_dma_wb_range(vaddr, size); + break; + default: + break; + } + return; + } + + /* op == NON_COHERENT_SYNC_DMA_FOR_CPU */ + if (dir == DMA_BIDIRECTIONAL || dir == DMA_FROM_DEVICE) + ax45mp_cpu_dma_inval_range(vaddr, size); +} + +static void ax45mp_configure_l2_cache(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + int ret; + + ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv->ax45mp_cache_line_size); + if (ret) { + dev_err(dev, "Failed to get cache-line-size, defaulting to 64 bytes\n"); + ax45mp_priv->ax45mp_cache_line_size = AX45MP_CACHE_LINE_SIZE; + } + + if (ax45mp_priv->ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) { + dev_err(dev, "Expected cache-line-size to be 64 bytes (found:%u). Defaulting to 64 bytes\n", + ax45mp_priv->ax45mp_cache_line_size); + ax45mp_priv->ax45mp_cache_line_size = AX45MP_CACHE_LINE_SIZE; + } +} + +static int ax45mp_l2c_probe(struct platform_device *pdev) +{ + ax45mp_priv = devm_kzalloc(&pdev->dev, sizeof(*ax45mp_priv), GFP_KERNEL); + if (!ax45mp_priv) + return -ENOMEM; + + ax45mp_priv->l2c_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ax45mp_priv->l2c_base)) + return PTR_ERR(ax45mp_priv->l2c_base); + + ax45mp_configure_l2_cache(pdev); + + ax45mp_cmos.cmo_patchfunc = ax45mp_no_iocp_cmo; + riscv_set_cache_maint_ops(&ax45mp_cmos); + + return 0; +} + +static const struct of_device_id ax45mp_cache_ids[] = { + { .compatible = "andestech,ax45mp-cache" }, + { /* sentinel */ } +}; + +static struct platform_driver ax45mp_l2c_driver = { + .driver = { + .name = "ax45mp-l2c", + .of_match_table = ax45mp_cache_ids, + }, + .probe = ax45mp_l2c_probe, +}; + +static int __init ax45mp_cache_init(void) +{ + return platform_driver_register(&ax45mp_l2c_driver); +} +arch_initcall(ax45mp_cache_init); + +MODULE_AUTHOR("Lad Prabhakar "); +MODULE_DESCRIPTION("Andes AX45MP L2 cache driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 660498252ec5..c3475c084685 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -340,6 +340,10 @@ if RISCV config ARCH_R9A07G043 bool "RISC-V Platform support for RZ/Five" select ARCH_RZG2L + select AX45MP_L2_CACHE + select DMA_GLOBAL_POOL + select ERRATA_ANDES + select ERRATA_ANDES_CMO help This enables support for the Renesas RZ/Five SoC. From patchwork Tue Jan 3 21:04:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13088039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B653DC3DA7D for ; Tue, 3 Jan 2023 21:05:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id A1A0AC433EF; Tue, 3 Jan 2023 21:05:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31830C4339B; Tue, 3 Jan 2023 21:05:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672779908; bh=lLEVQzA2tlebT8QA/9LqkjR/b1kC1VTxb7QPcn+rtZ4=; h=From:To:List-Id:Cc:Subject:Date:In-Reply-To:References:From; b=bgGm0ooI7Z7O8S2Kcc9oCnizUQcbqmdnTLhZRgi8QA9WMy12WagUsUxPtcQbAuN4u 4UMDRypjqe+7i/r+FGAOLr+IT+rk0NStICzwVYB9j25put4GtxuWnllBBepIdcqrdo Sd3Rf41jHzV8Nue/P5N9nqD0VNdgOW2+Mjy9kRRbVHlw+NUwIwKHADR8je4tPfSPym FxS+AzNRWMxY5TwevKk96Mhfpzw7/LRI1nJqgQQUdchL1tACKga97s2otheCyx6kJ3 3Z+lB6YsbVta+l25ypLyXorVsbuTHrEJ6XF6PWwpGtk5lVu7bVHY4K28wvuBPfKqew yaMHrWsDlJI8A== From: Conor Dooley To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org, Daire McNamara Subject: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Date: Tue, 3 Jan 2023 21:04:01 +0000 Message-Id: <20230103210400.3500626-10-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3267; i=conor.dooley@microchip.com; h=from:subject; bh=SqqmRKmJx1EFKtyZtFH3JDmksLOmZmeyHlLx3UHKDvY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlbZlj+bZvcG2t3PfD4fdEU258+/yK7V2xeznZdXHDuXj7J TwKzO0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRia8ZGXo+B97IuG6V7Bxw3+3r+a +6xzfPjOI+ftSBJ5oj/61kdQjD/4LL5x/OCX727NaKh/9+ZSQ1ryou+jFz2o0/0uctfPfpT2QGAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Daire McNamara SiFive L2 cache controller can flush L2 cache. Expose this capability via driver. Signed-off-by: Daire McNamara [Conor: rebase on top of move to cache subsystem] Signed-off-by: Conor Dooley --- This commit needs more work, and a way to enable it from errata. I've not gone and done this as PolarFire SoC has archid etc all set to zero. So we need to go figure out a workaround for this, before adding in errata enabling code for this. I've included it here as a second user of the cache management stuff, since what's currently upstream for the ccache driver does not do any cache management. --- drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index 47e7d6557f85..3c00f205bace 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -9,12 +9,14 @@ #define pr_fmt(fmt) "CCACHE: " fmt #include +#include #include #include #include #include #include #include +#include #include #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 @@ -42,11 +44,15 @@ #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 +#define SIFIVE_CCACHE_FLUSH64 0x200 +#define SIFIVE_CCACHE_FLUSH32 0x240 + #define SIFIVE_CCACHE_MAX_ECCINTR 4 static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static struct riscv_cache_maint_ops ccache_cmos; static int level; enum { @@ -205,6 +211,42 @@ static irqreturn_t ccache_int_handler(int irq, void *device) return IRQ_HANDLED; } +static void sifive_ccache_dma_wback_inv(void* vaddr, unsigned long size) +{ + void * __iomem flush = ccache_base + SIFIVE_CCACHE_FLUSH64; + phys_addr_t start = virt_to_phys(vaddr); + phys_addr_t aligned_start = start & ~0x3f; + u64 addr; + u64 end; + u64 aligned_end; + + size += start - aligned_start; + end = start + size; + aligned_end = end += 0x3f; + aligned_end &= ~0x3f; + + for (addr = aligned_start; addr < aligned_end; addr += 64) + writeq(addr, flush); +} + +static void sifive_ccache_cmo(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops) +{ + switch (dir) { + case DMA_TO_DEVICE: + sifive_ccache_dma_wback_inv(vaddr, size); + break; + case DMA_FROM_DEVICE: + sifive_ccache_dma_wback_inv(vaddr, size); + break; + case DMA_BIDIRECTIONAL: + sifive_ccache_dma_wback_inv(vaddr, size); + break; + default: + break; + } +} + static int __init sifive_ccache_init(void) { struct device_node *np; @@ -254,6 +296,9 @@ static int __init sifive_ccache_init(void) ccache_cache_ops.get_priv_group = ccache_get_priv_group; riscv_set_cacheinfo_ops(&ccache_cache_ops); + ccache_cmos.cmo_patchfunc = sifive_ccache_cmo; + riscv_set_cache_maint_ops(&ccache_cmos); + #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif