From patchwork Wed Jan 4 09:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13088346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4217C4708E for ; Wed, 4 Jan 2023 09:18:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238964AbjADJSe (ORCPT ); Wed, 4 Jan 2023 04:18:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234230AbjADJS0 (ORCPT ); Wed, 4 Jan 2023 04:18:26 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8F741C13B for ; Wed, 4 Jan 2023 01:18:24 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id m3so16187228wmq.0 for ; Wed, 04 Jan 2023 01:18:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5bUYMx+lRdCY1/mnzCkMofLUrng2f5iWQnvkVwv8g/U=; b=RSu2aiug7X1H3mi9T/uIpVB/dNH6K/6FYD1nXfwcUGdjXntzrt5jKFYs7TKXWrI0wm MRoguXr5tMt89YjNAccQBFAw3YkHXrG6m5B4Knu56ygDt1hyzPEqo1Bo4ffF6U33HIeR 4FR9403//8US01nLGOZ8JKSqLt8YGauYqXF2xUYhgN9rVRy9/2KmMHaqEVMIdyxn5sHl T+63qB6gAHf3v+/r8lXSk5wcxe9EHPqPqxM/lINRhcLIN+r/UGWOM+dYpmCyDEn6KsNt KOsUnCXxXPUnDt8vEtA1CnIZ3gvINSsrsfHUgsonty1uZo+I70krced+C5QJs+Sqthaa AO5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5bUYMx+lRdCY1/mnzCkMofLUrng2f5iWQnvkVwv8g/U=; b=FEYWF94tvANoiEGRLsgN4wmrVwh5i5ngGTHmCET5DLY4BioPi2+OMUYbFZIzOG7NLL /mW4KBVhMDQnD+NefLOC3VgaA7MaEV0cayWsrqaaWO/A7EcTt/t7kzSo2Har9CaikLO2 xWmMtX+mPxgvSMuYOJN6UGs+SKyNIr64Mzcvz+Wdd4PrnNAnqdBkbF7Am74EcHlJ+EEQ AyO2UO4dICkBcZo96cqRphgXesmN9JhHt9VVEXjxIwycmEnJklrSFc4C7cjhHdCYrhg7 piovll1ye+wG7BfM9Iq7G4daY/nh4OVAGO1qNRBtdAkB3Zd666QpTcozf8kD0YfaMeUJ 1HgA== X-Gm-Message-State: AFqh2koDNDf9lb8rta7+ExiMg4yzyDjZgOMV0H7OCArnOnHDUOD1nm4p 3E4UyNtLaSlaLqY+8atuxy2Auw== X-Google-Smtp-Source: AMrXdXvCBhHWjRFikdwCWfPZbQbMp+e1ttKXvtuMbXHBhugQ7wKPaLKvb7f6cEEcE7MWeY0s6H99Pg== X-Received: by 2002:a05:600c:354a:b0:3d9:74b8:2d05 with SMTP id i10-20020a05600c354a00b003d974b82d05mr24820221wmq.40.1672823903235; Wed, 04 Jan 2023 01:18:23 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b002a01e64f7a1sm3488656wrp.88.2023.01.04.01.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jan 2023 01:18:22 -0800 (PST) From: Neil Armstrong Date: Wed, 04 Jan 2023 10:18:20 +0100 Subject: [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices MIME-Version: 1.0 Message-Id: <20230104-topic-sm8550-upstream-dts-display-v1-1-aeab9751928f@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v1-0-aeab9751928f@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v1-0-aeab9751928f@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 295 +++++++++++++++++++++++++++++++++++ 1 file changed, 295 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index f1760eea3d6b..3b68bba81473 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1425,6 +1425,301 @@ opp-202000000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8550-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,dsi-phy-4nm-8550"; + reg = <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,dsi-phy-4nm-8550"; + reg = <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8550-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; From patchwork Wed Jan 4 09:18:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13088347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F4ECC4708E for ; Wed, 4 Jan 2023 09:18:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234120AbjADJSh (ORCPT ); Wed, 4 Jan 2023 04:18:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234504AbjADJS0 (ORCPT ); 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Wed, 04 Jan 2023 01:18:23 -0800 (PST) From: Neil Armstrong Date: Wed, 04 Jan 2023 10:18:21 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware MIME-Version: 1.0 Message-Id: <20230104-topic-sm8550-upstream-dts-display-v1-2-aeab9751928f@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v1-0-aeab9751928f@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v1-0-aeab9751928f@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 8586e16d6079..5b7e301cc2a2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -359,6 +359,28 @@ vreg_l3g_1p2: ldo3 { }; }; +&dispcc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12"; From patchwork Wed Jan 4 09:18:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13088348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8127C46467 for ; Wed, 4 Jan 2023 09:18:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234504AbjADJSl (ORCPT ); Wed, 4 Jan 2023 04:18:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234638AbjADJS2 (ORCPT ); Wed, 4 Jan 2023 04:18:28 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BF091ADBB for ; Wed, 4 Jan 2023 01:18:26 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id h16so32249938wrz.12 for ; Wed, 04 Jan 2023 01:18:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uPKIsPLN5aJ8m2V2u6J9M4j3Y5N3lS/nTl2zakrSabY=; b=KgUYk1XAtUleUltJuZN4EAebl/MKD0OC/bLHcREoQUoAJESZqUAA+ggjbUljS7+dx+ uNxOyDWiomIdomHY4ZVc/RJf3hj9StKjkcVBdYcRxxPL5DT1i9quM3easaql/mQVRVLT 2Fcyag8lhZS9oOmoPPYOBLovzgKYygb3QRvgVak0Z1UPEhQ+LmR4TEOROGJ82t8R9ntY XUiJiBA2gqk4q74G2W7jc43JM5ONerTiU3mFIhxZlgCoam2yEwzE96SmKyvOSKEOXKA2 310qHkjm8SeZQOF/MWHs6zsDScsWBfxhrBFf1ejMiJwBe985eyYjHjtdquAMsJquOXe+ YeKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uPKIsPLN5aJ8m2V2u6J9M4j3Y5N3lS/nTl2zakrSabY=; b=NpkhID2NbXFPA/8wKUPdSoSkmCqfO4SzHtyyAhC5h0WZ7nhcgrgQh+08QFB9/PM7fI VFAoIkM3nWMc8Phk+NPG2PmN/ibaRbgS0Sy8p8ILwYLmhdnpX90e2yiRSr8UgCgzg8KY KkY16cpsmrKuq4NlVbRVAZQz/KE/B2IC/Kglr+kIbaw20EGa0z85W5eexqFL5XhN4lUM JRc82Xjm0CXwK3ZGIk+d5B9WCW4pFpYMAo8+juC1OP8qyBOLdPM+8/coKWK0RtUWZwqh Sfznz+3NBfHZ+R9pgTaK0In9qKhMPNXO0iWZBxqSlPSZu172foprGESMqkbj2nn1qVOY Wk9Q== X-Gm-Message-State: AFqh2kqTJCiKBM+SOzya9jrt6iV51aEXwKOXqb40NoYprEAmueQ6URDU BAZmaFX88BxlFephdZdj5eW9Ow== X-Google-Smtp-Source: AMrXdXtETcqHUy17vv9iuJw/kb4eyU0lIMU44u+42OJLTYOJRHugOP8yr8b0m0qLuDUgcqXnA/B4dg== X-Received: by 2002:a5d:404a:0:b0:242:5cf5:3c2c with SMTP id w10-20020a5d404a000000b002425cf53c2cmr24539724wrp.15.1672823904927; Wed, 04 Jan 2023 01:18:24 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id k6-20020adff5c6000000b002a01e64f7a1sm3488656wrp.88.2023.01.04.01.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jan 2023 01:18:24 -0800 (PST) From: Neil Armstrong Date: Wed, 04 Jan 2023 10:18:22 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel MIME-Version: 1.0 Message-Id: <20230104-topic-sm8550-upstream-dts-display-v1-3-aeab9751928f@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v1-0-aeab9751928f@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v1-0-aeab9751928f@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5b7e301cc2a2..cbb63a31f0ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -370,6 +370,34 @@ &mdss { &mdss_dsi0 { vdda-supply = <&vreg_l3e_1p2>; status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + status = "okay"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -415,6 +443,34 @@ &sleep_clk { &tlmm { gpio-reserved-ranges = <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart7 {