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Thu, 5 Jan 2023 03:43:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT096.mail.protection.outlook.com (10.13.177.195) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.17 via Frontend Transport; Thu, 5 Jan 2023 03:43:52 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:43:50 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 01/45] drm/amd: Delay removal of the firmware framebuffer Date: Wed, 4 Jan 2023 21:42:35 -0600 Message-ID: <20230105034327.1439-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT096:EE_|LV2PR12MB5752:EE_ X-MS-Office365-Filtering-Correlation-Id: c3c2b430-eec4-46f6-f0c8-08daeecf1045 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:43:52.4537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3c2b430-eec4-46f6-f0c8-08daeecf1045 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5752 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , stable@vger.kernel.org, christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Removing the firmware framebuffer from the driver means that even if the driver doesn't support the IP blocks in a GPU it will no longer be functional after the driver fails to initialize. This change will ensure that unsupported IP blocks at least cause the driver to work with the EFI framebuffer. Cc: stable@vger.kernel.org Suggested-by: Alex Deucher Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9a1a5c2864a0..cdb681398a99 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -37,6 +37,7 @@ #include #include +#include #include #include #include @@ -89,6 +90,8 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); #define AMDGPU_MAX_RETRY_LIMIT 2 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) +static const struct drm_driver amdgpu_kms_driver; + const char *amdgpu_asic_name[] = { "TAHITI", "PITCAIRN", @@ -3685,6 +3688,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (r) return r; + /* Get rid of things like offb */ + r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver); + if (r) + return r; + /* Enable TMZ based on IP_VERSION */ amdgpu_gmc_tmz_set(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index db7e34eacc35..b9f14ec9edb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -23,7 +23,6 @@ */ #include -#include #include #include #include @@ -2096,11 +2095,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, } #endif - /* Get rid of things like offb */ - ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); - if (ret) - return ret; - adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); if (IS_ERR(adev)) return PTR_ERR(adev); From patchwork Thu Jan 5 03:42:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08F0CC46467 for ; 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Wed, 4 Jan 2023 21:43:52 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 02/45] drm/amd: Add a legacy mapping to "amdgpu_ucode_ip_version_decode" Date: Wed, 4 Jan 2023 21:42:36 -0600 Message-ID: <20230105034327.1439-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT105:EE_|PH8PR12MB7376:EE_ X-MS-Office365-Filtering-Correlation-Id: a6a1e970-fa42-4a79-369c-08daeecf1160 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rDZ2wIuoLmvUrsn5gbkrYXDr00CTqlXRSXg7dYr3j4bl+/Q65BoMspHGqUnbPVExoZCqH0boYNfHRP8dxXfngbiQTUquNt0mEVTeO8qeu92ZSqbhDintVSaFJVKYKLErtwPcd91K75eCqUPdLdc71n9mPckWjc8Var8KsCX8a/+imV/Zqx+VGgRsqy/KqgewrWqTd0VV8HRqc2eYF9+DogFhzNwnQeIJNkmnOte8Xi9Fy5+xUFtsKGFdnK7skQLRSDI9zjimLhcdmLgULPgozcbJATch7jB+wuilH5FLr5C4b5eKo2qd8y/j9KG7cjmnQKwXEU9RsUzhGVRJ9IO25WdObQWdVwfPuRbtfS4lAaARzL4QiHZl68VeUI0knumzbgPi/kpt9WyGOGnkLLsYgpit4cLah6xTkqMPMtN+Vdvc+/yIWll1zmEweAMgjETye6k4vGQgknJpW2qeAQn0yi7bWG8FVw44/WwWrRYToQCrQtIrhJHUWYOi+XPPK83g5bMil/8PYoLn48yL04G0FOsjlfwcbQAdzKbNJMdBOETKrjkjSiv1Mnq3wxj9rvXAiITzZY8wHJ65JgJolrRdl9UejZFYRaAsKHF0qLKcRn0/YKHMgl3JNJBZoYoPWlCEO04V3vTtkuLKUFiUgqXdA/0qauG62iQbGLBya7AeO7ASATukCOeIKw4rHrtoTqwR9VfQP9IgD/9pXdB9eKAca+buyqD0d9eJJq63x0kWSDQ= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199015)(46966006)(40470700004)(36840700001)(47076005)(16526019)(1076003)(426003)(2616005)(186003)(26005)(81166007)(82740400003)(356005)(336012)(86362001)(83380400001)(82310400005)(36756003)(36860700001)(44832011)(40480700001)(41300700001)(4326008)(8936002)(8676002)(40460700003)(5660300002)(6666004)(70586007)(316002)(70206006)(478600001)(54906003)(7696005)(2906002)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:43:54.3193 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6a1e970-fa42-4a79-369c-08daeecf1160 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7376 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This will allow other parts of the driver that currently special case firmware file names to before IP version style naming to just have a single call to `amdgpu_ucode_ip_version_decode`. Signed-off-by: Mario Limonciello Acked-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 221 ++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 5cb62e6249c2..eafcddce58d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -1059,12 +1059,233 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) return 0; } +static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) +{ + if (block_type == MP0_HWIP) { + switch (adev->ip_versions[MP0_HWIP][0]) { + case IP_VERSION(9, 0, 0): + switch (adev->asic_type) { + case CHIP_VEGA10: + return "vega10"; + case CHIP_VEGA12: + return "vega12"; + default: + return NULL; + } + break; + case IP_VERSION(10, 0, 0): + case IP_VERSION(10, 0, 1): + if (adev->asic_type == CHIP_RAVEN) { + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso"; + return "raven"; + } + break; + case IP_VERSION(11, 0, 0): + return "navi10"; + case IP_VERSION(11, 0, 2): + return "vega20"; + case IP_VERSION(11, 0, 4): + return "arcturus"; + case IP_VERSION(11, 0, 5): + return "navi14"; + case IP_VERSION(11, 0, 7): + return "sienna_cichlid"; + case IP_VERSION(11, 0, 9): + return "navi12"; + case IP_VERSION(11, 0, 11): + return "navy_flounder"; + case IP_VERSION(11, 0, 12): + return "dimgrey_cavefish"; + case IP_VERSION(11, 0, 13): + return "beige_goby"; + case IP_VERSION(11, 5, 0): + return "vangogh"; + case IP_VERSION(12, 0, 1): + if (adev->asic_type == CHIP_RENOIR) { + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir"; + return "green_sardine"; + } + break; + case IP_VERSION(13, 0, 2): + return "aldebaran"; + case IP_VERSION(13, 0, 1): + case IP_VERSION(13, 0, 3): + return "yellow_carp"; + } + } else if (block_type == MP1_HWIP) { + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(9, 0, 0): + case IP_VERSION(10, 0, 0): + case IP_VERSION(10, 0, 1): + case IP_VERSION(11, 0, 2): + if (adev->asic_type == CHIP_ARCTURUS) + return "arcturus_smc"; + return NULL; + case IP_VERSION(11, 0, 0): + return "navi10_smc"; + case IP_VERSION(11, 0, 5): + return "navi14_smc"; + case IP_VERSION(11, 0, 9): + return "navi12_smc"; + case IP_VERSION(11, 0, 7): + return "sienna_cichlid_smc"; + case IP_VERSION(11, 0, 11): + return "navy_flounder_smc"; + case IP_VERSION(11, 0, 12): + return "dimgrey_cavefish_smc"; + case IP_VERSION(11, 0, 13): + return "beige_goby_smc"; + case IP_VERSION(13, 0, 2): + return "aldebaran_smc"; + } + } else if (block_type == SDMA0_HWIP) { + switch (adev->ip_versions[SDMA0_HWIP][0]) { + case IP_VERSION(4, 0, 0): + return "vega10_sdma"; + case IP_VERSION(4, 0, 1): + return "vega12_sdma"; + case IP_VERSION(4, 1, 0): + case IP_VERSION(4, 1, 1): + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2_sdma"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso_sdma"; + return "raven_sdma"; + case IP_VERSION(4, 1, 2): + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir_sdma"; + return "green_sardine_sdma"; + case IP_VERSION(4, 2, 0): + return "vega20_sdma"; + case IP_VERSION(4, 2, 2): + return "arcturus_sdma"; + case IP_VERSION(4, 4, 0): + return "aldebaran_sdma"; + case IP_VERSION(5, 0, 0): + return "navi10_sdma"; + case IP_VERSION(5, 0, 1): + return "cyan_skillfish2_sdma"; + case IP_VERSION(5, 0, 2): + return "navi14_sdma"; + case IP_VERSION(5, 0, 5): + return "navi12_sdma"; + case IP_VERSION(5, 2, 0): + return "sienna_cichlid_sdma"; + case IP_VERSION(5, 2, 2): + return "navy_flounder_sdma"; + case IP_VERSION(5, 2, 4): + return "dimgrey_cavefish_sdma"; + case IP_VERSION(5, 2, 5): + return "beige_goby_sdma"; + case IP_VERSION(5, 2, 3): + return "yellow_carp_sdma"; + case IP_VERSION(5, 2, 1): + return "vangogh_sdma"; + } + } else if (block_type == UVD_HWIP) { + switch (adev->ip_versions[UVD_HWIP][0]) { + case IP_VERSION(1, 0, 0): + case IP_VERSION(1, 0, 1): + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2_vcn"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso_vcn"; + return "raven_vcn"; + case IP_VERSION(2, 5, 0): + return "arcturus_vcn"; + case IP_VERSION(2, 2, 0): + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir_vcn"; + return "green_sardine_vcn"; + case IP_VERSION(2, 6, 0): + return "aldebaran_vcn"; + case IP_VERSION(2, 0, 0): + return "navi10_vcn"; + case IP_VERSION(2, 0, 2): + if (adev->asic_type == CHIP_NAVI12) + return "navi12_vcn"; + return "navi14_vcn"; + case IP_VERSION(3, 0, 0): + case IP_VERSION(3, 0, 64): + case IP_VERSION(3, 0, 192): + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) + return "sienna_cichlid_vcn"; + return "navy_flounder_vcn"; + case IP_VERSION(3, 0, 2): + return "vangogh_vcn"; + case IP_VERSION(3, 0, 16): + return "dimgrey_cavefish_vcn"; + case IP_VERSION(3, 0, 33): + return "beige_goby_vcn"; + case IP_VERSION(3, 1, 1): + return "yellow_carp_vcn"; + } + } else if (block_type == GC_HWIP) { + switch (adev->ip_versions[GC_HWIP][0]) { + case IP_VERSION(9, 0, 1): + return "vega10"; + case IP_VERSION(9, 2, 1): + return "vega12"; + case IP_VERSION(9, 4, 0): + return "vega20"; + case IP_VERSION(9, 2, 2): + case IP_VERSION(9, 1, 0): + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso"; + return "raven"; + case IP_VERSION(9, 4, 1): + return "arcturus"; + case IP_VERSION(9, 3, 0): + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir"; + return "green_sardine"; + case IP_VERSION(9, 4, 2): + return "aldebaran"; + case IP_VERSION(10, 1, 10): + return "navi10"; + case IP_VERSION(10, 1, 1): + return "navi14"; + case IP_VERSION(10, 1, 2): + return "navi12"; + case IP_VERSION(10, 3, 0): + return "sienna_cichlid"; + case IP_VERSION(10, 3, 2): + return "navy_flounder"; + case IP_VERSION(10, 3, 1): + return "vangogh"; + case IP_VERSION(10, 3, 4): + return "dimgrey_cavefish"; + case IP_VERSION(10, 3, 5): + return "beige_goby"; + case IP_VERSION(10, 3, 3): + return "yellow_carp"; + case IP_VERSION(10, 1, 3): + case IP_VERSION(10, 1, 4): + return "cyan_skillfish2"; + } + } + return NULL; +} + void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) { int maj, min, rev; char *ip_name; + const char *legacy; uint32_t version = adev->ip_versions[block_type][0]; + legacy = amdgpu_ucode_legacy_naming(adev, block_type); + if (legacy) { + snprintf(ucode_prefix, len, "%s", legacy); + return; + } + switch (block_type) { case GC_HWIP: ip_name = "gc"; From patchwork Thu Jan 5 03:42:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0136FC46467 for ; Thu, 5 Jan 2023 03:44:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB19510E63D; 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Wed, 4 Jan 2023 21:43:54 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 03/45] drm/amd: Convert SMUv11 microcode to use `amdgpu_ucode_ip_version_decode` Date: Wed, 4 Jan 2023 21:42:37 -0600 Message-ID: <20230105034327.1439-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT068:EE_|DS0PR12MB7510:EE_ X-MS-Office365-Filtering-Correlation-Id: 85ea90c0-f5ea-4b07-85af-08daeecf12af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X+X7vTkwL1BGkXNOkUhcBbLBl8HIB8xHH5+SbEX41+zsCsS6wWpgG3Upn24RvsV1LLrOyk+m36rxZE6MsG522FdyUUWXckH4aBG3guOsziTYij5vOnQ9TAOochsF/SpXhPcNCFMoLvEYzx0CeNkhf5n2ZiQVy9Ymo9DXcTygyRNM0FycJt6c4oKcXfjyqw4kzzlkJTk5G57wuhnaFLPnZRxW6tc0ilEW8tI+9VKnp723JswYmwwUK7at/vQpRDLhxcPaUoEZhCxdG7j7UoMhG0rHV3RH4X+Lq8LFOWli9rWGQD4kSUa8yKatyh7QxOr/oU9fP5iJLrgycKxKTK6rzqfG5F4wUCCe+QY7WjYnzjI+crAphpi+48gv8/xoUMxdxU8vDLUzGgZ7LJOEAIFFqbObvfSn+kGCYnETScP1XTlQUMMp2ZHcuzw6YJIJ9eKlbeVu3mnB94t3gsojkHcV9g70zH4JAwgte/B48Wu/KSCAvD+j7AUYcYEBGUENE+2NjKSNHYfLET0SO2vegYVVpG+3RdzPcZH7USIXu6xBgdA5UnF0frsU5gJa6S/85hQXncA8AwyUzpSND6P13wU+LC+wD/WAHa4MHuji3DVap/7rO+c04wcC8PfjdcaNghlXqhC64Zd+7I8/nSvYCzMw2y6JdMATr1lqvBZIJuaF1zqd6S86ZB0NA/AUIdIQa6hwKVNYLEi/anVeG/aDQKGGEhJMGBzWSh/FKMRbAUIGty+Xve3diDNurCM4o/QbdVESMgqTcQlEjglwm0gQLNHNsg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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No intended functional changes. Signed-off-by: Mario Limonciello Acked-by: Christian König Reviewed-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 35 ++----------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index ad66d57aa102..d4756bd30830 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -93,7 +93,7 @@ static void smu_v11_0_poll_baco_exit(struct smu_context *smu) int smu_v11_0_init_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - const char *chip_name; + char ucode_prefix[30]; char fw_name[SMU_FW_NAME_LEN]; int err = 0; const struct smc_firmware_header_v1_0 *hdr; @@ -105,38 +105,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu) (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) return 0; - switch (adev->ip_versions[MP1_HWIP][0]) { - case IP_VERSION(11, 0, 0): - chip_name = "navi10"; - break; - case IP_VERSION(11, 0, 5): - chip_name = "navi14"; - break; - case IP_VERSION(11, 0, 9): - chip_name = "navi12"; - break; - case IP_VERSION(11, 0, 7): - chip_name = "sienna_cichlid"; - break; - case IP_VERSION(11, 0, 11): - chip_name = "navy_flounder"; - break; - case IP_VERSION(11, 0, 12): - chip_name = "dimgrey_cavefish"; - break; - case IP_VERSION(11, 0, 13): - chip_name = "beige_goby"; - break; - case IP_VERSION(11, 0, 2): - chip_name = "arcturus"; - break; - default: - dev_err(adev->dev, "Unsupported IP version 0x%x\n", - adev->ip_versions[MP1_HWIP][0]); - return -EINVAL; - } + amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); err = request_firmware(&adev->pm.fw, fw_name, adev->dev); if (err) From patchwork Thu Jan 5 03:42:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A064C54EBC for ; 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Wed, 4 Jan 2023 21:43:56 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 04/45] drm/amd: Convert SMUv13 microcode to use `amdgpu_ucode_ip_version_decode` Date: Wed, 4 Jan 2023 21:42:38 -0600 Message-ID: <20230105034327.1439-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT064:EE_|SN7PR12MB7371:EE_ X-MS-Office365-Filtering-Correlation-Id: 8369df65-9b7a-4c71-fd33-08daeecf13c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UHXZx66UKXF4JS2617CPH3yboINOpnMByyrrkQfxnMf2dBBCoSShLYov8UHNUaqwq9iJpH+nfKVhq1/A/wEsM05svq4HSjkn6EtPJHkTfOw07N8TAagVj6AMKFzeUMomzwhCrLAVWYwKHt1whTN1suo2Dr99KOCiktguqyaVdsP1gVRUFOuKU5JHY6QPOor2l2ChH/kc32f1r5oSGmCqHHgDXhQy0deaWFdQ2vGkkprLFRpRz8c+5ncV9OtpxrKBBcc5eK9q6xS5OUOQJU1+Gr6/Xm0U/Df6+Kqz9PJwGHdmgwKrpTTglZ9jSVfuzx3niKdSFpFyxZJwaUtg4EadKZh5a/AVYQyDAPkji3z0vQGjPMVLOWxqFMmYnhI4hv+598mVD/vAceBVPIvDxkGPa09eUgacUhLqJ84fQn5P5RMWx0KGEtVe0bO6pbs/GO78YNJrFjGo2TRiDGqC7OyTGn0hBqTIgGMaed+UR7k/EAMcLRv2ZPjti3keUN+CqrA6Onhmk0Ne85s05gRlqf9bpxXx/wl23fImbQuZLHsSbNfSCR7AVS9RVyW56+TIjxCmTRjXGPBX6g1hQniJ+e2B1wMDdqfoYfMu4pDki2LPllirvQzs0ziCWkYiaQxdkXddP4WWnkIt21FfE+4PmkRVskwFUh3LdVR10I6s48rYpxl/2mUN6Aqo6bygHqUoxsxnLNuG7FKjsd0a7Q3/wKCsKfBbmBuKeoFcrSLEdRx3LmS/R+w04xx5vP5fzzElY/RZX95cqfHlolF7FgdAzcfCcw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(39860400002)(136003)(396003)(376002)(451199015)(46966006)(40470700004)(36840700001)(70586007)(44832011)(5660300002)(70206006)(316002)(54906003)(41300700001)(2906002)(8676002)(4326008)(8936002)(478600001)(36756003)(110136005)(82310400005)(36860700001)(6666004)(26005)(83380400001)(2616005)(1076003)(16526019)(47076005)(426003)(186003)(66574015)(7696005)(82740400003)(86362001)(336012)(40480700001)(356005)(40460700003)(81166007)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:43:58.3220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8369df65-9b7a-4c71-fd33-08daeecf13c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7371 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , Evan Quan , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The special case for the one dGPU has been moved into `amdgpu_ucode_ip_version_decode`, so simplify this code. Signed-off-by: Mario Limonciello Acked-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 0ac9cac805f9..506a49a4b425 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -88,7 +88,6 @@ static const int link_speed[] = {25, 50, 80, 160}; int smu_v13_0_init_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - const char *chip_name; char fw_name[30]; char ucode_prefix[30]; int err = 0; @@ -100,16 +99,9 @@ int smu_v13_0_init_microcode(struct smu_context *smu) if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->ip_versions[MP1_HWIP][0]) { - case IP_VERSION(13, 0, 2): - chip_name = "aldebaran_smc"; - break; - default: - amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - chip_name = ucode_prefix; - } + amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); err = request_firmware(&adev->pm.fw, fw_name, adev->dev); if (err) From patchwork Thu Jan 5 03:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49504C5479D for ; Thu, 5 Jan 2023 03:44:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C89C10E649; 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Wed, 4 Jan 2023 21:43:58 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 05/45] drm/amd: Add a new helper for loading/validating microcode Date: Wed, 4 Jan 2023 21:42:39 -0600 Message-ID: <20230105034327.1439-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|DM4PR12MB5135:EE_ X-MS-Office365-Filtering-Correlation-Id: 468d4154-0a9d-4abb-5128-08daeecf14dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KhrifsgAonCd9QikMbSyA7+PU3MywwzSimCXBJky88LgcRkkpdZf9to0YY6nFqCJ94prn/qNHEPXTjRdVhVHafFDgQXqRF61L1a26gSdGwo5N8A9DT/pDhumd6eoWU/T/9thu9kPmsQwAAv6bzcMsuZ06ZbwRQDJTHvD05f9Svo2VCtoPk0l4g3A+lI8HAVso6TWh+ugPOn+T9CevAJ9Q+Ys7BtZqhgdJfc7yjslna8bW/GceEzexv1nP7aw9i6rkJWFONpcQAXUhVyd6Z42bUZKdoO0oT9BmGtQR/oz9Vb+kId8iXA9SqJdBypclaXYnwysFjRDyciD0Fkc6P4H07x3Yo+/+KgHwFKgqxLkPocRdM+3LKIr2j4cRzN9q7ADG7C3kbpZx7tLpBgp2WnLRv9uc5fA/Y2RUsRBg8Mx8jv09Zlwxhc1spOrn/Dg/pl87gP8FiP6x85Pcxthii3x0olfgBG2w2Yn/HiAm3wy1XoP4GiOHHKuA2YMKgvU9z9EGDz21BICcp0aYKWTe1Ix6uIVFyhx3vhF72hUekxoKhK821BI2x0wUcB/Zq8oBn+VH/8vjJXGsQpIXj15M4tEwwn1mUHhRqs4r6bYaHNWQ6XNsH5fE7nDp9GKw/PCQV5lm0OUfVPSwR885VUXpHW5ikZUgEKiucRzhmCOA36mfbbDAvNM7mIebbP2POtGJ1eoi9hkYBHdMrs+NYtbucge1ttRVw1ZOqexH5jTBl1ZX6o= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199015)(40470700004)(46966006)(36840700001)(36756003)(70206006)(70586007)(83380400001)(4326008)(5660300002)(44832011)(8676002)(86362001)(2906002)(8936002)(82740400003)(81166007)(36860700001)(54906003)(41300700001)(40460700003)(336012)(7696005)(2616005)(110136005)(6666004)(356005)(316002)(478600001)(26005)(1076003)(47076005)(82310400005)(16526019)(40480700001)(426003)(186003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:00.1501 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 468d4154-0a9d-4abb-5128-08daeecf14dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5135 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" All microcode runs a basic validation after it's been loaded. Each IP block as part of init will run both. Introduce a wrapper for request_firmware and amdgpu_ucode_validate. This wrapper will also remap any error codes from request_firmware to -ENODEV. This is so that early_init will fail if firmware couldn't be loaded instead of the IP block being disabled. Signed-off-by: Mario Limonciello --- v5->v6: * Fix argument to be ** not * --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 36 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++ 2 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index eafcddce58d3..8ebfec12da87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -1312,3 +1312,39 @@ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); } + +/* + * amdgpu_ucode_request - Fetch and validate amdgpu microcode + * + * @adev: amdgpu device + * @fw: pointer to load firmware to + * @fw_name: firmware to load + * + * This is a helper that will use request_firmware and amdgpu_ucode_validate + * to load and run basic validation on firmware. If the load fails, remap + * the error code to -ENODEV, so that early_init functions will fail to load. + */ +int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, + const char *fw_name) +{ + int err = request_firmware(fw, fw_name, adev->dev); + + if (err) + return -ENODEV; + err = amdgpu_ucode_validate(*fw); + if (err) + dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name); + + return err; +} + +/* + * amdgpu_ucode_release - Release firmware microcode + * + * @fw: pointer to firmware to release + */ +void amdgpu_ucode_release(const struct firmware **fw) +{ + release_firmware(*fw); + *fw = NULL; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 552e06929229..848579d4988b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -544,6 +544,9 @@ void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); int amdgpu_ucode_validate(const struct firmware *fw); +int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, + const char *fw_name); +void amdgpu_ucode_release(const struct firmware **fw); bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, uint16_t hdr_major, uint16_t hdr_minor); From patchwork Thu Jan 5 03:42:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93750C46467 for ; Thu, 5 Jan 2023 03:44:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E49310E641; 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Wed, 4 Jan 2023 21:44:00 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 06/45] drm/amd: Use `amdgpu_ucode_request` helper for SDMA Date: Wed, 4 Jan 2023 21:42:40 -0600 Message-ID: <20230105034327.1439-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|BL3PR12MB6428:EE_ X-MS-Office365-Filtering-Correlation-Id: 0273cd01-106d-41a6-38d0-08daeecf18a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FI528YcA6VVw41Yow2F1hgowNReELM5Gka6wwmivS+7vVvjuAroEvpSnmG1yOgO6ymkKEk2XccesOSgmDmBbD+7HSWdffqHCkSI9aJxiXQW+13p7zh89fyBOnV/Bc07nM7AuhY5kMcPqTN4T66jsCjj+P8HW+EZT8MQ12QvCrfUjU10vnDrQxfIiOwqslMbvJ+BLv60xKWmVlz7qsjQIlCYuSb6rGl/2vr3yyfmcR6czd7BcjcEqAleMvzIec1M3gZDXsO3pwzQH8S3ZWKdZsTT3hKNnC+YnN6clELXxQiqdWPJ2sOovMrb+gOVu7ed8Zcy1M6SBeEze1IzXl/DNUJmLxVkcoNhxkLFsFpCLaq2XXfr85uitHuSKv6KAQx+DOZN2GhmT4Vqtr2ZTz7sYG69CcUfZDKiXOifHZiFhuVNKOOh7pTPP16ly4SfcHuA5ET87BHKM1U3Lq9P2JMyT0FhcWbiZJmE1VCUiquUWjpTijYO77ZR6R4Byjt2pn54rDHS0ghGUxxJ/xVavFFJTzDCM7XkWFs/GyEwNArthDxLvKRdu+KHyzjl6ZXENSZVz6Q9BtU+rD72RnJTn0KhCSnMiluAj5BX4HbzPqjpT3zDyASgpGktR0Zy+IwwMwptKPV8iHVxbM7OIapGlstUFtX2hqVvZMzm5Ow4Fg2CFVereGPFp/XMRnLEFiAWjKrPPfrZK557vX1uRuHeNozLgXsnog1DGqyU0iX3hxOiWEEN51VMUNhYrcXT0G/3eWgBLqkTSIZDC85ehXyZQ+3uLkQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(396003)(39860400002)(346002)(376002)(451199015)(46966006)(36840700001)(40470700004)(47076005)(83380400001)(426003)(2616005)(26005)(186003)(82310400005)(16526019)(40480700001)(336012)(6666004)(7696005)(40460700003)(86362001)(36860700001)(36756003)(81166007)(356005)(82740400003)(1076003)(41300700001)(4326008)(8676002)(2906002)(5660300002)(8936002)(44832011)(316002)(478600001)(70206006)(110136005)(54906003)(70586007)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:06.4934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0273cd01-106d-41a6-38d0-08daeecf18a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6428 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index ea5278f094c0..a6a491569022 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -154,16 +154,11 @@ int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, static int amdgpu_sdma_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) { - int err = 0; uint16_t version_major; const struct common_firmware_header *header = NULL; const struct sdma_firmware_header_v1_0 *hdr; const struct sdma_firmware_header_v2_0 *hdr_v2; - err = amdgpu_ucode_validate(sdma_inst->fw); - if (err) - return err; - header = (const struct common_firmware_header *) sdma_inst->fw->data; version_major = le16_to_cpu(header->header_version_major); @@ -195,7 +190,7 @@ void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, int i; for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); + amdgpu_ucode_release(&adev->sdma.instance[i].fw); if (duplicate) break; } @@ -214,7 +209,7 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, const struct sdma_firmware_header_v2_0 *sdma_hdr; uint16_t version_major; - err = request_firmware(&adev->sdma.instance[instance].fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->sdma.instance[instance].fw, fw_name); if (err) goto out; From patchwork Thu Jan 5 03:42:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C67AC5479D for ; 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Wed, 4 Jan 2023 21:44:02 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 07/45] drm/amd: Convert SDMA to use `amdgpu_ucode_ip_version_decode` Date: Wed, 4 Jan 2023 21:42:41 -0600 Message-ID: <20230105034327.1439-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|SJ0PR12MB8113:EE_ X-MS-Office365-Filtering-Correlation-Id: ed55664e-a1b6-4b76-0ddd-08daeecf18db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6ig/wr9EwO4hu2mUv7PxQBfOX93tVytdzas5gwU2IWe9Aa6ye1sMqSMomSrIq/LUqr5LNSNym5UOWujmRYNLpAb0+DdZRmqO2c20taVSyJARJANlt9250RzElOZeBWtO0Io9JRbjNFOHsOISOY5z++edtaHB+OlnbYM8fZpD6H8Nz5azIuFwf7fiDM+EB9MaQYaWZEjIzm4MDLq8TMN/bymDUKzRYSUfJR5wdh7XXW8PpJIg0SGq3Vc7Vfv/+T9MPmYJBMPs8fgeZ7q0++UciXk/2nZvZURRU/dTShujFeSZ2JZM32N12Pvk+DiCWgeOwdpznNEwLinkvma0aaHp9nVydhuyKt/Ni4bfy92q2BqOWORHT6dNvgnS+Gn1uD1+lxmrprCNxGnq2SMIxQvjv9fivf+4ulytCezDWKqV8yH8Qo5vwkZZ9Ti4xG+c//DNCl2iRJEDRyz1okvKFN8LOtjEm794gEZ+40mkb8TU4SH8kwBR4FUI4KG7YQKOgLom1/uEfrzudqwGtF7/R+nvO5Vkz0K1agiIWvH5v8mRWeAqZXjxd74zZwl+RLC/gNlOeFzi7WxYa7qwM+OF4+Ziu8/Bc0Zs1vzsJLe7jlXdaDuc/AYCuD7X6c791UZdYOZPLWzEMzSQaMImjD/0fX0WsJ9MuDhrjpFo5MbnBE8mqXn4dbk3EcBK017ylaZjFG4oFmQ0VgWzl+Mi2pLvKx6uzIOF8BwQqPOJg6Xo9O+6yZ9UN1mQAUt+gV1OgGwpuDYz X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 4 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 47 +------------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 30 +------------ drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 55 +----------------------- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 25 +---------- 6 files changed, 17 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index a6a491569022..95e9450f3348 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -200,15 +200,21 @@ void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, } int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, - char *fw_name, u32 instance, - bool duplicate) + u32 instance, bool duplicate) { struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; int err = 0, i; const struct sdma_firmware_header_v2_0 *sdma_hdr; uint16_t version_major; - + char ucode_prefix[30]; + char fw_name[40]; + + amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); + if (instance == 0) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s%d.bin", ucode_prefix, i); err = amdgpu_ucode_request(adev, &adev->sdma.instance[instance].fw, fw_name); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index 7d99205c2e01..2d16e6d36728 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h @@ -124,8 +124,8 @@ int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev, int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); -int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, - char *fw_name, u32 instance, bool duplicate); +int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance, + bool duplicate); void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, bool duplicate); void amdgpu_sdma_unset_buffer_funcs_helper(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 4d780e4430e7..017ae298558e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -575,60 +575,17 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) // vega10 real chip need to use PSP to load firmware static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; - char fw_name[30]; int ret, i; - DRM_DEBUG("\n"); - - switch (adev->ip_versions[SDMA0_HWIP][0]) { - case IP_VERSION(4, 0, 0): - chip_name = "vega10"; - break; - case IP_VERSION(4, 0, 1): - chip_name = "vega12"; - break; - case IP_VERSION(4, 2, 0): - chip_name = "vega20"; - break; - case IP_VERSION(4, 1, 0): - case IP_VERSION(4, 1, 1): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - case IP_VERSION(4, 2, 2): - chip_name = "arcturus"; - break; - case IP_VERSION(4, 1, 2): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - case IP_VERSION(4, 4, 0): - chip_name = "aldebaran"; - break; - default: - BUG(); - } - for (i = 0; i < adev->sdma.num_instances; i++) { - if (i == 0) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { /* Acturus & Aldebaran will leverage the same FW memory for every SDMA instance */ - ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true); + ret = amdgpu_sdma_init_microcode(adev, 0, true); break; } else { - ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); + ret = amdgpu_sdma_init_microcode(adev, i, false); if (ret) return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index d4d9f196db83..1941b3b7c5d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -237,39 +237,13 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) // emulation only, won't work on real chip // navi10 real chip need to use PSP to load firmware static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) -{ - const char *chip_name; - char fw_name[40]; - int ret, i; +{ int ret, i; if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) return 0; - DRM_DEBUG("\n"); - - switch (adev->ip_versions[SDMA0_HWIP][0]) { - case IP_VERSION(5, 0, 0): - chip_name = "navi10"; - break; - case IP_VERSION(5, 0, 2): - chip_name = "navi14"; - break; - case IP_VERSION(5, 0, 5): - chip_name = "navi12"; - break; - case IP_VERSION(5, 0, 1): - chip_name = "cyan_skillfish2"; - break; - default: - BUG(); - } - for (i = 0; i < adev->sdma.num_instances; i++) { - if (i == 0) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); + ret = amdgpu_sdma_init_microcode(adev, i, false); if (ret) return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 65e7a710298d..8e445eb9dd49 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -89,59 +89,6 @@ static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 return base + internal_offset; } -/** - * sdma_v5_2_init_microcode - load ucode images from disk - * - * @adev: amdgpu_device pointer - * - * Use the firmware interface to load the ucode images into - * the driver (not loaded into hw). - * Returns 0 on success, error on failure. - */ - -// emulation only, won't work on real chip -// navi10 real chip need to use PSP to load firmware -static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) -{ - const char *chip_name; - char fw_name[40]; - - DRM_DEBUG("\n"); - - switch (adev->ip_versions[SDMA0_HWIP][0]) { - case IP_VERSION(5, 2, 0): - chip_name = "sienna_cichlid_sdma"; - break; - case IP_VERSION(5, 2, 2): - chip_name = "navy_flounder_sdma"; - break; - case IP_VERSION(5, 2, 1): - chip_name = "vangogh_sdma"; - break; - case IP_VERSION(5, 2, 4): - chip_name = "dimgrey_cavefish_sdma"; - break; - case IP_VERSION(5, 2, 5): - chip_name = "beige_goby_sdma"; - break; - case IP_VERSION(5, 2, 3): - chip_name = "yellow_carp_sdma"; - break; - case IP_VERSION(5, 2, 6): - chip_name = "sdma_5_2_6"; - break; - case IP_VERSION(5, 2, 7): - chip_name = "sdma_5_2_7"; - break; - default: - BUG(); - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); - - return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); -} - static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) { unsigned ret; @@ -1288,7 +1235,7 @@ static int sdma_v5_2_sw_init(void *handle) return r; } - r = sdma_v5_2_init_microcode(adev); + r = amdgpu_sdma_init_microcode(adev, 0, true); if (r) { DRM_ERROR("Failed to load sdma firmware!\n"); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 049c26a45d85..bf1fa5e8d2f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -78,29 +78,6 @@ static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 return base + internal_offset; } -/** - * sdma_v6_0_init_microcode - load ucode images from disk - * - * @adev: amdgpu_device pointer - * - * Use the firmware interface to load the ucode images into - * the driver (not loaded into hw). - * Returns 0 on success, error on failure. - */ -static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) -{ - char fw_name[30]; - char ucode_prefix[30]; - - DRM_DEBUG("\n"); - - amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); - - return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); -} - static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) { unsigned ret; @@ -1260,7 +1237,7 @@ static int sdma_v6_0_sw_init(void *handle) if (r) return r; - r = sdma_v6_0_init_microcode(adev); + r = amdgpu_sdma_init_microcode(adev, 0, true); if (r) { DRM_ERROR("Failed to load sdma firmware!\n"); return r; From patchwork Thu Jan 5 03:42:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 670C3C4708D for ; Thu, 5 Jan 2023 03:44:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A3EC210E645; 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Wed, 4 Jan 2023 21:44:04 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 08/45] drm/amd: Make SDMA firmware load failures less noisy. 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Drop the others. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 95e9450f3348..0e1e2521fe25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -280,10 +280,8 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, } out: - if (err) { - DRM_ERROR("SDMA: Failed to init firmware \"%s\"\n", fw_name); + if (err) amdgpu_sdma_destroy_inst_ctx(adev, duplicate); - } return err; } From patchwork Thu Jan 5 03:42:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D145AC4708D for ; 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Wed, 4 Jan 2023 21:44:06 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 09/45] drm/amd: Use `amdgpu_ucode_*` helpers for VCN Date: Wed, 4 Jan 2023 21:42:43 -0600 Message-ID: <20230105034327.1439-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|CY8PR12MB7681:EE_ X-MS-Office365-Filtering-Correlation-Id: cbc06ad2-f31c-48b8-2261-08daeecf19f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LP9wdfWVqBq9im3ifbs3PYw2LbbXAVPcO90ogPjSk2yMLGuq/pBDLBN7jg8/9/EIZn+RKcWK0p0a19eb36JciE4gM3kqpI3EdhnikonBIOxf1i4arZt+RKRstkoV3LGG1Une/+3M3xIYtFNprnORAxQXtApGaiiSP7u+wiuRqiMjMk0USKfNNHpKG9FbJO2Gk3Ini6XVC1SLk07wjtFuBn5vTkVKLHKAltqLaA1ISh/OULLm6RF/Vwv3dfgiA+DLImoVPGdgvejarSTWkhKTaCgaS5EiwoQ2EzRN/tQNczmDsdlRSrKazmpnmWmAonDolKOciiJH2L0SBCylk7DQvXiXgXO7OudAk/EUP51G4+qABz0MUkUQpsmrLjL2KChl7IXC0v6mBgq4j3sTLDbsEqxary//bg0nzR620nYOyuZ+WXyc3kHRa/g2W7oZlERb+Qx0n0IuhQ3OX7kW6bO1U6WblZvaoGial/7QAmU3DV/cTpBItfeRZTy7SZTaq92HZDZJmhZmU3ZAjRy8bIl4RlPP2CzpVYwbLnqHUnDbZyxNjlJ9oS8r611IB5lcPPzzbV9ZhosFf9aG62uMLzmbuVSpTD4c6Xb545Ew6lrjFtaQ1YEFLTREBLgN2+moiks+i8l7ZsvXABbgLrWBmiH88X3ryXGTLBzJ+WqgnhMVWy6geWZBZtixidZxzoIzfmMoprmuwT3cf2iEJDQeMdbSXTKbT+Sr4UoljFGnyNWfVpB6D0EPpC0cNmsZwYpYFNRQKj3/GmSOJkEAF3VrL+jjYA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199015)(40470700004)(46966006)(36840700001)(6666004)(478600001)(36756003)(110136005)(36860700001)(82310400005)(86362001)(40480700001)(82740400003)(40460700003)(356005)(81166007)(47076005)(426003)(1076003)(16526019)(186003)(7696005)(26005)(336012)(2616005)(83380400001)(5660300002)(70586007)(44832011)(8676002)(70206006)(4326008)(8936002)(54906003)(316002)(41300700001)(2906002)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:08.7276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbc06ad2-f31c-48b8-2261-08daeecf19f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7681 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index a23e26b272b4..b37400107a37 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -206,19 +206,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) return -EINVAL; } - r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); + r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); if (r) { - dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", - fw_name); - return r; - } - - r = amdgpu_ucode_validate(adev->vcn.fw); - if (r) { - dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", - fw_name); - release_firmware(adev->vcn.fw); - adev->vcn.fw = NULL; + amdgpu_ucode_release(&adev->vcn.fw); return r; } @@ -333,7 +323,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); } - release_firmware(adev->vcn.fw); + amdgpu_ucode_release(&adev->vcn.fw); mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); mutex_destroy(&adev->vcn.vcn_pg_lock); From patchwork Thu Jan 5 03:42:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B251C4708D for ; Thu, 5 Jan 2023 03:44:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56E1410E648; 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Wed, 4 Jan 2023 21:44:08 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 10/45] drm/amd: Load VCN microcode during early_init Date: Wed, 4 Jan 2023 21:42:44 -0600 Message-ID: <20230105034327.1439-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|IA0PR12MB7652:EE_ X-MS-Office365-Filtering-Correlation-Id: abd4b61b-8249-4f30-afd7-08daeecf1c18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F2WCgZ4J5V5Z8IJnhRyLBprISpNZL+kX5I7EN6TpX6aQwbA6KzYLEIWdHvImKkf36Q2GHTb4Te1cnYMXF/MmFwmKTGXEz7R0I7dswjVcI+6mLgttF6f3EYAa9FStJQWCU/tMTHCeaJcjl7zcR3aaLXLRAhfV9fDV+XK841j4MsoKhDuuLYPIHP4+mbZyTFIwIW+qp8XPBfLWk1/fMQ8ju2pGhkUFSACOR2ylnMZPJ7ILRc0Hl26+JQd5NQ5gWZAhuibMN/KLOlVjyrI+1KCyT22LRdDyFB8/uYP6rRQNANBkW+hw0c0Y2zF/HqJtM29pz+qQZdCI7umbGFPsmbHr4vHs/WHpmOBlh1+jCfBFJ9GSgun2SV53DoB8GbnBx8r665+emQcjDd0hcl1osaUQ9w0g0A/oJPmnRmIKOOiAxvh/LV8hS4WURexPDBmK7axevNKv9n6rHjX3qGYqGt+BTL8OpFmvVV7ODJJQoa+r4ePpt6TaGrNHk8opUhOMoy3J4aKGTI3SEFIyDFSG/Qr140UfCFNctATB6Vs+7V+5GbnrbyzW+Uw6MFGI0HbFeAsysbtDtbi0mV2tNo0CQktTomCUV0Wi6mfTV7nuG8F577mF1wexCgamaxfTuvEHCHpLHP+OdqIZUDwX4NcLaPmPOQVDTK+8O6QQwHO0RbCREkpXGwc5PJYy4DYWBvxbZceTMKoY2r9UWBZHW138w+i/NQTlhrvx+eo1wpC85CGxc+Mb62CyUw9oaQoo2wA+7PAxXKDdKmU+S3Z+iWJCBpZFbpv++eIVC3Qy7bKlU7Zw2hI= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(396003)(346002)(136003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(83380400001)(6666004)(36756003)(36860700001)(478600001)(82310400005)(16526019)(40460700003)(86362001)(81166007)(82740400003)(356005)(40480700001)(47076005)(1076003)(426003)(186003)(26005)(2616005)(7696005)(110136005)(336012)(5660300002)(30864003)(44832011)(70586007)(8676002)(4326008)(70206006)(8936002)(41300700001)(54906003)(2906002)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:12.2898 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abd4b61b-8249-4f30-afd7-08daeecf1c18 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7652 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Simplifies the code so that all VCN versions will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Signed-off-by: Mario Limonciello --- v5->v6: * Fix whitespace problem in firmware file names * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 53 +++++++------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 5 ++- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 5 ++- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 5 ++- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 5 ++- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 5 ++- 7 files changed, 31 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index b37400107a37..0fb9a6d23065 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -80,10 +80,24 @@ MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); +int amdgpu_vcn_early_init(struct amdgpu_device *adev) +{ + char ucode_prefix[30]; + char fw_name[40]; + int r; + + amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); + r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); + if (r) + amdgpu_ucode_release(&adev->vcn.fw); + + return r; +} + int amdgpu_vcn_sw_init(struct amdgpu_device *adev) { unsigned long bo_size; - const char *fw_name; const struct common_firmware_header *hdr; unsigned char fw_check; unsigned int fw_shared_size, log_offset; @@ -99,46 +113,27 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) switch (adev->ip_versions[UVD_HWIP][0]) { case IP_VERSION(1, 0, 0): case IP_VERSION(1, 0, 1): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - fw_name = FIRMWARE_RAVEN2; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - fw_name = FIRMWARE_PICASSO; - else - fw_name = FIRMWARE_RAVEN; - break; case IP_VERSION(2, 5, 0): - fw_name = FIRMWARE_ARCTURUS; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 2, 0): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - fw_name = FIRMWARE_RENOIR; - else - fw_name = FIRMWARE_GREEN_SARDINE; - if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 6, 0): - fw_name = FIRMWARE_ALDEBARAN; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 0, 0): - fw_name = FIRMWARE_NAVI10; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 0, 2): - if (adev->asic_type == CHIP_NAVI12) - fw_name = FIRMWARE_NAVI12; - else - fw_name = FIRMWARE_NAVI14; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; @@ -146,58 +141,46 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 64): case IP_VERSION(3, 0, 192): - if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) - fw_name = FIRMWARE_SIENNA_CICHLID; - else - fw_name = FIRMWARE_NAVY_FLOUNDER; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 0, 2): - fw_name = FIRMWARE_VANGOGH; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 0, 16): - fw_name = FIRMWARE_DIMGREY_CAVEFISH; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 0, 33): - fw_name = FIRMWARE_BEIGE_GOBY; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 1, 1): - fw_name = FIRMWARE_YELLOW_CARP; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 1, 2): - fw_name = FIRMWARE_VCN_3_1_2; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(4, 0, 0): - fw_name = FIRMWARE_VCN4_0_0; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(4, 0, 2): - fw_name = FIRMWARE_VCN4_0_2; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(4, 0, 4): - fw_name = FIRMWARE_VCN4_0_4; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; @@ -206,12 +189,6 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) return -EINVAL; } - r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); - if (r) { - amdgpu_ucode_release(&adev->vcn.fw); - return r; - } - hdr = (const struct common_firmware_header *)adev->vcn.fw->data; adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index dbb8d68a30c6..d3e2af902907 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -369,6 +369,7 @@ enum vcn_ring_type { VCN_UNIFIED_RING, }; +int amdgpu_vcn_early_init(struct amdgpu_device *adev); int amdgpu_vcn_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); int amdgpu_vcn_suspend(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index f0fbcda76f5e..c305b2cb8490 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -57,11 +57,12 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work); static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); /** - * vcn_v1_0_early_init - set function pointers + * vcn_v1_0_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers + * Load microcode from filesystem */ static int vcn_v1_0_early_init(void *handle) { @@ -75,7 +76,7 @@ static int vcn_v1_0_early_init(void *handle) jpeg_v1_0_early_init(handle); - return 0; + return amdgpu_vcn_early_init(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 08871bad9994..4b4cd88414e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -62,11 +62,12 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, struct dpg_pause_state *new_state); static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); /** - * vcn_v2_0_early_init - set function pointers + * vcn_v2_0_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers + * Load microcode from filesystem */ static int vcn_v2_0_early_init(void *handle) { @@ -81,7 +82,7 @@ static int vcn_v2_0_early_init(void *handle) vcn_v2_0_set_enc_ring_funcs(adev); vcn_v2_0_set_irq_funcs(adev); - return 0; + return amdgpu_vcn_early_init(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index ec87b00f2e05..b0b0e69c6a94 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -71,11 +71,12 @@ static int amdgpu_ih_clientid_vcns[] = { }; /** - * vcn_v2_5_early_init - set function pointers + * vcn_v2_5_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers + * Load microcode from filesystem */ static int vcn_v2_5_early_init(void *handle) { @@ -107,7 +108,7 @@ static int vcn_v2_5_early_init(void *handle) vcn_v2_5_set_irq_funcs(adev); vcn_v2_5_set_ras_funcs(adev); - return 0; + return amdgpu_vcn_early_init(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 9c8b5fd99037..bd228512424a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -78,11 +78,12 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); /** - * vcn_v3_0_early_init - set function pointers + * vcn_v3_0_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers + * Load microcode from filesystem */ static int vcn_v3_0_early_init(void *handle) { @@ -109,7 +110,7 @@ static int vcn_v3_0_early_init(void *handle) vcn_v3_0_set_enc_ring_funcs(adev); vcn_v3_0_set_irq_funcs(adev); - return 0; + return amdgpu_vcn_early_init(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 1e2b22299975..a79b6088374b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -68,11 +68,12 @@ static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); /** - * vcn_v4_0_early_init - set function pointers + * vcn_v4_0_early_init - set function pointers and load microcode * * @handle: amdgpu_device pointer * * Set ring and irq function pointers + * Load microcode from filesystem */ static int vcn_v4_0_early_init(void *handle) { @@ -88,7 +89,7 @@ static int vcn_v4_0_early_init(void *handle) vcn_v4_0_set_irq_funcs(adev); vcn_v4_0_set_ras_funcs(adev); - return 0; + return amdgpu_vcn_early_init(adev); } /** From patchwork Thu Jan 5 03:42:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CE01C4708D for ; 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Wed, 4 Jan 2023 21:44:10 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 11/45] drm/amd: Load MES microcode during early_init Date: Wed, 4 Jan 2023 21:42:45 -0600 Message-ID: <20230105034327.1439-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|PH0PR12MB8006:EE_ X-MS-Office365-Filtering-Correlation-Id: 7c091472-07d1-47cd-370a-08daeecf1c41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z5Eb+Fpj82kz8WA3xiOe795UNtN8VS/gMqjvcn1V9Qk/vYyYfG8jHsNVfKvjzexbN1/b1SF7JcN3RprH+VKS+3Ul+TnMtdWIQ1i2aCNONLkPicbhCOIWreCLy3QOY8xdzxxoqUMVXYo/k5Pt8yTQZZLkebHJykl+hH5FwcVNaOY8OaNezwxOcVrJL8GFr7k7+9qbxrwp7ZGT7Jf0gj1CINkCcljM32J5KrTo03H8m1EeGzPfV/aWIt4E4K5mdZuUDqzywN+PcaMgMAkG/WmBo/bep12nurM4mSpK77PWjf8rXOd8X0WDn/C/EUK3vEE0lzwZe65jgkvRPlVaUwx2Rkel37/Gf7W6BrO8qCWbb0XsFvk43tGgaWoyYDuVLaqwp0sTeW8YoGcnsF9mxWxvrn/j1DYXUfeANfciydaFqw2ChP1lJZVd8Amq6SXX9XNKR/B38eW45Pb+VQ8Cm/WkeKYmKXcwe9Mx/jjr5t5LDQIXvUmuSRezYFj5q41KPKmvxw+K0p17Rt5Uv1P9zp11FPQlPuP0HVmnkhUcn40K8H2VZlLi10GMSCn8TvqV9M9kbq2NKI48ycGlYVjpptBdf6smreq9GFPTSLffv3r17YcOwyxU3JFQEZdGYOaJBreC2dVSvCPEgWxWZQOEZ9rBsH0u/fd1/ODJbxZlIBKkqGZHwsb86sjASgOYvRXluCtlHofSDFMSGgUvBWs+PA676VrPNBKgJePizRHJPUX92fA= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(39860400002)(136003)(396003)(346002)(451199015)(40470700004)(36840700001)(46966006)(356005)(40480700001)(186003)(36756003)(40460700003)(26005)(16526019)(86362001)(316002)(81166007)(478600001)(54906003)(110136005)(4326008)(6666004)(44832011)(2906002)(8676002)(70586007)(70206006)(8936002)(30864003)(36860700001)(5660300002)(41300700001)(426003)(82740400003)(82310400005)(7696005)(47076005)(83380400001)(2616005)(1076003)(336012)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:12.5554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c091472-07d1-47cd-370a-08daeecf1c41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8006 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add an early_init phase to MES for fetching and validating microcode from the filesystem. If MES microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for MES microcode into the early_init phase so that if it's not available, early_init will fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 65 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 + drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 97 +++++-------------------- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 88 +++++----------------- 4 files changed, 100 insertions(+), 151 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 0c546245793b..dd8f35234507 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -21,6 +21,8 @@ * */ +#include + #include "amdgpu_mes.h" #include "amdgpu.h" #include "soc15_common.h" @@ -1423,3 +1425,66 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev) kfree(vm); return 0; } + +int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) +{ + const struct mes_firmware_header_v1_0 *mes_hdr; + struct amdgpu_firmware_info *info; + char ucode_prefix[30]; + char fw_name[40]; + int r; + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", + ucode_prefix, + pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1"); + r = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); + if (r) + goto out; + + r = amdgpu_ucode_validate(adev->mes.fw[pipe]); + if (r) + goto out; + + mes_hdr = (const struct mes_firmware_header_v1_0 *) + adev->mes.fw[pipe]->data; + adev->mes.uc_start_addr[pipe] = + le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | + ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); + adev->mes.data_start_addr[pipe] = + le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | + ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + int ucode, ucode_data; + + if (pipe == AMDGPU_MES_SCHED_PIPE) { + ucode = AMDGPU_UCODE_ID_CP_MES; + ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; + } else { + ucode = AMDGPU_UCODE_ID_CP_MES1; + ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; + } + + info = &adev->firmware.ucode[ucode]; + info->ucode_id = ucode; + info->fw = adev->mes.fw[pipe]; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), + PAGE_SIZE); + + info = &adev->firmware.ucode[ucode_data]; + info->ucode_id = ucode_data; + info->fw = adev->mes.fw[pipe]; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), + PAGE_SIZE); + } + + return 0; + +out: + release_firmware(adev->mes.fw[pipe]); + adev->mes.fw[pipe] = NULL; + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 97c05d08a551..547ec35691fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -306,6 +306,7 @@ struct amdgpu_mes_funcs { int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); +int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); int amdgpu_mes_init(struct amdgpu_device *adev); void amdgpu_mes_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c index 614394118a53..9c5ff8b7c202 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c @@ -379,82 +379,6 @@ static const struct amdgpu_mes_funcs mes_v10_1_funcs = { .resume_gang = mes_v10_1_resume_gang, }; -static int mes_v10_1_init_microcode(struct amdgpu_device *adev, - enum admgpu_mes_pipe pipe) -{ - const char *chip_name; - char fw_name[30]; - int err; - const struct mes_firmware_header_v1_0 *mes_hdr; - struct amdgpu_firmware_info *info; - - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(10, 1, 10): - chip_name = "navi10"; - break; - case IP_VERSION(10, 3, 0): - chip_name = "sienna_cichlid"; - break; - default: - BUG(); - } - - if (pipe == AMDGPU_MES_SCHED_PIPE) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", - chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", - chip_name); - - err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (err) - return err; - - err = amdgpu_ucode_validate(adev->mes.fw[pipe]); - if (err) { - release_firmware(adev->mes.fw[pipe]); - adev->mes.fw[pipe] = NULL; - return err; - } - - mes_hdr = (const struct mes_firmware_header_v1_0 *) - adev->mes.fw[pipe]->data; - adev->mes.uc_start_addr[pipe] = - le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | - ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); - adev->mes.data_start_addr[pipe] = - le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | - ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); - - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - int ucode, ucode_data; - - if (pipe == AMDGPU_MES_SCHED_PIPE) { - ucode = AMDGPU_UCODE_ID_CP_MES; - ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; - } else { - ucode = AMDGPU_UCODE_ID_CP_MES1; - ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; - } - - info = &adev->firmware.ucode[ucode]; - info->ucode_id = ucode; - info->fw = adev->mes.fw[pipe]; - adev->firmware.fw_size += - ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), - PAGE_SIZE); - - info = &adev->firmware.ucode[ucode_data]; - info->ucode_id = ucode_data; - info->fw = adev->mes.fw[pipe]; - adev->firmware.fw_size += - ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), - PAGE_SIZE); - } - - return 0; -} - static void mes_v10_1_free_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { @@ -1019,10 +943,6 @@ static int mes_v10_1_sw_init(void *handle) if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) continue; - r = mes_v10_1_init_microcode(adev, pipe); - if (r) - return r; - r = mes_v10_1_allocate_eop_buf(adev, pipe); if (r) return r; @@ -1229,6 +1149,22 @@ static int mes_v10_1_resume(void *handle) return amdgpu_mes_resume(adev); } +static int mes_v10_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int pipe, r; + + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) + continue; + r = amdgpu_mes_init_microcode(adev, pipe); + if (r) + return r; + } + + return 0; +} + static int mes_v10_0_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1241,6 +1177,7 @@ static int mes_v10_0_late_init(void *handle) static const struct amd_ip_funcs mes_v10_1_ip_funcs = { .name = "mes_v10_1", + .early_init = mes_v10_0_early_init, .late_init = mes_v10_0_late_init, .sw_init = mes_v10_1_sw_init, .sw_fini = mes_v10_1_sw_fini, diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 970b066b37bb..3af77a32baac 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -459,73 +459,6 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { .misc_op = mes_v11_0_misc_op, }; -static int mes_v11_0_init_microcode(struct amdgpu_device *adev, - enum admgpu_mes_pipe pipe) -{ - char fw_name[30]; - char ucode_prefix[30]; - int err; - const struct mes_firmware_header_v1_0 *mes_hdr; - struct amdgpu_firmware_info *info; - - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - if (pipe == AMDGPU_MES_SCHED_PIPE) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", - ucode_prefix); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", - ucode_prefix); - - err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (err) - return err; - - err = amdgpu_ucode_validate(adev->mes.fw[pipe]); - if (err) { - release_firmware(adev->mes.fw[pipe]); - adev->mes.fw[pipe] = NULL; - return err; - } - - mes_hdr = (const struct mes_firmware_header_v1_0 *) - adev->mes.fw[pipe]->data; - adev->mes.uc_start_addr[pipe] = - le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | - ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); - adev->mes.data_start_addr[pipe] = - le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | - ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); - - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - int ucode, ucode_data; - - if (pipe == AMDGPU_MES_SCHED_PIPE) { - ucode = AMDGPU_UCODE_ID_CP_MES; - ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; - } else { - ucode = AMDGPU_UCODE_ID_CP_MES1; - ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; - } - - info = &adev->firmware.ucode[ucode]; - info->ucode_id = ucode; - info->fw = adev->mes.fw[pipe]; - adev->firmware.fw_size += - ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), - PAGE_SIZE); - - info = &adev->firmware.ucode[ucode_data]; - info->ucode_id = ucode_data; - info->fw = adev->mes.fw[pipe]; - adev->firmware.fw_size += - ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), - PAGE_SIZE); - } - - return 0; -} - static void mes_v11_0_free_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { @@ -1100,10 +1033,6 @@ static int mes_v11_0_sw_init(void *handle) if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) continue; - r = mes_v11_0_init_microcode(adev, pipe); - if (r) - return r; - r = mes_v11_0_allocate_eop_buf(adev, pipe); if (r) return r; @@ -1338,6 +1267,22 @@ static int mes_v11_0_resume(void *handle) return amdgpu_mes_resume(adev); } +static int mes_v11_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int pipe, r; + + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) + continue; + r = amdgpu_mes_init_microcode(adev, pipe); + if (r) + return r; + } + + return 0; +} + static int mes_v11_0_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1352,6 +1297,7 @@ static int mes_v11_0_late_init(void *handle) static const struct amd_ip_funcs mes_v11_0_ip_funcs = { .name = "mes_v11_0", + .early_init = mes_v11_0_early_init, .late_init = mes_v11_0_late_init, .sw_init = mes_v11_0_sw_init, .sw_fini = mes_v11_0_sw_fini, From patchwork Thu Jan 5 03:42:46 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:14.5553 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f06e59b-5401-449d-5dfd-08daeecf1d72 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4584 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper provides symmetry for releasing firmware. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 10 ++-------- drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 10 +--------- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 10 +--------- 3 files changed, 4 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index dd8f35234507..82e27bd4f038 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -1438,11 +1438,7 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", ucode_prefix, pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1"); - r = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (r) - goto out; - - r = amdgpu_ucode_validate(adev->mes.fw[pipe]); + r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], fw_name); if (r) goto out; @@ -1482,9 +1478,7 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) } return 0; - out: - release_firmware(adev->mes.fw[pipe]); - adev->mes.fw[pipe] = NULL; + amdgpu_ucode_release(&adev->mes.fw[pipe]); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c index 9c5ff8b7c202..7848b9de79ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c @@ -379,13 +379,6 @@ static const struct amdgpu_mes_funcs mes_v10_1_funcs = { .resume_gang = mes_v10_1_resume_gang, }; -static void mes_v10_1_free_microcode(struct amdgpu_device *adev, - enum admgpu_mes_pipe pipe) -{ - release_firmware(adev->mes.fw[pipe]); - adev->mes.fw[pipe] = NULL; -} - static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { @@ -979,8 +972,7 @@ static int mes_v10_1_sw_fini(void *handle) amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], &adev->mes.eop_gpu_addr[pipe], NULL); - - mes_v10_1_free_microcode(adev, pipe); + amdgpu_ucode_release(&adev->mes.fw[pipe]); } amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 3af77a32baac..a0125e103007 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -459,13 +459,6 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { .misc_op = mes_v11_0_misc_op, }; -static void mes_v11_0_free_microcode(struct amdgpu_device *adev, - enum admgpu_mes_pipe pipe) -{ - release_firmware(adev->mes.fw[pipe]); - adev->mes.fw[pipe] = NULL; -} - static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { @@ -1069,8 +1062,7 @@ static int mes_v11_0_sw_fini(void *handle) amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], &adev->mes.eop_gpu_addr[pipe], NULL); - - mes_v11_0_free_microcode(adev, pipe); + amdgpu_ucode_release(&adev->mes.fw[pipe]); } amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, From patchwork Thu Jan 5 03:42:47 2023 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT109.mail.protection.outlook.com (10.13.176.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5966.18 via Frontend Transport; Thu, 5 Jan 2023 03:44:16 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:44:14 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 13/45] drm/amd: Remove superfluous assignment for `adev->mes.adev` Date: Wed, 4 Jan 2023 21:42:47 -0600 Message-ID: <20230105034327.1439-14-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT109:EE_|SA0PR12MB4462:EE_ X-MS-Office365-Filtering-Correlation-Id: d63b3729-8901-4aef-976e-08daeecf1eb6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:16.6801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d63b3729-8901-4aef-976e-08daeecf1eb6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4462 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" `amdgpu_mes_init` already sets `adev->mes.adev`, so there is no need to also set it in the IP specific versions. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 - drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c index 7848b9de79ce..2e2062636d5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c @@ -924,7 +924,6 @@ static int mes_v10_1_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int pipe, r; - adev->mes.adev = adev; adev->mes.funcs = &mes_v10_1_funcs; adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index a0125e103007..a36b0f14ff92 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1013,7 +1013,6 @@ static int mes_v11_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int pipe, r; - adev->mes.adev = adev; adev->mes.funcs = &mes_v11_0_funcs; adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; From patchwork Thu Jan 5 03:42:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95810C54EBD for ; Thu, 5 Jan 2023 03:44:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CCC110E659; Thu, 5 Jan 2023 03:44:27 +0000 (UTC) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by gabe.freedesktop.org (Postfix) with ESMTPS id D485E10E650; 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Thu, 5 Jan 2023 03:44:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.17 via Frontend Transport; Thu, 5 Jan 2023 03:44:18 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:44:16 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 14/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX9 Date: Wed, 4 Jan 2023 21:42:48 -0600 Message-ID: <20230105034327.1439-15-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|PH8PR12MB6748:EE_ X-MS-Office365-Filtering-Correlation-Id: 80868753-3882-4205-4a03-08daeecf1f82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:18.0151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80868753-3882-4205-4a03-08daeecf1f82 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6748 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper will provide symmetry on unload. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 82 +++++++-------------------- 1 file changed, 21 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f202b45c413c..ef2dbebbc90c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1078,18 +1078,12 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); kfree(adev->gfx.rlc.register_list_format); } @@ -1257,43 +1251,28 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, int err; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.ce_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); out: if (err) { - dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); } return err; } @@ -1328,10 +1307,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; @@ -1340,13 +1316,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); out: - if (err) { - dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - } + if (err) + amdgpu_ucode_release(&adev->gfx.rlc_fw); + return err; } @@ -1371,12 +1343,9 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec_fw); - if (err) - goto out; + return err; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); @@ -1386,11 +1355,8 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { @@ -1402,17 +1368,11 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; } -out: gfx_v9_0_check_if_need_gfxoff(adev); gfx_v9_0_check_fw_write_wait(adev); if (err) { - dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); } return err; } From patchwork Thu Jan 5 03:42:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4710AC4708D for ; Thu, 5 Jan 2023 03:44:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57D6F10E658; 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Wed, 4 Jan 2023 21:44:18 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 15/45] drm/amd: Load GFX9 microcode during early_init Date: Wed, 4 Jan 2023 21:42:49 -0600 Message-ID: <20230105034327.1439-16-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|MN0PR12MB6270:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a47d2e2-7fe2-428e-23e0-08daeecf20c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UfEahBIEkYjIUsbqvDEzO1NtOaGycHcuNJfFAbQI0xXPZU7ToKd2j6s6HrqSLYtVt/Durdx4jwftOUJiOrh7x4c7p+U5B8Bj2rzdFXNVy98Z40skFVnSOEkSY+/zOLOHaQwggI0ghqd7cJ7Nn6rric8q3iK6GtMHFX7aj6ZWwzyVbg2W1f8iJzorN/GDdm6E4asxUexb+kpZr29mcp0NqkF9WTvPNRzeIG2wQkWBKl2EBna3Mwb4c+ZFG2joT1fiZBETTyHn8Xfe0BSfm4lLHMMA0vvLyzhBDVeD74Pj4YTEFIfMxf0XPBdrrAIKBTjEuFb6tqnaUw66HqfgaQYu44wF9arL/5O4Z3lN/Z4seZC9x4cPckAU26dOb7wrnieBC59NJzTaqi3mF7DcVG2Nqa52WQ9tvC2GEWVW9V0/9Nn19x9IpgMs6R1mRYLIQGTrmIpZ/CmS8afrK8MKkhE0z/B1V8Sj/Dtrc+N/PVqgjDVt2PWv8ZrG8FbwfPaYWYtF3ulj33e6GX5ChMAdYCwfGR+6ew/sbu5Lfz/HrBGjIrcNZUlcSmc73bFtvYzqCYBUss3PsXIBlrmHz6LiT32S93OWrwnraQ1/fc7sKnTmShU8e6CrtQk6HHOeRN+GjGuUlvpcL+GQUIZdAw1lhvm7CeE9Hy+3XutkzHHIcaw3XKIFhgcHtQ6sADAFqzeunIjcbqbYRzrq8LKbRVq/38fo0YP9q7AKsWn4i3CGMc+gt6I= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 58 +++++---------------------- 1 file changed, 9 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ef2dbebbc90c..0dba690cf7dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1245,7 +1245,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) } static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, - const char *chip_name) + char *chip_name) { char fw_name[30]; int err; @@ -1278,7 +1278,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, } static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, - const char *chip_name) + char *chip_name) { char fw_name[30]; int err; @@ -1333,7 +1333,7 @@ static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) } static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, - const char *chip_name) + char *chip_name) { char fw_name[30]; int err; @@ -1379,58 +1379,24 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; + char ucode_prefix[30]; int r; DRM_DEBUG("\n"); - - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(9, 0, 1): - chip_name = "vega10"; - break; - case IP_VERSION(9, 2, 1): - chip_name = "vega12"; - break; - case IP_VERSION(9, 4, 0): - chip_name = "vega20"; - break; - case IP_VERSION(9, 2, 2): - case IP_VERSION(9, 1, 0): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - case IP_VERSION(9, 4, 1): - chip_name = "arcturus"; - break; - case IP_VERSION(9, 3, 0): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - case IP_VERSION(9, 4, 2): - chip_name = "aldebaran"; - break; - default: - BUG(); - } + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); /* No CPG in Arcturus */ if (adev->gfx.num_gfx_rings) { - r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); + r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix); if (r) return r; } - r = gfx_v9_0_init_rlc_microcode(adev, chip_name); + r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix); if (r) return r; - r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); + r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix); if (r) return r; @@ -2118,12 +2084,6 @@ static int gfx_v9_0_sw_init(void *handle) adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; - r = gfx_v9_0_init_microcode(adev); - if (r) { - DRM_ERROR("Failed to load gfx firmware!\n"); - return r; - } - if (adev->gfx.rlc.funcs) { if (adev->gfx.rlc.funcs->init) { r = adev->gfx.rlc.funcs->init(adev); @@ -4565,7 +4525,7 @@ static int gfx_v9_0_early_init(void *handle) /* init rlcg reg access ctrl */ gfx_v9_0_init_rlcg_reg_access_ctrl(adev); - return 0; + return gfx_v9_0_init_microcode(adev); } static int gfx_v9_0_ecc_late_init(void *handle) From patchwork Thu Jan 5 03:42:50 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:22.4680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f9f5e89-7c14-4cf8-c098-08daeecf2229 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4476 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unload. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 71 ++++++++------------------ 1 file changed, 20 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 49d34c7bbf20..140bb18ff768 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3891,18 +3891,12 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); kfree(adev->gfx.rlc.register_list_format); } @@ -4030,41 +4024,31 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.ce_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); if (!amdgpu_sriov_vf(adev)) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); /* don't check this. There are apparently firmwares in the wild with * incorrect size in the header */ - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + if (err == -ENODEV) + goto out; if (err) dev_dbg(adev->dev, "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", @@ -4078,21 +4062,15 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { @@ -4103,21 +4081,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) gfx_v10_0_check_fw_write_wait(adev); out: if (err) { - dev_err(adev->dev, - "gfx10: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:24.2179 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4405a864-e7de-4ad6-c4f4-08daeecf2334 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7692 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Simplifies the code so that GFX10 will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Any failures will cause the driver to fail to probe before the firmware framebuffer has been removed. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 84 ++++++-------------------- 1 file changed, 18 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 140bb18ff768..6983acc456b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3968,9 +3968,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; char fw_name[40]; - char *wks = ""; + char ucode_prefix[30]; + const char *wks = ""; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; @@ -3978,71 +3978,31 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) DRM_DEBUG("\n"); - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(10, 1, 10): - chip_name = "navi10"; - break; - case IP_VERSION(10, 1, 1): - chip_name = "navi14"; - if (!(adev->pdev->device == 0x7340 && - adev->pdev->revision != 0x00)) - wks = "_wks"; - break; - case IP_VERSION(10, 1, 2): - chip_name = "navi12"; - break; - case IP_VERSION(10, 3, 0): - chip_name = "sienna_cichlid"; - break; - case IP_VERSION(10, 3, 2): - chip_name = "navy_flounder"; - break; - case IP_VERSION(10, 3, 1): - chip_name = "vangogh"; - break; - case IP_VERSION(10, 3, 4): - chip_name = "dimgrey_cavefish"; - break; - case IP_VERSION(10, 3, 5): - chip_name = "beige_goby"; - break; - case IP_VERSION(10, 3, 3): - chip_name = "yellow_carp"; - break; - case IP_VERSION(10, 3, 6): - chip_name = "gc_10_3_6"; - break; - case IP_VERSION(10, 1, 3): - case IP_VERSION(10, 1, 4): - chip_name = "cyan_skillfish2"; - break; - case IP_VERSION(10, 3, 7): - chip_name = "gc_10_3_7"; - break; - default: - BUG(); - } + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && + (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) + wks = "_wks"; + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); if (!amdgpu_sriov_vf(adev)) { - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); /* don't check this. There are apparently firmwares in the wild with * incorrect size in the header @@ -4051,7 +4011,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) goto out; if (err) dev_dbg(adev->dev, - "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", + "gfx10: amdgpu_ucode_request() failed \"%s\"\n", fw_name); rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; version_major = le16_to_cpu(rlc_hdr->header.header_version_major); @@ -4061,14 +4021,14 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) goto out; } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (!err) { amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); @@ -4077,6 +4037,8 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) err = 0; adev->gfx.mec2_fw = NULL; } + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); gfx_v10_0_check_fw_write_wait(adev); out: @@ -4239,19 +4201,11 @@ static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); } -static int gfx_v10_0_me_init(struct amdgpu_device *adev) +static void gfx_v10_0_me_init(struct amdgpu_device *adev) { - int r; - bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); amdgpu_gfx_graphics_queue_acquire(adev); - - r = gfx_v10_0_init_microcode(adev); - if (r) - DRM_ERROR("Failed to load gfx firmware!\n"); - - return r; } static int gfx_v10_0_mec_init(struct amdgpu_device *adev) @@ -4619,9 +4573,7 @@ static int gfx_v10_0_sw_init(void *handle) adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; - r = gfx_v10_0_me_init(adev); - if (r) - return r; + gfx_v10_0_me_init(adev); if (adev->gfx.rlc.funcs) { if (adev->gfx.rlc.funcs->init) { @@ -7599,7 +7551,7 @@ static int gfx_v10_0_early_init(void *handle) /* init rlcg reg access ctrl */ gfx_v10_0_init_rlcg_reg_access_ctrl(adev); - return 0; + return gfx_v10_0_init_microcode(adev); } static int gfx_v10_0_late_init(void *handle) From patchwork Thu Jan 5 03:42:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B717C54EBC for ; Thu, 5 Jan 2023 03:44:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FB0910E661; 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Wed, 4 Jan 2023 21:44:23 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 18/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX11 Date: Wed, 4 Jan 2023 21:42:52 -0600 Message-ID: <20230105034327.1439-19-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|PH7PR12MB6979:EE_ X-MS-Office365-Filtering-Correlation-Id: cbbb6a22-4d63-46a8-030f-08daeecf2409 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BhqtRLTQ7mHJqTPeBw0FsFQqu4gr0RbDGZ0K8jA7BeqGBrxbAx/h4EMT7saYKKOfFOXI6dibwXf5JNbvfVWottStSIocKSEv3TCuuQk1xd9OeXwzHbvrEOO8cHqHvnjOqkyN77eRIycsU4Vv6iizoMaRgFyCQgRY8rYkXaZFE1byyh2elFtmHFe9pAPENkMahIs07QN2rFxJX1I46UrX/I5PLmXPsbAHFVKLDNyDeV0mfbUt5jMgo3SvN+Uwdy+fT+aMxaABFCLEHxn2/0CWRjVdQI3LzBBVIRqKId6jwMH8j1Xl1gpsgHDTovOFoIaR2z4B7jcQUqj2LUvTJHoLm1IEWfbRNAA/CyDjOuJwwpHM08Nhp54DsZw4CpR9IIOLWbd8tbpF8IvNBSv55a6h/pRatXvqSYrKGrgcnhXN9OORkzQaXn2fr7o7qRMvdYxOEQ7rGgZN2mP+1iHQ5ToYZ83cOk8np6Qm5KnAMKH8QaC4M9XA9jdbXueyIziFnUNhm0J7pwmYXdK8RuzMH8re/1cHp3fYqNMUQwC81YrJC8Nd8rH0fiFV2LY6mYhr675uhI9H2UmKpZF11Rzs6u+iozjzuaL8PXS3fsXIzuzM7OaG9xnXgQXrXmsBw879Lnc9xrlz+MWqyUpzel2fZZPnmjWMZPsteGXulR5+xFsUj45il+PC1OMWNZAvrCBHC617Ypo2veEHYam99ZrunTUfiXN7y1ppfgiz5+KO1UDNHeHdScPbvAfcecQ62Agax2xHXO3KbvR8gEdNL7umW7J/WA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(46966006)(36840700001)(40470700004)(6666004)(26005)(16526019)(2906002)(478600001)(7696005)(186003)(70206006)(70586007)(4326008)(2616005)(8676002)(336012)(41300700001)(110136005)(426003)(40460700003)(316002)(47076005)(40480700001)(44832011)(83380400001)(82740400003)(5660300002)(36756003)(8936002)(54906003)(1076003)(86362001)(36860700001)(81166007)(82310400005)(356005)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:25.6089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbbb6a22-4d63-46a8-030f-08daeecf2409 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6979 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper will provide symmetery on unload. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 104 +++++++++---------------- drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 7 +- 2 files changed, 39 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a56c6e106d00..d4f67624d05b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -431,18 +431,39 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); kfree(adev->gfx.rlc.register_list_format); } +static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) +{ + const struct psp_firmware_header_v1_0 *toc_hdr; + int err = 0; + char fw_name[40]; + char ucode_prefix[30]; + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); + if (err) + goto out; + + toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; + adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); + adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); + adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); + adev->psp.toc.start_addr = (uint8_t *)toc_hdr + + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); + return 0; +out: + amdgpu_ucode_release(&adev->psp.toc_fw); + return err; +} + static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) { char fw_name[40]; @@ -457,10 +478,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ @@ -477,10 +495,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; if (adev->gfx.rs64_enable) { @@ -493,10 +508,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) if (!amdgpu_sriov_vf(adev)) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; @@ -508,10 +520,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; if (adev->gfx.rs64_enable) { @@ -530,54 +539,15 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - dev_err(adev->dev, - "gfx11: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); } return err; } -static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) -{ - const struct psp_firmware_header_v1_0 *toc_hdr; - int err = 0; - char fw_name[40]; - char ucode_prefix[30]; - - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); - err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->psp.toc_fw); - if (err) - goto out; - - toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; - adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); - adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); - adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); - adev->psp.toc.start_addr = (uint8_t *)toc_hdr + - le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); - return 0; -out: - dev_err(adev->dev, "Failed to load TOC microcode\n"); - release_firmware(adev->psp.toc_fw); - adev->psp.toc_fw = NULL; - return err; -} - static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) { u32 count = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index 95548c512f4f..ed0d368149aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -49,10 +49,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev) amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix); - err = request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.imu_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name); if (err) goto out; imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; @@ -77,7 +74,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev) dev_err(adev->dev, "gfx11: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gfx.imu_fw); + amdgpu_ucode_release(&adev->gfx.imu_fw); } return err; From patchwork Thu Jan 5 03:42:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39E53C5479D for ; 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Wed, 4 Jan 2023 21:44:25 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 19/45] drm/amd: Load GFX11 microcode during early_init Date: Wed, 4 Jan 2023 21:42:53 -0600 Message-ID: <20230105034327.1439-20-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|DM6PR12MB4449:EE_ X-MS-Office365-Filtering-Correlation-Id: f5d469a5-59ca-462d-662f-08daeecf2554 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 75tWbpKEqK9hhGZmeQFLOhrNgjVzEXTLrD0CTbmFQnIGsJ5qeV86lHl7pDveyJr3fV/nxjDX1C3CYe3bdmZ8pgGDLDvAXqLWCru9E/DFEU7/bx5DRSEE8n1LS49dZPFtGIoREFb2iI/I7iDGPsYaGaFFYDJwMRdhKXEPc6Nc8D7IUoP39wNjVfpdexy2rdhjev4HZTmobaYZSW2aLxCw8O5XDAnNw8sV7tan9uf1QIYEtJKDuzn4bVGLpcuUHIRIIRb0+tYkXpjoEdtns/GCY0mexKsc2H7ZSR8Is8FjTrQH8CnIOkwM82HIKpKO+Hm/eK7MYp2JxaAw+NHIgfS0t0kyNf9cbFDyizjfT/QQbtoHQQQ19Kr8ZLWQ3ZqXodi242PwWqpgoi62284SkFGQLy15HUE90J8qKmlxdw5qmis9oxYWgtmbIaJ/Gg7yPPoq0y8I/UmtZIAhtITdDcdP23IBNs1ZZN5YoHIzg81/971QdKMBZ6GjVTqteSLiMzIN0Ex8mc5sfeplZN05J4olHBm6FYPfy7TSaWYMFlowCX/gtP3dKuY30kk3V3JAVuPLcwmQr76sq0rPPhuvWK9pwicXyDaNGDQGuw5uSka8oLLZ2Iq/lIy344cvN5GoAXJnY0EvRraVrg69j1IFtq+T3CqmXr/uDbn5ky2/qn2t7jMmGbUhtKpWe9D4vjhUQXnN4c3Ars1kKu2EZ5vQwcbANGPy6A8StqVpTmzUB9OmcGg= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Move the request for GFX11 microcode into the early_init phase so that if it's not available, driver init will fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Rebase on earlier changes --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index d4f67624d05b..5cc329cf66c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -439,14 +439,12 @@ static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) kfree(adev->gfx.rlc.register_list_format); } -static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) +static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) { const struct psp_firmware_header_v1_0 *toc_hdr; int err = 0; char fw_name[40]; - char ucode_prefix[30]; - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); if (err) @@ -534,6 +532,9 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); } + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) + err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); + /* only one MEC for gfx 11.0.0. */ adev->gfx.mec2_fw = NULL; @@ -684,19 +685,11 @@ static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); } -static int gfx_v11_0_me_init(struct amdgpu_device *adev) +static void gfx_v11_0_me_init(struct amdgpu_device *adev) { - int r; - bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); amdgpu_gfx_graphics_queue_acquire(adev); - - r = gfx_v11_0_init_microcode(adev); - if (r) - DRM_ERROR("Failed to load gfx firmware!\n"); - - return r; } static int gfx_v11_0_mec_init(struct amdgpu_device *adev) @@ -1309,9 +1302,7 @@ static int gfx_v11_0_sw_init(void *handle) } } - r = gfx_v11_0_me_init(adev); - if (r) - return r; + gfx_v11_0_me_init(adev); r = gfx_v11_0_rlc_init(adev); if (r) { @@ -1379,9 +1370,6 @@ static int gfx_v11_0_sw_init(void *handle) /* allocate visible FB for rlc auto-loading fw */ if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { - r = gfx_v11_0_init_toc_microcode(adev); - if (r) - dev_err(adev->dev, "Failed to load toc firmware!\n"); r = gfx_v11_0_rlc_autoload_buffer_init(adev); if (r) return r; @@ -4650,7 +4638,7 @@ static int gfx_v11_0_early_init(void *handle) gfx_v11_0_init_rlcg_reg_access_ctrl(adev); - return 0; + return gfx_v11_0_init_microcode(adev); } static int gfx_v11_0_ras_late_init(void *handle) From patchwork Thu Jan 5 03:42:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25FD3C4708D for ; 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Wed, 4 Jan 2023 21:44:28 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 20/45] drm/amd: Parse both v1 and v2 TA microcode headers using same function Date: Wed, 4 Jan 2023 21:42:54 -0600 Message-ID: <20230105034327.1439-21-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT091:EE_|BN9PR12MB5163:EE_ X-MS-Office365-Filtering-Correlation-Id: 423a7a56-5be1-4e59-cf6a-08daeecf26da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JEgQONuPTolf1DlR4oesoJWSmZYe1pUF6C7xAVL22fmdvl8nn1Ewvn744gTLwFPp/ZlepTpP1yEaa4U1VVhn8OGvaUbdIuno4l/gLek2Os+Zj0xSa1HsvLv5/K4910mx8RvbEcIKR7Cp/kK23cCAAlSwAeAYMEUofXxtZvFKCSZZhJMSqS3OrxKyjASitaxwpqgGP7zbA1DvW3jFCj/N9Xbsfaaa2R699ZlN1kCeJ+rPbOTkNhO0EGPTU6vqbL7scqAdLVIqnU3s5EG311zfzQxC8m85SrmDZC9F9QRm8XgeKkg7625cl3Y2Nhs9X1h2E17LN3K2boCRxW9RBry6KI9FTgid9sk7dnjcJhlHVMbyAcFEQP9yDJRAmQAtTruv9n9Cb5YpYsa9UBnH/dtwuRz2NFYO4OnYGA/D+qpTf0AieTVEw4Vx4nMV38snRJX4tnmmzkgu618NE4qyU6dtZA+HJpfmaB/HaxeeZm0dkG8z2ACTn+0lUCUhfNquXwuKMlg2/ATRaFyJiclsT+yVq5jIaAHJE0fj/vppci35n1HdNTTYr5Wxza1qK02C+kcf3agv6n1Fbx+DixuiPo/r+H1Dfmm21mbRZYc0bJO53NpEaDkNcju4paW/EgXJOBsF9O0R237yJbTGZcuGKWe/Q11a/qNogVXhx+yCQ1GyQk8z7tGtqTP4Yfc+yk30oI+zgh2gYWKr3b/sIKO+ZA8II35hjB2o+GfdLjmtJ8YU9ko= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(396003)(346002)(136003)(39860400002)(376002)(451199015)(46966006)(40470700004)(36840700001)(8676002)(4326008)(5660300002)(70586007)(6666004)(70206006)(40460700003)(316002)(41300700001)(8936002)(54906003)(2906002)(110136005)(478600001)(7696005)(81166007)(356005)(82740400003)(16526019)(26005)(47076005)(2616005)(426003)(186003)(336012)(1076003)(36860700001)(36756003)(40480700001)(86362001)(44832011)(30864003)(82310400005)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:30.3392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 423a7a56-5be1-4e59-cf6a-08daeecf26da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5163 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Several IP versions duplicate code and can't use the common helpers. Move this code into a single function so that the helpers can be used. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello Reviewed-by: Lijo Lazar > --- v5->v6: * Rebase on earlier patches --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 120 ++++++++++++++++++------ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 64 +------------ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 77 ++------------- drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 62 +----------- 4 files changed, 109 insertions(+), 214 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 7a2fc920739b..d971e3785eaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3272,41 +3272,75 @@ static int parse_ta_bin_descriptor(struct psp_context *psp, return 0; } -int psp_init_ta_microcode(struct psp_context *psp, - const char *chip_name) +static int parse_ta_v1_microcode(struct psp_context *psp) { + const struct ta_firmware_header_v1_0 *ta_hdr; struct amdgpu_device *adev = psp->adev; - char fw_name[PSP_FW_NAME_LEN]; - const struct ta_firmware_header_v2_0 *ta_hdr; - int err = 0; - int ta_index = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for ta microcode\n"); + ta_hdr = (const struct ta_firmware_header_v1_0 *) + adev->psp.ta_fw->data; + + if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) return -EINVAL; + + adev->psp.xgmi_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->xgmi.fw_version); + adev->psp.xgmi_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->xgmi.size_bytes); + adev->psp.xgmi_context.context.bin_desc.start_addr = + (uint8_t *)ta_hdr + + le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); + adev->psp.ras_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->ras.fw_version); + adev->psp.ras_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->ras.size_bytes); + adev->psp.ras_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->ras.offset_bytes); + adev->psp.hdcp_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->hdcp.fw_version); + adev->psp.hdcp_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->hdcp.size_bytes); + adev->psp.hdcp_context.context.bin_desc.start_addr = + (uint8_t *)ta_hdr + + le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); + adev->psp.dtm_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->dtm.fw_version); + adev->psp.dtm_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->dtm.size_bytes); + adev->psp.dtm_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->dtm.offset_bytes); + if (adev->apu_flags & AMD_APU_IS_RENOIR) { + adev->psp.securedisplay_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->securedisplay.fw_version); + adev->psp.securedisplay_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->securedisplay.size_bytes); + adev->psp.securedisplay_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->securedisplay.offset_bytes); } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) - goto out; + return 0; +} - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out; +static int parse_ta_v2_microcode(struct psp_context *psp) +{ + const struct ta_firmware_header_v2_0 *ta_hdr; + struct amdgpu_device *adev = psp->adev; + int err = 0; + int ta_index = 0; ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; - if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { - dev_err(adev->dev, "unsupported TA header version\n"); - err = -EINVAL; - goto out; - } + if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) + return -EINVAL; if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); - err = -EINVAL; - goto out; + return -EINVAL; } for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { @@ -3314,14 +3348,46 @@ int psp_init_ta_microcode(struct psp_context *psp, &ta_hdr->ta_fw_bin[ta_index], ta_hdr); if (err) - goto out; + return err; } return 0; -out: - dev_err(adev->dev, "fail to initialize ta microcode\n"); - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; +} + +int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) +{ + const struct common_firmware_header *hdr; + struct amdgpu_device *adev = psp->adev; + char fw_name[PSP_FW_NAME_LEN]; + int err; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); + err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); + if (err) + return err; + err = amdgpu_ucode_validate(adev->psp.ta_fw); + if (err) + return err; + + hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; + switch (le16_to_cpu(hdr->header_version_major)) { + case 1: + err = parse_ta_v1_microcode(psp); + break; + case 2: + err = parse_ta_v2_microcode(psp); + break; + default: + dev_err(adev->dev, "unsupported TA header version\n"); + err = -EINVAL; + } + + if (err) { + dev_err(adev->dev, "fail to initialize ta microcode\n"); + release_firmware(adev->psp.ta_fw); + adev->psp.ta_fw = NULL; + } + return err; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 9de46fa8f46c..f14fcfb9c425 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -48,9 +48,8 @@ static int psp_v10_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; const char *chip_name; - char fw_name[30]; + char ucode_prefix[30]; int err = 0; - const struct ta_firmware_header_v1_0 *ta_hdr; DRM_DEBUG("\n"); switch (adev->asic_type) { @@ -64,66 +63,13 @@ static int psp_v10_0_init_microcode(struct psp_context *psp) break; default: BUG(); } + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp, ucode_prefix); if (err) - goto out; - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v10.0: Failed to load firmware \"%s\"\n", - fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out2; - - ta_hdr = (const struct ta_firmware_header_v1_0 *) - adev->psp.ta_fw->data; - adev->psp.hdcp_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->hdcp.fw_version); - adev->psp.hdcp_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->hdcp.size_bytes); - adev->psp.hdcp_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); - - adev->psp.dtm_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->dtm.fw_version); - adev->psp.dtm_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->dtm.size_bytes); - adev->psp.dtm_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->dtm.offset_bytes); - - adev->psp.securedisplay_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->securedisplay.fw_version); - adev->psp.securedisplay_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->securedisplay.size_bytes); - adev->psp.securedisplay_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->securedisplay.offset_bytes); - - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - } - - return 0; - -out2: - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; -out: - if (err) { - dev_err(adev->dev, - "psp v10.0: Failed to load firmware \"%s\"\n", - fw_name); - } + return err; - return err; + return psp_init_ta_microcode(psp, ucode_prefix); } static int psp_v10_0_ring_create(struct psp_context *psp, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index bd3e3e23a939..21d20ca2377a 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -89,9 +89,8 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; const char *chip_name; - char fw_name[PSP_FW_NAME_LEN]; + char ucode_prefix[30]; int err = 0; - const struct ta_firmware_header_v1_0 *ta_hdr; DRM_DEBUG("\n"); @@ -129,6 +128,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) default: BUG(); } + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); switch (adev->ip_versions[MP0_HWIP][0]) { @@ -140,35 +140,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) err = psp_init_asd_microcode(psp, chip_name); if (err) return err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out2; - - ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; - adev->psp.xgmi_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->xgmi.fw_version); - adev->psp.xgmi_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->xgmi.size_bytes); - adev->psp.xgmi_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - adev->psp.ras_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->ras.fw_version); - adev->psp.ras_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->ras.size_bytes); - adev->psp.ras_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->ras.offset_bytes); - } + err = psp_init_ta_microcode(psp, ucode_prefix); + if (err) + return err; break; case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 5): @@ -179,39 +153,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) err = psp_init_asd_microcode(psp, chip_name); if (err) return err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out2; - - ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; - adev->psp.hdcp_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->hdcp.fw_version); - adev->psp.hdcp_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->hdcp.size_bytes); - adev->psp.hdcp_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu( - ta_hdr->header.ucode_array_offset_bytes); - - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - - adev->psp.dtm_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->dtm.fw_version); - adev->psp.dtm_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->dtm.size_bytes); - adev->psp.dtm_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context - .bin_desc.start_addr + - le32_to_cpu(ta_hdr->dtm.offset_bytes); - } + err = psp_init_ta_microcode(psp, ucode_prefix); + if (err) + return err; break; case IP_VERSION(11, 0, 7): case IP_VERSION(11, 0, 11): @@ -237,11 +181,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) } return 0; - -out2: - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - return err; } static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index 8ed2281b6557..634fa2822d8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -49,9 +49,8 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; const char *chip_name; - char fw_name[30]; + char ucode_prefix[30]; int err = 0; - const struct ta_firmware_header_v1_0 *ta_hdr; DRM_DEBUG("\n"); switch (adev->asic_type) { @@ -64,67 +63,12 @@ static int psp_v12_0_init_microcode(struct psp_context *psp) default: BUG(); } + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); err = psp_init_asd_microcode(psp, chip_name); if (err) return err; - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v12.0: Failed to load firmware \"%s\"\n", - fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out; - - ta_hdr = (const struct ta_firmware_header_v1_0 *) - adev->psp.ta_fw->data; - adev->psp.hdcp_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->hdcp.fw_version); - adev->psp.hdcp_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->hdcp.size_bytes); - adev->psp.hdcp_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); - - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - - adev->psp.dtm_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->dtm.fw_version); - adev->psp.dtm_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->dtm.size_bytes); - adev->psp.dtm_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->dtm.offset_bytes); - - if (adev->apu_flags & AMD_APU_IS_RENOIR) { - adev->psp.securedisplay_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->securedisplay.fw_version); - adev->psp.securedisplay_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->securedisplay.size_bytes); - adev->psp.securedisplay_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->securedisplay.offset_bytes); - } - } - - return 0; - -out: - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - if (err) { - dev_err(adev->dev, - "psp v12.0: Failed to load firmware \"%s\"\n", - fw_name); - } - - return err; + return psp_init_ta_microcode(psp, ucode_prefix); } static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) From patchwork Thu Jan 5 03:42:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9C62C54EBC for ; Thu, 5 Jan 2023 03:44:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57D9E10E660; Thu, 5 Jan 2023 03:44:41 +0000 (UTC) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2069.outbound.protection.outlook.com [40.107.244.69]) by gabe.freedesktop.org (Postfix) with ESMTPS id E17A410E65B; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:31.7252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eec5fcda-6516-4ba9-4a2e-08daeecf27ae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4918 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" No need to crash the kernel. AMDGPU will now fail to probe. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index d971e3785eaf..a4a62753bfd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -380,7 +380,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp) adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; break; default: - BUG(); + ret = -EINVAL; break; } return ret; From patchwork Thu Jan 5 03:42:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 392BFC54EBC for ; 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Wed, 4 Jan 2023 21:44:32 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 22/45] drm/amd: Load PSP microcode during early_init Date: Wed, 4 Jan 2023 21:42:56 -0600 Message-ID: <20230105034327.1439-23-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT015:EE_|CH0PR12MB5043:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ca1c532-8c5c-4561-238e-08daeecf291f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BZ7Evy2kzaHNNN9i4GfPGm+D0NHC4vwcTs6lacRMV2GTxGJUtJ/XnB7LV9h0u9esSarYw8RzgjyWvryg9oJfmBII1A3BXqFaw/87VSFPDD9w9YaKaVnpdkxcEwyEO9/XWxIZp3iZyuAbBlNiXPdW5feaVMFjyi7aOElxXjDUm9kuzNzzaXQwzcXrhj0mMKsZDb8GyO+grrJ2nhgmpsIMp3wGRJ86LdhzSyKid/HL0oFZaNiKMstW6GY4uKoRFu4BrNEEKuDeWoSd2XsBQi4MOWZkWj4nZDXzPugpTshSslzyys6bJw/C/bcKaGQ7N62cvwV2L8WvNjthrbCk/va2bfosPtgV500CRD084wE+ZJ9pTiHOvV6zCHOUpAq32i+tx1QtfifgGqDfMQeTzfjefwztOSB/DSbBqXhy42PV9a7kaw/L0BcKx8E6qv33tHAlRsrdqEwTmgI6KsIcERwXiTqzxh/wocckRavEekeGV6IOrHVySPMkgVdu5wRZeBKyD1tifd/BRrLUVt/CUPhdYUEB8NyNpScLEKu/ILCcvkzs2MeV1Li5/w4b7VrAqqtUTMyDe9NZqzJvGTLhZobp+A5XQg4w4oEyWO8dDIPNMSZV4ewHT4YvPdATbMiGDX3RU+wkly8YmzfjmwD2m2jZOF5DKPpZ02B7AepRJapZh5czm2nISvuApdqVQXVnXJwffk4DZIQDR6kdqczP3zSa8JhG6faaZIxov/Ri26szgbw= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(39860400002)(136003)(396003)(376002)(451199015)(46966006)(36840700001)(40470700004)(6666004)(8936002)(86362001)(426003)(41300700001)(36860700001)(7696005)(47076005)(40460700003)(478600001)(82310400005)(336012)(5660300002)(82740400003)(83380400001)(70586007)(26005)(36756003)(44832011)(16526019)(1076003)(81166007)(4326008)(316002)(186003)(70206006)(8676002)(2616005)(110136005)(2906002)(356005)(30864003)(40480700001)(54906003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:34.1425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ca1c532-8c5c-4561-238e-08daeecf291f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5043 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Simplifies the code so that all PSP versions will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Any failures will cause the driver to fail to probe before the firmware framebuffer has been removed. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * rebase on earlier patches --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 120 +++++++++-------------- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 12 --- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 52 ++-------- drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 13 +-- drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 27 ++--- drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c | 14 +-- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 16 +-- 7 files changed, 69 insertions(+), 185 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a4a62753bfd6..beaca5846c73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -122,6 +122,44 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp } } +static int psp_init_sriov_microcode(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + char ucode_prefix[30]; + int ret = 0; + + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); + + switch (adev->ip_versions[MP0_HWIP][0]) { + case IP_VERSION(9, 0, 0): + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; + ret = psp_init_cap_microcode(psp, ucode_prefix); + break; + case IP_VERSION(11, 0, 9): + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; + ret = psp_init_cap_microcode(psp, ucode_prefix); + break; + case IP_VERSION(11, 0, 7): + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; + ret = psp_init_cap_microcode(psp, ucode_prefix); + break; + case IP_VERSION(13, 0, 2): + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; + ret = psp_init_cap_microcode(psp, ucode_prefix); + ret &= psp_init_ta_microcode(psp, ucode_prefix); + break; + case IP_VERSION(13, 0, 0): + adev->virt.autoload_ucode_id = 0; + break; + case IP_VERSION(13, 0, 10): + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; + break; + default: + return -EINVAL; + } + return ret; +} + static int psp_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -192,7 +230,10 @@ static int psp_early_init(void *handle) psp_check_pmfw_centralized_cstate_management(psp); - return 0; + if (amdgpu_sriov_vf(adev)) + return psp_init_sriov_microcode(psp); + else + return psp_init_microcode(psp); } void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) @@ -350,42 +391,6 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, return ret; } -static int psp_init_sriov_microcode(struct psp_context *psp) -{ - struct amdgpu_device *adev = psp->adev; - int ret = 0; - - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(9, 0, 0): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; - ret = psp_init_cap_microcode(psp, "vega10"); - break; - case IP_VERSION(11, 0, 9): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; - ret = psp_init_cap_microcode(psp, "navi12"); - break; - case IP_VERSION(11, 0, 7): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; - ret = psp_init_cap_microcode(psp, "sienna_cichlid"); - break; - case IP_VERSION(13, 0, 2): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; - ret = psp_init_cap_microcode(psp, "aldebaran"); - ret &= psp_init_ta_microcode(psp, "aldebaran"); - break; - case IP_VERSION(13, 0, 0): - adev->virt.autoload_ucode_id = 0; - break; - case IP_VERSION(13, 0, 10): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; - break; - default: - ret = -EINVAL; - break; - } - return ret; -} - static int psp_sw_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -401,15 +406,6 @@ static int psp_sw_init(void *handle) ret = -ENOMEM; } - if (amdgpu_sriov_vf(adev)) - ret = psp_init_sriov_microcode(psp); - else - ret = psp_init_microcode(psp); - if (ret) { - DRM_ERROR("Failed to load psp firmware!\n"); - return ret; - } - adev->psp.xgmi_context.supports_extended_data = !adev->gmc.xgmi.connected_to_cpu && adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); @@ -2908,19 +2904,13 @@ int psp_ring_cmd_submit(struct psp_context *psp, return 0; } -int psp_init_asd_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) { struct amdgpu_device *adev = psp->adev; char fw_name[PSP_FW_NAME_LEN]; const struct psp_firmware_header_v1_0 *asd_hdr; int err = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for asd microcode\n"); - return -EINVAL; - } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); if (err) @@ -2944,19 +2934,13 @@ int psp_init_asd_microcode(struct psp_context *psp, return err; } -int psp_init_toc_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) { struct amdgpu_device *adev = psp->adev; char fw_name[PSP_FW_NAME_LEN]; const struct psp_firmware_header_v1_0 *toc_hdr; int err = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for toc microcode\n"); - return -EINVAL; - } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); if (err) @@ -3107,8 +3091,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev) return 0; } -int psp_init_sos_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) { struct amdgpu_device *adev = psp->adev; char fw_name[PSP_FW_NAME_LEN]; @@ -3121,11 +3104,6 @@ int psp_init_sos_microcode(struct psp_context *psp, uint8_t *ucode_array_start_addr; int fw_index = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for sos microcode\n"); - return -EINVAL; - } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); if (err) @@ -3391,8 +3369,7 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) return err; } -int psp_init_cap_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) { struct amdgpu_device *adev = psp->adev; char fw_name[PSP_FW_NAME_LEN]; @@ -3400,11 +3377,6 @@ int psp_init_cap_microcode(struct psp_context *psp, struct amdgpu_firmware_info *info = NULL; int err = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for cap microcode\n"); - return -EINVAL; - } - if (!amdgpu_sriov_vf(adev)) { dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index f14fcfb9c425..e1b7fca09666 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -47,22 +47,10 @@ MODULE_FIRMWARE("amdgpu/raven_ta.bin"); static int psp_v10_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; char ucode_prefix[30]; int err = 0; DRM_DEBUG("\n"); - switch (adev->asic_type) { - case CHIP_RAVEN: - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - default: BUG(); - } amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); err = psp_init_asd_microcode(psp, ucode_prefix); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 21d20ca2377a..5fb572d3e42a 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -88,56 +88,20 @@ MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); static int psp_v11_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; char ucode_prefix[30]; int err = 0; DRM_DEBUG("\n"); - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(11, 0, 2): - chip_name = "vega20"; - break; - case IP_VERSION(11, 0, 0): - chip_name = "navi10"; - break; - case IP_VERSION(11, 0, 5): - chip_name = "navi14"; - break; - case IP_VERSION(11, 0, 9): - chip_name = "navi12"; - break; - case IP_VERSION(11, 0, 4): - chip_name = "arcturus"; - break; - case IP_VERSION(11, 0, 7): - chip_name = "sienna_cichlid"; - break; - case IP_VERSION(11, 0, 11): - chip_name = "navy_flounder"; - break; - case IP_VERSION(11, 5, 0): - chip_name = "vangogh"; - break; - case IP_VERSION(11, 0, 12): - chip_name = "dimgrey_cavefish"; - break; - case IP_VERSION(11, 0, 13): - chip_name = "beige_goby"; - break; - default: - BUG(); - } amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 4): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp, ucode_prefix); if (err) return err; err = psp_init_ta_microcode(psp, ucode_prefix); @@ -147,10 +111,10 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 5): case IP_VERSION(11, 0, 9): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp, ucode_prefix); if (err) return err; err = psp_init_ta_microcode(psp, ucode_prefix); @@ -161,18 +125,18 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) case IP_VERSION(11, 0, 11): case IP_VERSION(11, 0, 12): case IP_VERSION(11, 0, 13): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp, ucode_prefix); if (err) return err; break; case IP_VERSION(11, 5, 0): - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_toc_microcode(psp, chip_name); + err = psp_init_toc_microcode(psp, ucode_prefix); if (err) return err; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index 634fa2822d8a..45810e4a7e45 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -48,24 +48,13 @@ MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); static int psp_v12_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; char ucode_prefix[30]; int err = 0; DRM_DEBUG("\n"); - switch (adev->asic_type) { - case CHIP_RENOIR: - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - default: - BUG(); - } amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp, ucode_prefix); if (err) return err; return psp_init_ta_microcode(psp, ucode_prefix); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index e6a26a7e5e5e..d62fcc77af95 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -70,32 +70,19 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); static int psp_v13_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; char ucode_prefix[30]; int err = 0; - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(13, 0, 2): - chip_name = "aldebaran"; - break; - case IP_VERSION(13, 0, 1): - case IP_VERSION(13, 0, 3): - chip_name = "yellow_carp"; - break; - default: - amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - chip_name = ucode_prefix; - break; - } + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(13, 0, 2): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; /* It's not necessary to load ras ta on Guest side */ if (!amdgpu_sriov_vf(adev)) { - err = psp_init_ta_microcode(&adev->psp, chip_name); + err = psp_init_ta_microcode(psp, ucode_prefix); if (err) return err; } @@ -105,21 +92,21 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 8): case IP_VERSION(13, 0, 11): - err = psp_init_toc_microcode(psp, chip_name); + err = psp_init_toc_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp, ucode_prefix); if (err) return err; break; case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 7): case IP_VERSION(13, 0, 10): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; /* It's not necessary to load ras ta on Guest side */ - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp, ucode_prefix); if (err) return err; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c index 9d4e24e518e8..d5ba58eba3e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c @@ -35,25 +35,17 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin"); static int psp_v13_0_4_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; char ucode_prefix[30]; int err = 0; - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(13, 0, 4): - amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - chip_name = ucode_prefix; - break; - default: - BUG(); - } + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(13, 0, 4): - err = psp_init_toc_microcode(psp, chip_name); + err = psp_init_toc_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp, ucode_prefix); if (err) return err; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 157147c6c94e..f6b75e3e47ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -57,26 +57,18 @@ static int psp_v3_1_ring_stop(struct psp_context *psp, static int psp_v3_1_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; + char ucode_prefix[30]; int err = 0; DRM_DEBUG("\n"); - switch (adev->asic_type) { - case CHIP_VEGA10: - chip_name = "vega10"; - break; - case CHIP_VEGA12: - chip_name = "vega12"; - break; - default: BUG(); - } + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp, ucode_prefix); if (err) return err; From patchwork Thu Jan 5 03:42:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2885C5479D for ; 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Wed, 4 Jan 2023 21:44:34 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 23/45] drm/amd: Use `amdgpu_ucode_*` helpers for PSP Date: Wed, 4 Jan 2023 21:42:57 -0600 Message-ID: <20230105034327.1439-24-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT030:EE_|DM6PR12MB4910:EE_ X-MS-Office365-Filtering-Correlation-Id: 448cd07c-e859-4fad-dd97-08daeecf2a36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rjoKe8c/WbnM1DdRNZIInHQhzWeE9J4wB797tujkRPmYl2O/ozZ1WK8Kmm9Nno8b9KqIsfZuRZ3yQ22tE0jyMNiihlF/jG6AR4wK4xNQLDyDoyDyzk88Qi6QOC2i/glkkqqa7IwTc9yg7uRoMSRUkw36kvoH4V/HjzuqETxJ1O8HNFPoa1GSHQY/ac/Hvej81716y3dX6DiFmGPFRQd4BY5/FBAC4zvFrpzokvzhOcvBfxTaBjk29m14iVjIFk7/nS5qIKsNeBpaJo1wKXpx/eyVzA6SP1BMf4Jz8HbkEB3MsHyZipgKewfq/PMGFQbJO6XAUyAnMRo1STECbBCmGNFtubxMf1DnqZCXJJmBgw4ojjaBfTH694NwY+Ax6ByPodJd12n3HOXDaFea7tJPG/l56uf6aVL/PvPGkgKlSTRBKX2JQfVupKr9i321SpXAudKe1MJVGj+gUASxnM8p+epeZvgagcID69RrISYPkGHOxskWICpIpDR/BLnRUAv4ZIX/Mhle5xTRGwidm6A8W4SjHkZmP0WudovLAbCJJ/wq7tCK/vBLotjAacCWIpQMh3hZb63pcNO6vHIu2AEMpCuUF9OKVtpkKHdGTaNWKuiNqjOvF1IHOpT49smmhW5w0opEQDFVPhQFAJzl7aVRImRsYfuuRCNulh+v1CpO2aRA57FZGMC9JZsti0BoMb0ha10fop5cMXbjDsCklt/zquAdMXcG1WlYQccCzvkHT6EEyaPqxCu52IqLeUpywiLk19j9y7IMDMm2xLwE3ekfAA== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 80 +++++++------------------ 1 file changed, 21 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index beaca5846c73..aaef30bba97f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -510,20 +510,11 @@ static int psp_sw_fini(void *handle) psp_memory_training_fini(psp); - release_firmware(psp->sos_fw); - psp->sos_fw = NULL; - - release_firmware(psp->asd_fw); - psp->asd_fw = NULL; - - release_firmware(psp->ta_fw); - psp->ta_fw = NULL; - - release_firmware(psp->cap_fw); - psp->cap_fw = NULL; - - release_firmware(psp->toc_fw); - psp->toc_fw = NULL; + amdgpu_ucode_release(&psp->sos_fw); + amdgpu_ucode_release(&psp->asd_fw); + amdgpu_ucode_release(&psp->ta_fw); + amdgpu_ucode_release(&psp->cap_fw); + amdgpu_ucode_release(&psp->toc_fw); if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) @@ -2912,11 +2903,7 @@ int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) int err = 0; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); - err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->psp.asd_fw); + err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); if (err) goto out; @@ -2928,9 +2915,7 @@ int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); return 0; out: - dev_err(adev->dev, "fail to initialize asd microcode\n"); - release_firmware(adev->psp.asd_fw); - adev->psp.asd_fw = NULL; + amdgpu_ucode_release(&adev->psp.asd_fw); return err; } @@ -2942,11 +2927,7 @@ int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) int err = 0; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); - err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->psp.toc_fw); + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); if (err) goto out; @@ -2958,9 +2939,7 @@ int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); return 0; out: - dev_err(adev->dev, "fail to request/validate toc microcode\n"); - release_firmware(adev->psp.toc_fw); - adev->psp.toc_fw = NULL; + amdgpu_ucode_release(&adev->psp.toc_fw); return err; } @@ -3105,11 +3084,7 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) int fw_index = 0; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); - err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->psp.sos_fw); + err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); if (err) goto out; @@ -3181,10 +3156,7 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) return 0; out: - dev_err(adev->dev, - "failed to init sos firmware\n"); - release_firmware(adev->psp.sos_fw); - adev->psp.sos_fw = NULL; + amdgpu_ucode_release(&adev->psp.sos_fw); return err; } @@ -3340,10 +3312,7 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) int err; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) - return err; - err = amdgpu_ucode_validate(adev->psp.ta_fw); + err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); if (err) return err; @@ -3360,11 +3329,8 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) err = -EINVAL; } - if (err) { - dev_err(adev->dev, "fail to initialize ta microcode\n"); - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - } + if (err) + amdgpu_ucode_release(&adev->psp.ta_fw); return err; } @@ -3383,17 +3349,14 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); - err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); - if (err) { - dev_warn(adev->dev, "cap microcode does not exist, skip\n"); - err = 0; - goto out; - } - - err = amdgpu_ucode_validate(adev->psp.cap_fw); + err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); if (err) { + if (err == -ENODEV) { + dev_warn(adev->dev, "cap microcode does not exist, skip\n"); + err = 0; + goto out; + } dev_err(adev->dev, "fail to initialize cap microcode\n"); - goto out; } info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; @@ -3410,8 +3373,7 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) return 0; out: - release_firmware(adev->psp.cap_fw); - adev->psp.cap_fw = NULL; + amdgpu_ucode_release(&adev->psp.cap_fw); return err; } From patchwork Thu Jan 5 03:42:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66FB3C4708D for ; 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Wed, 4 Jan 2023 21:44:36 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 24/45] drm/amd/display: Load DMUB microcode during early_init Date: Wed, 4 Jan 2023 21:42:58 -0600 Message-ID: <20230105034327.1439-25-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT046:EE_|CO6PR12MB5396:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c857138-778a-426b-0226-08daeecf2c97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: N/D/CmSDRQI94f6g0FXsCaeWca8JTA6yyVw186s4SrMq0bAJFXdlBpIpECCOVNy8sdGtDCWOZcOlVO7Q8BEqhh4IJ9CEpBqQA+xnnD2Pi+W34a/OR4cZ9j6g2vnDKPbXabg0ALRWOHemaGbQz3j8u8qi39HWP3n2Xg3zqcqiRi86gFc5Ze7lOc5I5UmyZS8s3VAqyhY1cnZBftWlz73/HbdzX/5UpHzd2+vZzspL1Jv3Mn6sOfdZP+krYgoDcMLCwY3po1cVlXUUd+dWCWmFiER87nqy5e/2cm7lotb9AheH74mlmOVY1KUJzD7FXeUOFXAf/HWko+67Q5l9SCSyzNZFnfi7bUHCCzfilWFtaLnxv7hcyjds4US1O+iabNjwxM1P2e28B/63VrAiP8Aj858XggCNE5M0lOGMQoYwjKRn6q2bzL+xRjBOmfeT+dHKZMazFTvO3MEMuV40u3kPGisZ39LKmwST7QB6DxaOvou6mIfRStV7W2+j2pL2bpKeERBDpmALXy9u3LjYi8pHEv/vZxC7Phk+jeUlk9JaVU2bLoD0R/eIpSSbUo+vvs9Hh4G0eF/pAvmaPyENZM51XWAHNCB3qN45DiC3aJlHT4Q0KbYgxsTbcctN8nOAbFFUBZLBNjWTaozGzm6qiiqDvgmwLAAqVvT0sFjOh4gA2oALI64PgGvGJKIKomuw800kqFC/0JmLmlcxH/+JCn1HUgKZnRkYR9RCkMN3rUHZqAQ= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Any failures will cause the driver to fail to probe before the firmware framebuffer has been removed. Reviewed-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 89 ++++++++++++------- 1 file changed, 58 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4829b5431e4c..c8c5d37c8b3a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1945,7 +1945,6 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) struct dmub_srv_fb_info *fb_info; struct dmub_srv *dmub_srv; const struct dmcub_firmware_header_v1_0 *hdr; - const char *fw_name_dmub; enum dmub_asic dmub_asic; enum dmub_status status; int r; @@ -1953,73 +1952,46 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) switch (adev->ip_versions[DCE_HWIP][0]) { case IP_VERSION(2, 1, 0): dmub_asic = DMUB_ASIC_DCN21; - fw_name_dmub = FIRMWARE_RENOIR_DMUB; - if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) - fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; break; case IP_VERSION(3, 0, 0): - if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) { + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) dmub_asic = DMUB_ASIC_DCN30; - fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; - } else { + else dmub_asic = DMUB_ASIC_DCN30; - fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; - } break; case IP_VERSION(3, 0, 1): dmub_asic = DMUB_ASIC_DCN301; - fw_name_dmub = FIRMWARE_VANGOGH_DMUB; break; case IP_VERSION(3, 0, 2): dmub_asic = DMUB_ASIC_DCN302; - fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; break; case IP_VERSION(3, 0, 3): dmub_asic = DMUB_ASIC_DCN303; - fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; break; case IP_VERSION(3, 1, 2): case IP_VERSION(3, 1, 3): dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; - fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; break; case IP_VERSION(3, 1, 4): dmub_asic = DMUB_ASIC_DCN314; - fw_name_dmub = FIRMWARE_DCN_314_DMUB; break; case IP_VERSION(3, 1, 5): dmub_asic = DMUB_ASIC_DCN315; - fw_name_dmub = FIRMWARE_DCN_315_DMUB; break; case IP_VERSION(3, 1, 6): dmub_asic = DMUB_ASIC_DCN316; - fw_name_dmub = FIRMWARE_DCN316_DMUB; break; case IP_VERSION(3, 2, 0): dmub_asic = DMUB_ASIC_DCN32; - fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; break; case IP_VERSION(3, 2, 1): dmub_asic = DMUB_ASIC_DCN321; - fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; break; default: /* ASIC doesn't support DMUB. */ return 0; } - r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); - if (r) { - DRM_ERROR("DMUB firmware loading failed: %d\n", r); - return 0; - } - - r = amdgpu_ucode_validate(adev->dm.dmub_fw); - if (r) { - DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); - return 0; - } - hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); @@ -4513,6 +4485,61 @@ DEVICE_ATTR_WO(s3_debug); #endif +static int dm_init_microcode(struct amdgpu_device *adev) +{ + char *fw_name_dmub; + int r; + + switch (adev->ip_versions[DCE_HWIP][0]) { + case IP_VERSION(2, 1, 0): + fw_name_dmub = FIRMWARE_RENOIR_DMUB; + if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) + fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; + break; + case IP_VERSION(3, 0, 0): + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) + fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; + else + fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; + break; + case IP_VERSION(3, 0, 1): + fw_name_dmub = FIRMWARE_VANGOGH_DMUB; + break; + case IP_VERSION(3, 0, 2): + fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; + break; + case IP_VERSION(3, 0, 3): + fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; + break; + case IP_VERSION(3, 1, 2): + case IP_VERSION(3, 1, 3): + fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; + break; + case IP_VERSION(3, 1, 4): + fw_name_dmub = FIRMWARE_DCN_314_DMUB; + break; + case IP_VERSION(3, 1, 5): + fw_name_dmub = FIRMWARE_DCN_315_DMUB; + break; + case IP_VERSION(3, 1, 6): + fw_name_dmub = FIRMWARE_DCN316_DMUB; + break; + case IP_VERSION(3, 2, 0): + fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; + break; + case IP_VERSION(3, 2, 1): + fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; + break; + default: + /* ASIC doesn't support DMUB. */ + return 0; + } + r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); + if (r) + DRM_ERROR("DMUB firmware loading failed: %d\n", r); + return r; +} + static int dm_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -4645,7 +4672,7 @@ static int dm_early_init(void *handle) #endif adev->dc_enabled = true; - return 0; + return dm_init_microcode(adev); } static bool modereset_required(struct drm_crtc_state *crtc_state) From patchwork Thu Jan 5 03:42:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A360C54EBC for ; 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Wed, 4 Jan 2023 21:44:38 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 25/45] drm/amd: Use `amdgpu_ucode_release` helper for DMUB Date: Wed, 4 Jan 2023 21:42:59 -0600 Message-ID: <20230105034327.1439-26-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT046:EE_|BL3PR12MB6475:EE_ X-MS-Office365-Filtering-Correlation-Id: e1db5a86-f713-46e9-b3a7-08daeecf2d23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: idQowE7cAniKBOcQ2kDStIKu4EbONFRucrlAzAbVCZVfpC2Ev+AFM14JIF67iudYqaZeppYfWHeRWcviRvjFEn49IKPRYMyTnPNGLOu+nLwZgjmmtbeQvqSfiyPtMK17BeYR36rQbsfuf204L9VQw3lNmaUIo5QjuRviS4+TTdskeA6928fe5FY2Y1V9UomG10sWzWpkY/0is55NMkv3gRJThEcxRN26TWZWZF4qv8iIneWdGwWkcmbQmk59+46T90DayFpNqRZ2Q4zfNC6B7sRlDrTS+CQIWK9EQebBUngw4qGtwB62gviceTaxvuhoXs6PBWARN59eMwpSCmb9oPgmH2bfgpxRAaaBja38+Zq8E5QlIwIodbjUDu/r6zJazzJBFv9oL7Mw7NyZNVNmzTMZoevhJiCfHdLzj29nmbtIKPcmxs0Ff7GyGgTAB98/5Na7lx6g3wK40/w1PCFAY6geHU+8z+1Aw7xmGl5mJatfEdgdaCHzEeC4XtW35Chs7T0dTZi31yuibinZ731SA0+Sd7+UK6Y+BK0VNoAuDoZQuLhFe3hrbYK29h1sIm+//nBb4Y4rGDG36YZvHbG5NlGDOJdwwl8OFa0WWlHnf5yrq3O4o7/4e/tY9z9EilHM/AtALDpRn8qcxOxWqNM+XCsXMWgZybU/lCVdBMSMGXo7qfdVdqrWPILgEyEHGIggWFlXMMtgDNS2uDVrSaPAwa0VHydSkpjcqnX+wI4Za9S0soXEC6RGa0e/jUZocsjpD2NYEwJdCxuN2sWA8mKcpA== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello Reviewed-by: Harry Wentland --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c8c5d37c8b3a..61c192ead62f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1898,8 +1898,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) if (r) { dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", fw_name_dmcu); - release_firmware(adev->dm.fw_dmcu); - adev->dm.fw_dmcu = NULL; + amdgpu_ucode_release(&adev->dm.fw_dmcu); return r; } @@ -2113,11 +2112,8 @@ static int dm_sw_fini(void *handle) adev->dm.dmub_srv = NULL; } - release_firmware(adev->dm.dmub_fw); - adev->dm.dmub_fw = NULL; - - release_firmware(adev->dm.fw_dmcu); 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Thu, 5 Jan 2023 03:44:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT064.mail.protection.outlook.com (10.13.176.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5966.17 via Frontend Transport; Thu, 5 Jan 2023 03:44:42 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:44:40 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 26/45] drm/amd: Use `amdgpu_ucode_*` helpers for SMU Date: Wed, 4 Jan 2023 21:43:00 -0600 Message-ID: <20230105034327.1439-27-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT064:EE_|CH2PR12MB4889:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cab490f-8f8d-451a-7614-08daeecf2e08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:42.3825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cab490f-8f8d-451a-7614-08daeecf2e08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4889 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , Evan Quan , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 16 ++++------------ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 16 ++++------------ 2 files changed, 8 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index d4756bd30830..6492d69e2e60 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -109,10 +109,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); - err = request_firmware(&adev->pm.fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->pm.fw); + err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); if (err) goto out; @@ -130,12 +127,8 @@ int smu_v11_0_init_microcode(struct smu_context *smu) } out: - if (err) { - DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n", - fw_name); - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; - } + if (err) + amdgpu_ucode_release(&adev->pm.fw); return err; } @@ -143,8 +136,7 @@ void smu_v11_0_fini_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; + amdgpu_ucode_release(&adev->pm.fw); adev->pm.fw_version = 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 506a49a4b425..59d00fefc558 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -103,10 +103,7 @@ int smu_v13_0_init_microcode(struct smu_context *smu) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); - err = request_firmware(&adev->pm.fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->pm.fw); + err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); if (err) goto out; @@ -124,12 +121,8 @@ int smu_v13_0_init_microcode(struct smu_context *smu) } out: - if (err) { - DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n", - fw_name); - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; - } + if (err) + amdgpu_ucode_release(&adev->pm.fw); return err; } @@ -137,8 +130,7 @@ void smu_v13_0_fini_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; + amdgpu_ucode_release(&adev->pm.fw); adev->pm.fw_version = 0; } From patchwork Thu Jan 5 03:43:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E48EEC4708D for ; Thu, 5 Jan 2023 03:45:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD63810E68A; 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Wed, 4 Jan 2023 21:44:42 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 27/45] drm/amd: Load SMU microcode during early_init Date: Wed, 4 Jan 2023 21:43:01 -0600 Message-ID: <20230105034327.1439-28-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT107:EE_|CY8PR12MB7562:EE_ X-MS-Office365-Filtering-Correlation-Id: e3cac597-be9e-4994-ddff-08daeecf2f21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lUOjdaMKOcPPGvyRUxuyrCcAXdizQP/BM5bqMBkeukxggm3WpKUGQ2MlrsYRWt8pDX51YmDDNJV0B9PHM9qqFMSt5ONvMsNhOSQdM04613N0vNDC3lRI69GAmyEWyl0rU21BeC/tBz83VGGHO5Bcg+6MfctMY/GMuHA2huI47Rp1BuUxjbBTns0Cz1dcYDUn6C6E/UF/swu31rMVVQ38V2UmxjCMk10Nihyi38rpvWWX31/BghSVTPuDVbn+DQeH7SYXxYcr70HPpqGCMxWjPU4AvK191lhnhbZIkU2vdm1nc+6kpiCUlW8QpdAX3PM0UkMObRQLPlyn1AsMiO3rNIGy9j7gCYDenWANL6sEZASnTK7zYgm0cC5VhvtUXCDbfpKd2b/SiF19UFem28t7rwUyntEKPOsMWZSE7F28wSPasq+Ve+BuucGMccBkLUp4HsYy88XErMw5R/como0oqRQPUQYhTgVmc2U/9o9RkRVvF0y3tHMKp6Ce2Oi5ACr3D6yYO1RfucY/mktyf19WHfhFzRu/Bd1DY9MRGZFSfPIjsdUZX4+YHju5nw/9la4BpOQn7H6fqrFK3NHqcNhYZVw7RKnvSL7XUrGwME/HcM+p8fzDf4yfZraFPw5AlT30l3mrEX1Lh8759OprgyvMJVFdH8DP2J81fvP2zuFeGISGj8qQxu1g7RO2bffXLyyqIcIDtUvV63AT6MibxJKuLb5g1KN+7uDnX+muyrjA5Oo= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(346002)(39860400002)(396003)(376002)(451199015)(46966006)(40470700004)(36840700001)(5660300002)(2906002)(44832011)(8936002)(41300700001)(4326008)(8676002)(316002)(70206006)(70586007)(110136005)(54906003)(478600001)(7696005)(2616005)(1076003)(40480700001)(26005)(16526019)(186003)(6666004)(336012)(82310400005)(426003)(83380400001)(47076005)(82740400003)(81166007)(356005)(40460700003)(36860700001)(86362001)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:44.2267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3cac597-be9e-4994-ddff-08daeecf2f21 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7562 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , Evan Quan , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This will ensure that the microcode is available before the firmware framebuffer has been destroyed. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 2fa79f892a92..ec52830dde24 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -623,6 +623,7 @@ static int smu_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct smu_context *smu; + int r; smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); if (!smu) @@ -640,7 +641,10 @@ static int smu_early_init(void *handle) adev->powerplay.pp_handle = smu; adev->powerplay.pp_funcs = &swsmu_pm_funcs; - return smu_set_funcs(adev); + r = smu_set_funcs(adev); + if (r) + return r; + return smu_init_microcode(smu); } static int smu_set_default_dpm_table(struct smu_context *smu) @@ -1067,12 +1071,6 @@ static int smu_sw_init(void *handle) smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; - ret = smu_init_microcode(smu); - if (ret) { - dev_err(adev->dev, "Failed to load smu firmware!\n"); - return ret; - } - ret = smu_smc_table_sw_init(smu); if (ret) { dev_err(adev->dev, "Failed to sw init smc table!\n"); From patchwork Thu Jan 5 03:43:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7B93C46467 for ; Thu, 5 Jan 2023 03:45:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD80F10E677; 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Wed, 4 Jan 2023 21:44:44 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 28/45] drm/amd: Optimize SRIOV switch/case for PSP microcode load Date: Wed, 4 Jan 2023 21:43:02 -0600 Message-ID: <20230105034327.1439-29-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT103:EE_|DS0PR12MB8019:EE_ X-MS-Office365-Filtering-Correlation-Id: 91dfc648-911a-4ad3-2af5-08daeecf3039 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +ICosUsaeYYbNSThLE2QIeZFYO5aeP2NloH+3tVg/+S8dgcDtaFgrVSXlwvX0IPQtF5IyOEKD+jZSjitIcS+AKTljwLBK34obV9S14KWaSmbMR865o4WgFJofB4UvrTBMfsCQO5f34yYyQ0MQr1wb6LeJrS84zHtOmVKuhTyNfretMnhmKnpJN1vcCxDUX0MNmJIX21O4KwiOwYyAJPJJYtPCngezLrdAOkym6zDQNBF/Pc8JsXD+Hkg8tVjFcE0uCraRCTkRr3JFy6F2Ef0alWr/PdhegO6m8hD1sRnzoDwMvcblCfvZILUyFxQPpKVht/VN6bphdXN5iUfz3KTVFGHy+wmFnyP5P6eA33jfCSgF6u+nfzYUTEG3xMC+0/v2UgnU9wx+uEoctbR0MIqJzZUnYfkJjieFFTPOZvmnhAhwqArLF9HlCInK6CC5+aCrE+jgLy9vxbmQwe/Q9ySux879nr8Z8riCij6OXf+oAoor6vG6IXn/z4ACaYP5E+cSpyzZ6b8qZ1FqmIP8QNAun5r1SFDW6I0BvS50KVRgRba3FfplaDU0j8Z07uu+GLSHyn9v8u1zi0jau6LX2pvBTxjM/zo0JvXfmDLRWECqee2yS8UiI+3eeOESXBfWjSS5ukFWgnB8DKmAIqZHeOGaGKcA2u5+8I/67xQLrLzvtk2ckE29fFg9/sffUnkOS34lWKMRdAHX4Ds74tZGI9S915vwBQ7sMiiC52ddb5rrFA= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index aaef30bba97f..380e08affc25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -132,14 +132,8 @@ static int psp_init_sriov_microcode(struct psp_context *psp) switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(9, 0, 0): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; - ret = psp_init_cap_microcode(psp, ucode_prefix); - break; - case IP_VERSION(11, 0, 9): - adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; - ret = psp_init_cap_microcode(psp, ucode_prefix); - break; case IP_VERSION(11, 0, 7): + case IP_VERSION(11, 0, 9): adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; ret = psp_init_cap_microcode(psp, ucode_prefix); break; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:47.9416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9fc3ad1-d9f8-4b66-b6d5-08daeecf3158 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8051 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 30 +++++++-------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 204b246f0e3f..438eab348fc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -338,10 +338,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; @@ -349,10 +346,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; @@ -360,10 +354,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.ce_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; @@ -371,10 +362,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); @@ -382,14 +372,10 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) out: if (err) { pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); 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Thu, 5 Jan 2023 03:44:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT104.mail.protection.outlook.com (10.13.177.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5966.17 via Frontend Transport; Thu, 5 Jan 2023 03:44:49 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:44:48 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 30/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX7 Date: Wed, 4 Jan 2023 21:43:04 -0600 Message-ID: <20230105034327.1439-31-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT104:EE_|CY5PR12MB6275:EE_ X-MS-Office365-Filtering-Correlation-Id: 48769525-4677-4171-f622-08daeecf3273 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:49.8135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48769525-4677-4171-f622-08daeecf3273 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6275 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 68 +++++++-------------------- 1 file changed, 17 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 0f2976507e48..646999ad4f04 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -887,6 +887,16 @@ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *bu static void gfx_v7_0_init_pg(struct amdgpu_device *adev); static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); +static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) +{ + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); +} + /* * Core functions */ @@ -927,88 +937,44 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.ce_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; if (adev->asic_type == CHIP_KAVERI) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (err) goto out; } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); - out: if (err) { pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; + gfx_v7_0_free_microcode(adev); } return err; } -static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) -{ - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; -} - /** * gfx_v7_0_tiling_mode_table_init - init the hw tiling table * From patchwork Thu Jan 5 03:43:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0573BC46467 for ; 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The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 94 ++++++++++----------------- 1 file changed, 33 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index d47135606e3e..04577e5234ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -924,20 +924,14 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); if ((adev->asic_type != CHIP_STONEY) && (adev->asic_type != CHIP_TOPAZ)) - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.mec2_fw); kfree(adev->gfx.rlc.register_list_format); } @@ -989,18 +983,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err == -ENOENT) { + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); + if (err == -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); } - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; @@ -1009,18 +1000,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err == -ENOENT) { + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); + if (err == -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); } - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; @@ -1030,18 +1018,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err == -ENOENT) { + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); + if (err == -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); } - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.ce_fw); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; @@ -1060,10 +1045,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->virt.chained_ib_support = false; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); @@ -1110,18 +1094,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err == -ENOENT) { + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); + if (err == -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); } - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; @@ -1132,19 +1113,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) (adev->asic_type != CHIP_TOPAZ)) { if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (err == -ENOENT) { + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); + if (err == -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); } if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; cp_hdr = (const struct gfx_firmware_header_v1_0 *) adev->gfx.mec2_fw->data; adev->gfx.mec2_fw_version = @@ -1219,18 +1197,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) dev_err(adev->dev, "gfx8: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); } return err; } From patchwork Thu Jan 5 03:43:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 657BAC4708D for ; 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Wed, 4 Jan 2023 21:44:51 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 32/45] drm/amd: Use `amdgpu_ucode_*` helpers for GMC6 Date: Wed, 4 Jan 2023 21:43:06 -0600 Message-ID: <20230105034327.1439-33-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|DS7PR12MB8276:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d4bf051-8f69-40de-20fd-08daeecf348a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DCkEWdOvBg11Bd1a5tnfjL/15iWPs//L7ddoWXjWvKnXAh3168AiiO1AgxqXWPhQ2q8Pz5aXxlgHzYF8cVXA641VbYxMXtZffUpHC9gvw5AoOFUR2TQhGPyeW/rqjwUe7RyU0Lwp00IXctmI66l+20S1YEaA+S5pnN24LbPmVKSraOxbeWoDnHzKcbHCk9oD5qBopOfOPJR9JcpeRZwLKiRa97GlGh8KxIPBNthVGYVTBEytiD7D6iBXTu+GtqIyeChxz46fc+QWKkOLjJQeJALdlJb4Ar17jDPEuSrPevvCnioDpnbTrefuXuq+ytOCuedjtQayAjZzH2BMxYVPQ7kgzqAf81CBqE7ZXuj9oniR18RTCpfqhhZJPLD28dQuzNOzrk+jsj/TTtYSxKOgKnHUeVdLOHwLSykiJhmbc95nnlgRIBRa13ERvKi4gIb3nJKQ3LVbWA95/IRVW14CSRdUN1ZLRq1zr7xHVUMLEz2x/fdeh8rT9KFbhn9J7YifLvn9rasL+UTX2wk66cTWdoJYGfNED8nBPUpF5d7AvK1QImaNVnhDyUTihLTEIpdWk19Bks5ygOH4Wi5WIA7YoeZYzKOOl+LOPg52guFTA+fcfDC1H6IKYbx+iPc9h0O96aQlhXYJWKSK0IEJz4WdevCHce3RcEOAL0L4oiCFk4+AFLXex8rAbVkYy5UiZPmjCU8qbUnLOVfzoURQU7lkLdH6zLJnYZGiQI7exM+wkeMCHBVjOZ/85Rrha/cf7hM3QU9JFggGTeoR/XRZ4pirRQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199015)(46966006)(36840700001)(40470700004)(47076005)(426003)(83380400001)(82310400005)(16526019)(26005)(336012)(2616005)(186003)(6666004)(1076003)(40480700001)(7696005)(86362001)(40460700003)(36860700001)(36756003)(82740400003)(356005)(81166007)(41300700001)(4326008)(8676002)(2906002)(5660300002)(44832011)(8936002)(478600001)(70206006)(54906003)(70586007)(316002)(110136005)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:53.2986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d4bf051-8f69-40de-20fd-08daeecf348a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8276 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index ec291d28edff..d154ab48f507 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -131,19 +131,12 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin"); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); - err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->gmc.fw); - -out: + err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); if (err) { dev_err(adev->dev, "si_mc: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gmc.fw); - adev->gmc.fw = NULL; + amdgpu_ucode_release(&adev->gmc.fw); } return err; } @@ -894,8 +887,7 @@ static int gmc_v6_0_sw_fini(void *handle) amdgpu_vm_manager_fini(adev); amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); - release_firmware(adev->gmc.fw); - adev->gmc.fw = NULL; + amdgpu_ucode_release(&adev->gmc.fw); return 0; } From patchwork Thu Jan 5 03:43:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9962CC54EBC for ; Thu, 5 Jan 2023 03:45:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8938010E685; 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Wed, 4 Jan 2023 21:44:53 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 33/45] drm/amd: Use `amdgpu_ucode_*` helpers for GMC7 Date: Wed, 4 Jan 2023 21:43:07 -0600 Message-ID: <20230105034327.1439-34-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT086:EE_|DM4PR12MB6566:EE_ X-MS-Office365-Filtering-Correlation-Id: 5913e84e-3f4b-4d5f-8f27-08daeecf3578 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nwmmSFzNSlr+Tyyl8Zd5V9fQ4dc/fbFVQPstCcjAAyqIQ5ml9WTgZByJtHYeoWI7s9pprRF8XJxLode+YF9XFEfv/zV09vuVIkZNlbUTj+mQl8+XrjgGBFxzrpu0fAETr9jeaQ5J8ayZP49ad5BiGgNc3F2R5jpI+saJ+1b9GjjE2+gg356Qwu62z+vd1XYTWJ9H9NSNhFlyKJzpfYk0hYbTw0vVaM0iBv/VIkrPOsXXvwokd9X7R+Vy06YuGQRa+P+Pvz1V7GLzqq3OX9zqiicn3gjy7GwxkUzGDtYxJY4WcofOB0goi9feavINRw2bScEz5qvVSHOxZdav/WC83QLpECIdevV+0MDyVMZ1QwOikNnVvEcFDqgssT1kPwIVlsOg2UUJaUGKAyUhdn8AvPr4o2Vvvu0ivpO3vA+s32uXArvqBMury6V87W8BiBD0nEzQib8NqwKUgW0f6UXz/zZ9UHbJLxIk/lvXqmuuKtUOUVY+fHgUaU4v7ICINbxyLF6ax81YKcfURiUMt+RUHsYS3UGEsF0Vm+IfVq2K0x3t/XnujbXJkublMlisi+Q77vdQYk02TCKGtAJUANxLBpmQs8vdY4OcsMs7xnay9KJGOnoL5EV9/Ew2qEvaxRaNUKiuU3mQ9N7313pwG3X4gKBsmjMeFMcCc/1Jyc3LIllLhFbAEQbL0oK2M1ZYGLI0kbSUAtCWcSQhPAIAXlL1ju9S7H8tc646rybLPzbOHDU+JyQ9EUlSmtRcpONwXrozBHsG/AM2s9fOzajBhrcmyw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199015)(36840700001)(46966006)(40470700004)(54906003)(186003)(26005)(1076003)(110136005)(6666004)(70206006)(478600001)(2616005)(16526019)(4326008)(83380400001)(336012)(44832011)(8676002)(8936002)(426003)(5660300002)(47076005)(41300700001)(2906002)(316002)(70586007)(36860700001)(82740400003)(40480700001)(356005)(81166007)(40460700003)(86362001)(7696005)(36756003)(82310400005)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:54.8455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5913e84e-3f4b-4d5f-8f27-08daeecf3578 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6566 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 979da6f510e8..4412e8c65726 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -156,16 +156,10 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); - err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gmc.fw); - -out: + err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); if (err) { pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gmc.fw); - adev->gmc.fw = NULL; + amdgpu_ucode_release(&adev->gmc.fw); } return err; } @@ -1081,8 +1075,7 @@ static int gmc_v7_0_sw_fini(void *handle) kfree(adev->gmc.vm_fault_info); amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); - release_firmware(adev->gmc.fw); - adev->gmc.fw = NULL; + amdgpu_ucode_release(&adev->gmc.fw); return 0; } From patchwork Thu Jan 5 03:43:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A050DC5479D for ; Thu, 5 Jan 2023 03:45:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BE0710E68F; Thu, 5 Jan 2023 03:45:10 +0000 (UTC) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2080.outbound.protection.outlook.com [40.107.244.80]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5323610E67B; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:56.4104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02b094c3-4b4a-4d0c-f60c-08daeecf3664 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5135 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 382dde1ce74c..561daac2e6f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -264,16 +264,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); - err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gmc.fw); - -out: + err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); if (err) { pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gmc.fw); - adev->gmc.fw = NULL; + amdgpu_ucode_release(&adev->gmc.fw); } return err; } @@ -1203,8 +1197,7 @@ static int gmc_v8_0_sw_fini(void *handle) kfree(adev->gmc.vm_fault_info); amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); - release_firmware(adev->gmc.fw); - adev->gmc.fw = NULL; + amdgpu_ucode_release(&adev->gmc.fw); return 0; } From patchwork Thu Jan 5 03:43:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5EAAC5479D for ; Thu, 5 Jan 2023 03:45:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3F7110E683; Thu, 5 Jan 2023 03:45:05 +0000 (UTC) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2076.outbound.protection.outlook.com [40.107.223.76]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1F5410E67A; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:57.9514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de8c4f7d-b465-46be-1776-08daeecf3750 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8352 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index c52d246a1d96..fd2a7b66ac56 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -113,10 +113,9 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) { int i; - for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); - adev->sdma.instance[i].fw = NULL; - } + + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ucode_release(&adev->sdma.instance[i].fw); } /** @@ -151,10 +150,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); + err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); if (err) goto out; hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; @@ -176,10 +172,8 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) out: if (err) { pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); - for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); - adev->sdma.instance[i].fw = NULL; - } + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ucode_release(&adev->sdma.instance[i].fw); } return err; } From patchwork Thu Jan 5 03:43:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92CFCC46467 for ; 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Wed, 4 Jan 2023 21:44:58 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 36/45] drm/amd: Use `amdgpu_ucode_*` helpers for SDMA3.0 Date: Wed, 4 Jan 2023 21:43:10 -0600 Message-ID: <20230105034327.1439-37-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT107:EE_|PH7PR12MB6467:EE_ X-MS-Office365-Filtering-Correlation-Id: 5916db2a-7865-4bf8-2fe4-08daeecf3842 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zhSjGEp8NAkVeWgBrjnfxCXEj4AFdXwOBb1oeVg8pLCYgCzcioMywNvv1SB99miXpOUaErLLnNmBlpUZrTHeL8EHRm0ZIN9yyEdCj6sfjX7073Rgp74jjIA+0nBkSIC7ce42sGzg+hKSsEG61kdZ3C3V/LjOGH+9qDYn05WudbnxmxnAYd3cvVVNefKCCf/hQzhfWn7v5R2lgrDT3SwWxEEeFWBeA4jasIF/CJhqYrQ5wEZEjpN+WkplexPorxmKdcjCaF/WSSD+n1pAku6INeC4WTA5mJU7isdLzjmOh6TkJeH1oDQnXxvPNlSWsdkhZmzQEhmozPh7Ge6LqzLKlj9z/JMK8+Kk2ASdadrQWt/exPOjL/DnqfEN11ahc5Nv2jSyoEd5cPN7qK8tz1s2Rwo1YcU4Jydo5/vVylbtwda3WHW4UpqRpio7adAtFKdDMJ1dI97inbA5j/2jv5SP+TGjevzTlU/eagQXJ+PWgpw5weuVN3OQ4uxlo7K9C7j0wfRqKPddEZkVfhDeyw72VHTRGVuAvJHTk4zA1dipSjC+CPH95tyi2xILp4BibC56gwod2EsE2H23hxhiKhOnz8wCSJv4u0zag6DQaKj9HaQ0hpX7FpJrtr0ly8ObfmjCs3uhGXw16hYR6vLFxZhxjTgDlErxIe8Kzulb0gQjs4vf3+WCGPVgLu5FhCbihhZjhP3tYSsy5F7smtV3nStgM0Pk9bOWeUTxFkTxlifxihezMOS4avjpghDudwk+jnXQ X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(44832011)(8936002)(356005)(5660300002)(82740400003)(2906002)(83380400001)(426003)(36860700001)(47076005)(86362001)(41300700001)(54906003)(70586007)(70206006)(81166007)(110136005)(40480700001)(82310400005)(6666004)(7696005)(4326008)(40460700003)(478600001)(2616005)(16526019)(1076003)(186003)(316002)(8676002)(26005)(336012)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:59.5380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5916db2a-7865-4bf8-2fe4-08daeecf3842 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6467 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 486d9b5c1b9e..e572389089d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -250,10 +250,9 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) { int i; - for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); - adev->sdma.instance[i].fw = NULL; - } + + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ucode_release(&adev->sdma.instance[i].fw); } /** @@ -309,10 +308,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); + err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); if (err) goto out; hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; @@ -332,10 +328,8 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) out: if (err) { pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); - for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); - adev->sdma.instance[i].fw = NULL; - } + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ucode_release(&adev->sdma.instance[i].fw); } return err; } From patchwork Thu Jan 5 03:43:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6D2FC4708D for ; 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Wed, 4 Jan 2023 21:44:59 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 37/45] drm/amd: Use `amdgpu_ucode_*` helpers for SDMA on CIK Date: Wed, 4 Jan 2023 21:43:11 -0600 Message-ID: <20230105034327.1439-38-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT077:EE_|BL0PR12MB4930:EE_ X-MS-Office365-Filtering-Correlation-Id: e14b20f7-6450-4248-7ee9-08daeecf3d1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: I2LMU4xAyUN/6AXFj3EsiClDN8n7BWWV0q80/C+a0wN3U6IUvKbF2+wSZ5/cncoKR8gTbUo9AWt9Z3ePB+ktfNTisPdPoiv7qYeUeIG1lUQq3pS22jmBtFUcK2YoS2DsCqp0WBP81KrqamPXoGzcIO0kwVNqorY8HIOnZGmJooLO3z6bvGEV5JHWaYK1GxIDiwXCjbjD6XlLD8OChdl4hDTug8XX1pEjfmtB09NSKQga7FCTYXInmLhPm+l4i0Ghe/bc3X8jS/n3hb/etVklAVQK4ShX4d8VkBtle6k7xNi6akns0txZYmAKv1QBlE+NvYnQmbXVIYJ9UUuJea0m/dZgfXGuA0aOmFmxMCg4/LXzPK4ku2P24KmYptCrTyYImuss5E6nTn7KTkF6uu53ZO71vea0xFpIcNFzca75oArix2UAnAI/TApNAkL4uLsJzvcsf1+EVWBovoYt5Rt+V+cXDjfx7kqHrLKUfbSipyfo1jJiNpRWrNhn5JujleNUJ/4FhyIYeT8FZfRJGXMHOLBe6Vv7iZZ8iQhwKg4aVovKWhCuKEVMD0Q+MeahCxTf2rNMV+kADTRjHb/OdDrMH0gIGfyrkWPAlsXehrDnj2HvJBML5lsnb9vlKJJmKXNkJXo4NIHfDTZT4UKDXF3Svv+Wpz+5eHYyKk5+t8Iuj2qMbVdr2t12ukrEhVBSazsjI3/Hbbqpys+vIA6YpwX+Z0Pc5BmK7N4JGV9WH7ppUkoL6jvUIEJZEqY9JC7mbAXAOvKh4WFcE5hhx/4FWHyKPQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index cbca9866645c..67d16236b216 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -73,10 +73,9 @@ u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); static void cik_sdma_free_microcode(struct amdgpu_device *adev) { int i; - for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); - adev->sdma.instance[i].fw = NULL; - } + + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ucode_release(&adev->sdma.instance[i].fw); } /* @@ -137,18 +136,15 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); if (err) goto out; - err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); } out: if (err) { pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); - for (i = 0; i < adev->sdma.num_instances; i++) { - release_firmware(adev->sdma.instance[i].fw); - adev->sdma.instance[i].fw = NULL; - } + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ucode_release(&adev->sdma.instance[i].fw); } return err; } From patchwork Thu Jan 5 03:43:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63978C4708D for ; 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Wed, 4 Jan 2023 21:45:01 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 38/45] drm/amd: Use `amdgpu_ucode_*` helpers for UVD Date: Wed, 4 Jan 2023 21:43:12 -0600 Message-ID: <20230105034327.1439-39-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT077:EE_|SJ0PR12MB6965:EE_ X-MS-Office365-Filtering-Correlation-Id: cef281ce-4341-4af6-418a-08daeecf3d43 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h3jTE+f8qRwYTrwXI+SrQi8HtGatYnS5BFtrfhgKdjMRrsBpPjYU8xMW8rvp7WcBi7SndKwm+0wgl5JFKcoqah5cDELRCBess7WFA5RLnx+nog3Juh+jnZXsvcqPQTsLjvHGVzKmY9vl5rmwyBHRQ9lOYFadAqQzAYppAbkozT2bT2S4ln4An+SjJIqlUIGtit32cyiAq8gecjes9d31D+g8x2VKRlpIKCGrmLJXUNK4lgTGAlgvUYi3+3rQ7hYLxC4iYCn3Vx68NYJCFLw2zmtKUBSOQw9QefBz/AOQ3Lh+8Y+TNY69yWxucS5VQzwp7ugf2/cB1Tb/4F+NdENdRxrFkvHTa8WrggMtckP6aPMq7HUZKubP2nhmd2vhygzT/fFQUV4Lcx43uSyCmUZTY8T6tK2X5A2B22VhOKBfZyul7dv1dbA1wmn01YeOb+idgbU6PrHD79jjswNFs3/s8jGpOBxg92vI0uteV1Q1oionYW8jOQsMF56ZrYyeeSEutWDon7njPTlnclNFNRqUdQ3eFDgYLXwfxGRgyCHfdUI8Unk9zAAnoBl37hudcGbSeaQYxgVQPcF7amZa4maznTMErbxo8nFyzHINr34HGFW92Ytbu9MASdSEqupcMChzor6PmC10MOH65IgOVZF0I+8v+00O2HNIvxFEFLwMyhE28hzvCZhcx6/GZgzYNmndJs1Yr7pK6tYCzt6X5WxlriTLGlZ7K5dJ6hKO1Lswurvh7qXWzZ5VMvT0E44Ka5cY+56sZ34qpz6JsikBFCJrwA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199015)(46966006)(40470700004)(36840700001)(47076005)(83380400001)(426003)(82310400005)(16526019)(26005)(336012)(2616005)(186003)(6666004)(1076003)(40480700001)(7696005)(86362001)(40460700003)(36860700001)(36756003)(82740400003)(356005)(81166007)(41300700001)(4326008)(8676002)(2906002)(5660300002)(44832011)(8936002)(478600001)(70206006)(70586007)(316002)(54906003)(110136005)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:45:07.9336 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cef281ce-4341-4af6-418a-08daeecf3d43 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6965 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 6eac649499d3..482fcf71d1c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -260,19 +260,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) return -EINVAL; } - r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); - if (r) { - dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", - fw_name); - return r; - } - - r = amdgpu_ucode_validate(adev->uvd.fw); + r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name); if (r) { dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", fw_name); - release_firmware(adev->uvd.fw); - adev->uvd.fw = NULL; + amdgpu_ucode_release(&adev->uvd.fw); return r; } @@ -394,7 +386,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); } amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr); - release_firmware(adev->uvd.fw); + amdgpu_ucode_release(&adev->uvd.fw); return 0; } From patchwork Thu Jan 5 03:43:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37F6AC5479D for ; Thu, 5 Jan 2023 03:45:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A4AA10E695; Thu, 5 Jan 2023 03:45:21 +0000 (UTC) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2061.outbound.protection.outlook.com [40.107.237.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id D130810E691; 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The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 02cb3a12dd76..ea78b7513182 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -158,19 +158,11 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) return -EINVAL; } - r = request_firmware(&adev->vce.fw, fw_name, adev->dev); - if (r) { - dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n", - fw_name); - return r; - } - - r = amdgpu_ucode_validate(adev->vce.fw); + r = amdgpu_ucode_request(adev, &adev->vce.fw, fw_name); if (r) { dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n", fw_name); - release_firmware(adev->vce.fw); - adev->vce.fw = NULL; + amdgpu_ucode_release(&adev->vce.fw); return r; } @@ -226,7 +218,7 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev) for (i = 0; i < adev->vce.num_rings; i++) amdgpu_ring_fini(&adev->vce.ring[i]); - release_firmware(adev->vce.fw); + amdgpu_ucode_release(&adev->vce.fw); mutex_destroy(&adev->vce.idle_mutex); return 0; From patchwork Thu Jan 5 03:43:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC4AAC4708D for ; Thu, 5 Jan 2023 03:45:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D8E2E10E692; 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Wed, 4 Jan 2023 21:45:05 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 40/45] drm/amd: Use `amdgpu_ucode_*` helpers for CGS Date: Wed, 4 Jan 2023 21:43:14 -0600 Message-ID: <20230105034327.1439-41-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT077:EE_|BY5PR12MB4902:EE_ X-MS-Office365-Filtering-Correlation-Id: c705d78b-ff65-4111-376b-08daeecf3dde X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0rhSD5y+RGD8wGxLVvez8L3pg/WnAERaxVGsVsEMaBrUT6QmCkSfq8zTfz24mAM0UjTKfE51CdkjXwzv8K24bXSwHtUyKExaotXpIHza4RKNTsmEJiymUH4GxYi2JeFMYjiRVvyCBDT7Y3j5cKa0MTtGVBVeQaa39l1HRIcpGkDXkBA6mpo1nkd4W3UUFPYUL2AmxhTW3jaftQU/qL9jq60/abdM9t08I+yXBZgkpwPGKeXY6ml4vtKB7f3wJ0vtEnIuuzZk8TCPSIzpe6BgywzeqXtdaBeW0JxuMlfNXOJiXe/VJF5Te5v+2Gg5AnbR0u2/cWx9OMoc7DXWebRmQgJMpkQN8DqoWYqOv1ubkRI0LG9i3CdMkuTEeSiqwkt6hewRPhL9hhrbpnkTxFdNLrGJCFCpeGkz+uAqMF0e3XtACYqS8iVVpk+8xfQ0BnKoIcYXnRG/7kist4o/XkP8punojwwW7y+vt2pdx+qdZcq8XuZZnT52xPAT1EUOn2p+wfcYgjLQyGgKYspdsl5NZX6ARBeg+yB1nUDPxmK6Kgc8L7VfH24xAu3tu808aamuQoZVoyqAsecA29pOnkyF/I+Zfxd+tUlKYb/U/WN/Bj9J012ms0L4sNLXWcoJXViWJaW5+va3XYeZX5dskZERteNf0a0KL8yvg1Jo2MluAOFDsjyYcxxVRh6UBi6CVEZ1cXbnNL9q6Xhi4Krc+8un+b8HE5me8t440jaQrg/ZTZvTRMTJZTcHY/94noOhtTQRrb5mCzeJYVCpUlE0bijnOw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index f1a050379190..456e385333b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -411,17 +411,10 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, return -EINVAL; } - err = request_firmware(&adev->pm.fw, fw_name, adev->dev); - if (err) { - DRM_ERROR("Failed to request firmware\n"); - return err; - } - - err = amdgpu_ucode_validate(adev->pm.fw); + err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); if (err) { DRM_ERROR("Failed to load firmware \"%s\"", fw_name); - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; + amdgpu_ucode_release(&adev->pm.fw); return err; } From patchwork Thu Jan 5 03:43:15 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:45:10.2616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: baf059bb-4bd8-4d68-7921-08daeecf3ea6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6370 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cdb681398a99..406d53ac3096 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1983,17 +1983,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); - err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name); if (err) { dev_err(adev->dev, - "Failed to load gpu_info firmware \"%s\"\n", - fw_name); - goto out; - } - err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); - if (err) { - dev_err(adev->dev, - "Failed to validate gpu_info firmware \"%s\"\n", + "Failed to get gpu_info firmware \"%s\"\n", fw_name); goto out; } @@ -4030,8 +4023,7 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) amdgpu_fence_driver_sw_fini(adev); amdgpu_device_ip_fini(adev); - release_firmware(adev->firmware.gpu_info_fw); - adev->firmware.gpu_info_fw = NULL; + amdgpu_ucode_release(&adev->firmware.gpu_info_fw); adev->accel_working = false; dma_fence_put(rcu_dereference_protected(adev->gang_submit, true)); From patchwork Thu Jan 5 03:43:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 467D3C46467 for ; Thu, 5 Jan 2023 03:45:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0B3010E696; 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Wed, 4 Jan 2023 21:45:08 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 42/45] drm/amd: Use `amdgpu_ucode_*` helpers for DMCU Date: Wed, 4 Jan 2023 21:43:16 -0600 Message-ID: <20230105034327.1439-43-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT077:EE_|PH7PR12MB6737:EE_ X-MS-Office365-Filtering-Correlation-Id: 955faf5e-cc41-47d6-85d5-08daeecf3f16 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ba60JHFTS6U+KI67XSL6HXKLX6M7A+GO2uWh4cFuqwsvu1Oiq4dNyVFqGSL1NBJmCQBLHK5kZ/vkVyMbtSbHi1C34cDEAfcqz55OufihUWhiN47HkYW9SU/KODxP9TGuwkVs7WGE4iaJXyohauX/f4g5kdmkmmq6bDpnt2un+v5CqagfT8MaqIAqZ1MMovFZgyje4vkMhbRgiV64tOiq9dAP4wOPI8QAUPqVKQqM/cMyL1N4mipxgIqAec3+5/qDb4qrYTV/ytVtJ+4PjI9e1L9JrbBhh6uNIzb29CqvvRXOsK2oP9jZ3HmJOzbQqewhTt+JFT//rjN6MWDgz3+w7UuD8H0s5tOUEjoaVSD5mkZBogoLZyECeFJQk3Jq9CkqrPI+dMBafIzj7fEa1tFFdpd5dWOS+ARmv9C5RGcw18mBxL91py7RV4sYu/dpLQxxNGItn/kOPtTPWTNNobJ5Ffjcus0nQIs7T4DcAxwp7IU4ORersAkOf9ujQNaKfXi1ylr/NKi275Bh3N3smdz5tZFW3/VR9ZHWFjZqXkGgQR+LIagiF0Inf7rj+RGHt30kBC3o5bBSOuYaxuHBlUGOWrNH63Mme2CcCVL8rjQxBJK8RG7A7xIfFFTx/4GMlemJMhsaauEF1IKbHYpDFLeggIiS1sxUhF5/jZmQc9vT2h02O+lN9TWoYL1UHWihFKBpKE3/1Anr4C1aasKgNBrHOeIY2/+sJJDvcW71gQ9RV9f5Q8agdW9KSe70ueEF+4XSwvNtf6Vh+8zc4W4bId4wGA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(396003)(346002)(376002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(41300700001)(426003)(40460700003)(47076005)(70206006)(316002)(54906003)(44832011)(336012)(8676002)(4326008)(2616005)(70586007)(36756003)(82740400003)(36860700001)(81166007)(82310400005)(86362001)(356005)(8936002)(40480700001)(83380400001)(110136005)(5660300002)(1076003)(2906002)(478600001)(6666004)(186003)(16526019)(7696005)(26005)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:45:10.9959 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 955faf5e-cc41-47d6-85d5-08daeecf3f16 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6737 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Leo Li , Lazar Lijo , Rodrigo Siqueira , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 61c192ead62f..79c4652e8e40 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1881,20 +1881,13 @@ static int load_dmcu_fw(struct amdgpu_device *adev) return 0; } - r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); - if (r == -ENOENT) { + r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); + if (r == -ENODEV) { /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); adev->dm.fw_dmcu = NULL; return 0; } - if (r) { - dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", - fw_name_dmcu); - return r; - } - - r = amdgpu_ucode_validate(adev->dm.fw_dmcu); if (r) { dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", fw_name_dmcu); From patchwork Thu Jan 5 03:43:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90285C4708D for ; Thu, 5 Jan 2023 03:45:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02A1B88130; Thu, 5 Jan 2023 03:45:27 +0000 (UTC) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by gabe.freedesktop.org (Postfix) with ESMTPS id F100410E68C; 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Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 8f2cc6310340..11b7b4cffaae 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -111,8 +111,7 @@ static int pp_sw_fini(void *handle) hwmgr_sw_fini(hwmgr); - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; + amdgpu_ucode_release(&adev->pm.fw); return 0; } From patchwork Thu Jan 5 03:43:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56B30C54EBD for ; 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Wed, 4 Jan 2023 21:45:11 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 44/45] drm/amd: Use `amdgpu_ucode_release` helper for si Date: Wed, 4 Jan 2023 21:43:18 -0600 Message-ID: <20230105034327.1439-45-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT024:EE_|DM4PR12MB5294:EE_ X-MS-Office365-Filtering-Correlation-Id: 6dd64e58-6517-47c3-3cb7-08daeecf4098 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3SzHiWBWcLwNda0WfxZcrWT5ZYYMWMq1o8+czXzHH8m2JW2giwabodly+aKS9SgDuR1FbyipQ2UhvpzUS+ZD7tTDlfs5yUj5q/+2Vnbxur1ZiOq3t09V2HwXwqvyiY+mc2+LMKpRg4gzgalVQRoGyhdEnEO3shxord5f4O9In/qrjYhya61MOTK4YdZdOb+oIzcmkLS0Srm5BX2asjv49e3i0B6Vu0lXFJGOLVFe1wZXtupXbueHK9AjEkTgWrKuydWiPvhhyIooOM+1teRG9E4tAwcN5gNGJRfEFNHpFOJeJvkfQaL32EJ7Ta6lbAzuM+S2ECEYunIIPUUpDY4E+Lp7yc/xXb4hjaQRhIveyrIZWJ9srxVyC7eHJ6cTt0b53pdHjOllR6Qt1jbsa7qcaifJQ/OfDPInQWJUgCEYy2zPljX0CV622xt4WB2j4qBY5AVWD9nZ7ov42pT6RHhgvMMhvovacHgtWeLaKfLS/P8jj2nDrlyYmQbksGsP8KhipZH7vPN57TWuKg41j8N5mhjMGkgTQG6Op2hR+RheznziBM3ED98ywdWqS6dDf1j+lOWhDvxmuT7BAJCs8Bauf1ezgDZ2pTE2M9KWfZhtCPpI6KnAJEYgPAIzTKFd9YR/gUTvcMBUqxyte1zeyKFoi3088nYzdIyYTQxU6jefSr3jssYFd5uPFF0qNVIxw/2eq5Aie6P8qAdS1iC1zkbXQKZdX8IppqqcQaBiKNn1eR6+1HcsBEo/M8ymdQI5HiPnhXthqrEJ85UESKbJo7QeaQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 49c398ec0aaf..d6d9e3b1b2c0 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7714,20 +7714,13 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); - err = request_firmware(&adev->pm.fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->pm.fw); - -out: + err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name); if (err) { DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n", err, fw_name); - release_firmware(adev->pm.fw); - adev->pm.fw = NULL; + amdgpu_ucode_release(&adev->pm.fw); } return err; - } static int si_dpm_sw_init(void *handle) From patchwork Thu Jan 5 03:43:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8479DC4708D for ; Thu, 5 Jan 2023 03:45:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C85F10E69D; Thu, 5 Jan 2023 03:45:22 +0000 (UTC) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2073.outbound.protection.outlook.com [40.107.244.73]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8864C10E684; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:45:15.4587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64fcb8f8-4fde-4fd4-7fba-08daeecf41bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7895 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" No consumers outside of amdgpu_ucode.c use amdgpu_ucode_validate anymore, so make the function static. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 8ebfec12da87..47549d659d9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -504,7 +504,7 @@ void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) } } -int amdgpu_ucode_validate(const struct firmware *fw) +static int amdgpu_ucode_validate(const struct firmware *fw) { const struct common_firmware_header *hdr = (const struct common_firmware_header *)fw->data; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 848579d4988b..bee93ab4298f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -543,7 +543,6 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); -int amdgpu_ucode_validate(const struct firmware *fw); int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, const char *fw_name); void amdgpu_ucode_release(const struct firmware **fw);