From patchwork Fri Jan 6 09:21:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 762B8C678DC for ; Fri, 6 Jan 2023 09:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234383AbjAFJ0g (ORCPT ); Fri, 6 Jan 2023 04:26:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234646AbjAFJZe (ORCPT ); Fri, 6 Jan 2023 04:25:34 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 482286C7D3; Fri, 6 Jan 2023 01:22:02 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3064rUCU028596; Fri, 6 Jan 2023 09:21:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=V/bptrVcXVHFSDujslPeTwO4nzZz362HA58mkxTRXeE=; b=VAGQDRZbiM+7bVGWwOUGn/hCAeS+5wF232moBBAmEb2u7or1XRQJnqHdRHQ1m8skCN+w yL3bRSY189qJOAOnhydRYbZ+0jmplYuDdiHaw/QspnyFP3XDjqMpJlcAki39UXTREU9X KrloMGVb7Wlz53FFq1s5VHZvvm2dtl/h4ZN1RacgoT6IiiViCY5JNCnl1r6I5ScPNtFc Bd50pLuYYjrOpFulESx6oObtuju8FSPx9rSddb7wY/NTzBRihNBhocxlNv1vqi0LQYTM bZT/ykaMV5z2nGmcfIOupJycCoHksYpfuKUCPwXCVkwg6zYPznKrrZupYEUU3qi78oE4 Vg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mwxhkabx4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Jan 2023 09:21:36 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3069LaAF021122 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Jan 2023 09:21:36 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 6 Jan 2023 01:21:35 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v16 1/8] coresight: core: Use IDR for non-cpu bound sources' paths. Date: Fri, 6 Jan 2023 01:21:12 -0800 Message-ID: <20230106092119.20449-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wAp4xeBwD2nhcJrGWL_JVCisD0sBsq7W X-Proofpoint-ORIG-GUID: wAp4xeBwD2nhcJrGWL_JVCisD0sBsq7W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=926 impostorscore=0 mlxscore=0 bulkscore=0 clxscore=1015 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Except stm, there could be other sources which are not associated with cpus. Use IDR to store and search these sources' paths. Reviewed-by: Suzuki K Poulose Reviewed-by: Mike Leach Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++++++------ 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ce3aa845ecc2..5eb013f49a0d 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,13 @@ static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); +/* + * Use IDR to map the hash of the source's device name + * to the pointer of path for the source. The idr is for + * the sources which aren't associated with CPU. + */ +static DEFINE_IDR(path_idr); + /** * struct coresight_node - elements of a path, from source to sink * @csdev: Address of an element. @@ -42,14 +50,6 @@ struct coresight_node { */ static DEFINE_PER_CPU(struct list_head *, tracer_path); -/* - * As of this writing only a single STM can be found in CS topologies. Since - * there is no way to know if we'll ever see more and what kind of - * configuration they will enact, for the time being only define a single path - * for STM. - */ -static struct list_head *stm_path; - /* * When losing synchronisation a new barrier packet needs to be inserted at the * beginning of the data collected in a buffer. That way the decoder knows that @@ -1075,6 +1075,7 @@ int coresight_enable(struct coresight_device *csdev) struct coresight_device *sink; struct list_head *path; enum coresight_dev_subtype_source subtype; + u32 hash; subtype = csdev->subtype.source_subtype; @@ -1129,7 +1130,14 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - stm_path = path; + /* + * Use the hash of source's device name as ID + * and map the ID to the pointer of the path. + */ + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL); + if (ret) + goto err_source; break; default: /* We can't be here */ @@ -1153,6 +1161,7 @@ void coresight_disable(struct coresight_device *csdev) { int cpu, ret; struct list_head *path = NULL; + u32 hash; mutex_lock(&coresight_mutex); @@ -1170,14 +1179,20 @@ void coresight_disable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - path = stm_path; - stm_path = NULL; + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + /* Find the path by the hash. */ + path = idr_find(&path_idr, hash); + if (path == NULL) { + pr_err("Path is not found for %s\n", dev_name(&csdev->dev)); + goto out; + } break; default: /* We can't be here */ break; } + idr_remove(&path_idr, hash); coresight_disable_path(path); coresight_release_path(path); From patchwork Fri Jan 6 09:21:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A48B1C54EBD for ; Fri, 6 Jan 2023 09:26:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232958AbjAFJ02 (ORCPT ); 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Fri, 06 Jan 2023 09:21:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3069LaHg022757 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Jan 2023 09:21:36 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 6 Jan 2023 01:21:35 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v16 2/8] Coresight: Add coresight TPDM source driver Date: Fri, 6 Jan 2023 01:21:13 -0800 Message-ID: <20230106092119.20449-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2OG7TLWwQoLpFo282wA5VS5Yxd49WJk6 X-Proofpoint-ORIG-GUID: 2OG7TLWwQoLpFo282wA5VS5Yxd49WJk6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 spamscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add driver to support Coresight device TPDM (Trace, Profiling and Diagnostics Monitor). TPDM is a monitor to collect data from different datasets. This change is to add probe/enable/disable functions for tpdm source. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/Kconfig | 12 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 149 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 26 ++++ include/linux/coresight.h | 1 + 6 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 45c1eb5dfcb7..82811db1a5cf 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,16 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. + +config CORESIGHT_TPDM + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver" + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for configuring monitor. Monitors are + primarily responsible for data set collection and support the + ability to collect any permutation of data set types. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpdm. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 329a0c704b87..6bb9b1746bc7 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 5eb013f49a0d..a798008ac56e 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1061,7 +1061,8 @@ static int coresight_validate_source(struct coresight_device *csdev, } if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && - subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) { + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; } @@ -1130,6 +1131,7 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: /* * Use the hash of source's device name as ID * and map the ID to the pointer of the path. @@ -1179,6 +1181,7 @@ void coresight_disable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); /* Find the path by the hash. */ path = idr_find(&path_idr, hash); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c new file mode 100644 index 000000000000..95dbf4badfd2 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpdm.h" + +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); + +/* TPDM enable operations */ +static int tpdm_enable(struct coresight_device *csdev, + struct perf_event *event, u32 mode) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) { + spin_unlock(&drvdata->spinlock); + return -EBUSY; + } + + drvdata->enable = true; + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); + return 0; +} + +/* TPDM disable operations */ +static void tpdm_disable(struct coresight_device *csdev, + struct perf_event *event) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (!drvdata->enable) { + spin_unlock(&drvdata->spinlock); + return; + } + + drvdata->enable = false; + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); +} + +static const struct coresight_ops_source tpdm_source_ops = { + .enable = tpdm_enable, + .disable = tpdm_disable, +}; + +static const struct coresight_ops tpdm_cs_ops = { + .source_ops = &tpdm_source_ops, +}; + +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) +{ + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct tpdm_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + /* driver data*/ + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + /* Set up coresight component description */ + desc.name = coresight_alloc_device_name(&tpdm_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type = CORESIGHT_DEV_TYPE_SOURCE; + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.ops = &tpdm_cs_ops; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + desc.access = CSDEV_ACCESS_IOMEM(base); + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + spin_lock_init(&drvdata->spinlock); + /* Decrease pm refcount when probe is done.*/ + pm_runtime_put(&adev->dev); + + return 0; +} + +static void __exit tpdm_remove(struct amba_device *adev) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); +} + +/* + * Different TPDM has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpdm_ids[] = { + { + .id = 0x000f0e00, + .mask = 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpdm_driver = { + .drv = { + .name = "coresight-tpdm", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = tpdm_probe, + .id_table = tpdm_ids, + .remove = tpdm_remove, +}; + +module_amba_driver(tpdm_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h new file mode 100644 index 000000000000..2ec8a6810771 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDM_H +#define _CORESIGHT_CORESIGHT_TPDM_H + +/** + * struct tpdm_drvdata - specifics associated to an TPDM component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @spinlock: lock for the drvdata value. + * @enable: enable status of the component. + */ + +struct tpdm_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + bool enable; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index e241eb88dfb9..f19a47b9bb5a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, }; enum coresight_dev_subtype_helper { From patchwork Fri Jan 6 09:21:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EF0DC6379F for ; Fri, 6 Jan 2023 09:26:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233592AbjAFJ0b (ORCPT ); Fri, 6 Jan 2023 04:26:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234394AbjAFJZ2 (ORCPT ); Fri, 6 Jan 2023 04:25:28 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD29C718BC; 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Fri, 06 Jan 2023 09:21:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3069LaOK014861 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Jan 2023 09:21:36 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 6 Jan 2023 01:21:36 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson , Rob Herring Subject: [PATCH v16 3/8] dt-bindings: arm: Adds CoreSight TPDM hardware Date: Fri, 6 Jan 2023 01:21:14 -0800 Message-ID: <20230106092119.20449-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _v94ThAcq4oHKBdcSWhdA0lcUbHal8Os X-Proofpoint-ORIG-GUID: _v94ThAcq4oHKBdcSWhdA0lcUbHal8Os X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 mlxscore=0 bulkscore=0 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds new coresight-tpdm.yaml file describing the bindings required to define tpdm in the device trees. Acked-by: Suzuki K Poulose Reviewed-by: Mike Leach Reviewed-by: Rob Herring Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml new file mode 100644 index 000000000000..5c08342664ea --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Monitor - TPDM + +description: | + The TPDM or Monitor serves as data collection component for various dataset + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef), + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete + Single Bit (DSB). It performs data collection in the data producing clock + domain and transfers it to the data collection time domain, generally ATB + clock domain. + + The primary use case of the TPDM is to collect data from different data + sources and send it to a TPDA for packetization, timestamping, and funneling. + +maintainers: + - Mao Jinlong + - Tao Zhang + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tpdm + required: + - compatible + +properties: + $nodename: + pattern: "^tpdm(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpdm + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + out-ports: + description: | + Output connections from the TPDM to coresight funnel/TPDA. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Output connection from the TPDM to coresight + funnel/TPDA. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum TPDM definition. TPDM connect to coresight TPDA. + - | + tpdm@684c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0684c000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_prng>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..92e7805bf2e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2124,6 +2124,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml +F: Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/trace/coresight/* From patchwork Fri Jan 6 09:21:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D948C5479D for ; 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Fri, 6 Jan 2023 01:21:36 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v16 4/8] coresight-tpdm: Add DSB dataset support Date: Fri, 6 Jan 2023 01:21:15 -0800 Message-ID: <20230106092119.20449-5-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1c6kI7csJs6jVJfZJIyteSExy4GOoB9s X-Proofpoint-ORIG-GUID: 1c6kI7csJs6jVJfZJIyteSExy4GOoB9s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 spamscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org TPDM serves as data collection component for various dataset types. DSB(Discrete Single Bit) is one of the dataset types. DSB subunit can be enabled for data collection by writing 1 to the first bit of DSB_CR register. This change is to add enable/disable function for DSB dataset by writing DSB_CR register. Reviewed-by: Suzuki K Poulose Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 56 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++++++ 2 files changed, 78 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 95dbf4badfd2..4a37ae6054b4 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,7 +20,28 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val |= TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /* TPDM enable operations */ +static void __tpdm_enable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + tpdm_enable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev, return -EBUSY; } + __tpdm_enable(drvdata); drvdata->enable = true; spin_unlock(&drvdata->spinlock); @@ -39,7 +61,28 @@ static int tpdm_enable(struct coresight_device *csdev, return 0; } +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 0 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val &= ~TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /* TPDM disable operations */ +static void __tpdm_disable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + tpdm_disable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static void tpdm_disable(struct coresight_device *csdev, struct perf_event *event) { @@ -51,6 +94,7 @@ static void tpdm_disable(struct coresight_device *csdev, return; } + __tpdm_disable(drvdata); drvdata->enable = false; spin_unlock(&drvdata->spinlock); @@ -66,6 +110,17 @@ static const struct coresight_ops tpdm_cs_ops = { .source_ops = &tpdm_source_ops, }; +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +{ + u32 pidr; + + CS_UNLOCK(drvdata->base); + /* Get the datasets present on the TPDM. */ + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); + drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); + CS_LOCK(drvdata->base); +} + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -107,6 +162,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev); spin_lock_init(&drvdata->spinlock); + tpdm_init_default_data(drvdata); /* Decrease pm refcount when probe is done.*/ pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 2ec8a6810771..3f7ee37b6303 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -6,6 +6,26 @@ #ifndef _CORESIGHT_CORESIGHT_TPDM_H #define _CORESIGHT_CORESIGHT_TPDM_H +/* The max number of the datasets that TPDM supports */ +#define TPDM_DATASETS 7 + +/* DSB Subunit Registers */ +#define TPDM_DSB_CR (0x780) +/* Enable bit for DSB subunit */ +#define TPDM_DSB_CR_ENA BIT(0) + +/** + * The bits of PERIPHIDR0 register. + * The fields [6:0] of PERIPHIDR0 are used to determine what + * interfaces and subunits are present on a given TPDM. + * + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 + */ + +#define TPDM_PIDR0_DS_IMPDEF BIT(0) +#define TPDM_PIDR0_DS_DSB BIT(1) + /** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. @@ -13,6 +33,7 @@ * @csdev: component vitals needed by the framework. * @spinlock: lock for the drvdata value. * @enable: enable status of the component. + * @datasets: The datasets types present of the TPDM. */ struct tpdm_drvdata { @@ -21,6 +42,7 @@ struct tpdm_drvdata { struct coresight_device *csdev; spinlock_t spinlock; bool enable; + unsigned long datasets; }; #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ From patchwork Fri Jan 6 09:21:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66704C678D9 for ; Fri, 6 Jan 2023 09:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234352AbjAFJ0g (ORCPT ); Fri, 6 Jan 2023 04:26:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232218AbjAFJZ5 (ORCPT ); Fri, 6 Jan 2023 04:25:57 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 817126DB9D; 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Fri, 06 Jan 2023 09:21:38 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3069LbqJ029771 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Jan 2023 09:21:37 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 6 Jan 2023 01:21:36 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v16 5/8] coresight-tpdm: Add integration test support Date: Fri, 6 Jan 2023 01:21:16 -0800 Message-ID: <20230106092119.20449-6-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BSZg-BrQ217LxpnFJpdcsIwmegmuqxoW X-Proofpoint-ORIG-GUID: BSZg-BrQ217LxpnFJpdcsIwmegmuqxoW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Integration test for tpdm can help to generate the data for verification of the topology during TPDM software bring up. Sample: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test cat /dev/tmc_etf0 > /data/etf-tpdm0.bin Reviewed-by: Suzuki K Poulose Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 13 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 54 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++ 3 files changed, 81 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm new file mode 100644 index 000000000000..4a58e649550d --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -0,0 +1,13 @@ +What: /sys/bus/coresight/devices//integration_test +Date: January 2023 +KernelVersion 6.2 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Run integration test for tpdm. Integration test + will generate test data for tpdm. It can help to make + sure that the trace path is enabled and the link configurations + are fine. + + Accepts only one of the 2 values - 1 or 2. + 1 : Generate 64 bits data + 2 : Generate 32 bits data diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 4a37ae6054b4..d85ca967e59f 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -121,6 +121,59 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) CS_LOCK(drvdata->base); } +/* + * value 1: 64 bits test data + * value 2: 32 bits test data + */ +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val != 1 && val != 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val == 1) + val = ATBCNTRL_VAL_64; + else + val = ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i = 0; i < INTEGRATION_TEST_CYCLE; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); + +static struct attribute *tpdm_attrs[] = { + &dev_attr_integration_test.attr, + NULL, +}; + +static struct attribute_group tpdm_attr_grp = { + .attrs = tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] = { + &tpdm_attr_grp, + NULL, +}; + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -157,6 +210,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; desc.access = CSDEV_ACCESS_IOMEM(base); + desc.groups = tpdm_attr_grps; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 3f7ee37b6303..543854043a2d 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -14,6 +14,20 @@ /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + +/* + * Number of cycles to write value when + * integration test. + */ +#define INTEGRATION_TEST_CYCLE 10 + /** * The bits of PERIPHIDR0 register. * The fields [6:0] of PERIPHIDR0 are used to determine what From patchwork Fri Jan 6 09:21:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 141CEC678D7 for ; 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Fri, 6 Jan 2023 01:21:37 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v16 6/8] Coresight: Add TPDA link driver Date: Fri, 6 Jan 2023 01:21:17 -0800 Message-ID: <20230106092119.20449-7-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wZHJYoiwJkO2KRYqzrz8XIoqdYDq6vtc X-Proofpoint-GUID: wZHJYoiwJkO2KRYqzrz8XIoqdYDq6vtc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org TPDA(Trace, Profiling and Diagnostics Aggregator) is to provide packetization, funneling and timestamping of TPDM data. Multiple monitors are connected to different input ports of TPDA.This change is to add tpda enable/disable/probe functions for coresight tpda driver. - - - - - - - - - - - - | TPDM 0| | TPDM 1 | | TPDM 2| - - - - - - - - - - - - | | | |_ _ _ _ _ _ | _ _ _ _ | | | | | | | ------------------ | TPDA | ------------------ Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 211 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 +++ 4 files changed, 258 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 82811db1a5cf..f580f1a94f96 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -205,6 +205,7 @@ config CORESIGHT_TRBE config CORESIGHT_TPDM tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver" select CORESIGHT_LINKS_AND_SINKS + select CORESIGHT_TPDA help This driver provides support for configuring monitor. Monitors are primarily responsible for data set collection and support the @@ -213,4 +214,14 @@ config CORESIGHT_TPDM To compile this driver as a module, choose M here: the module will be called coresight-tpdm. +config CORESIGHT_TPDA + tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver" + help + This driver provides support for configuring aggregator. This is + primarily useful for pulling the data sets from one or more + attached monitors and pushing the resultant data out. Multiple + monitors are connected on different input ports of TPDA. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpda. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 6bb9b1746bc7..1712d82e7260 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o +obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c new file mode 100644 index 000000000000..59897980bbb8 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpda.h" +#include "coresight-trace-id.h" + +DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); + +/* Settings pre enabling port control register */ +static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_CR); + val &= ~TPDA_CR_ATID; + val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + writel_relaxed(val, drvdata->base + TPDA_CR); +} + +static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* Enable the port */ + val |= TPDA_Pn_CR_ENA; + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +} + +static void __tpda_enable(struct tpda_drvdata *drvdata, int port) +{ + CS_UNLOCK(drvdata->base); + + if (!drvdata->csdev->enable) + tpda_enable_pre_port(drvdata); + + tpda_enable_port(drvdata, port); + + CS_LOCK(drvdata->base); +} + +static int tpda_enable(struct coresight_device *csdev, int inport, int outport) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (atomic_read(&csdev->refcnt[inport]) == 0) + __tpda_enable(drvdata, inport); + + atomic_inc(&csdev->refcnt[inport]); + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", inport); + return 0; +} + +static void __tpda_disable(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + val &= ~TPDA_Pn_CR_ENA; + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); + + CS_LOCK(drvdata->base); +} + +static void tpda_disable(struct coresight_device *csdev, int inport, + int outport) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (atomic_dec_return(&csdev->refcnt[inport]) == 0) + __tpda_disable(drvdata, inport); + + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", inport); +} + +static const struct coresight_ops_link tpda_link_ops = { + .enable = tpda_enable, + .disable = tpda_disable, +}; + +static const struct coresight_ops tpda_cs_ops = { + .link_ops = &tpda_link_ops, +}; + +static int tpda_init_default_data(struct tpda_drvdata *drvdata) +{ + int atid; + /* + * TPDA must has a unique atid. This atid can uniquely + * identify the TPDM trace source connected to the TPDA. + * The TPDMs which are connected to same TPDA share the + * same trace-id. When TPDA does packetization, different + * port will have unique channel number for decoding. + */ + atid = coresight_trace_id_get_system_id(); + if (atid < 0) + return atid; + + drvdata->atid = atid; + return 0; +} + +static int tpda_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct tpda_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + void __iomem *base; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + base = devm_ioremap_resource(dev, &adev->res); + if (!base) + return -ENOMEM; + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + ret = tpda_init_default_data(drvdata); + if (ret) + return ret; + + desc.name = coresight_alloc_device_name(&tpda_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type = CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops = &tpda_cs_ops; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + desc.access = CSDEV_ACCESS_IOMEM(base); + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + pm_runtime_put(&adev->dev); + + dev_dbg(drvdata->dev, "TPDA initialized\n"); + return 0; +} + +static void __exit tpda_remove(struct amba_device *adev) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_trace_id_put_system_id(drvdata->atid); + coresight_unregister(drvdata->csdev); +} + +/* + * Different TPDA has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpda_ids[] = { + { + .id = 0x000f0f00, + .mask = 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpda_driver = { + .drv = { + .name = "coresight-tpda", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = tpda_probe, + .remove = tpda_remove, + .id_table = tpda_ids, +}; + +module_amba_driver(tpda_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h new file mode 100644 index 000000000000..0399678df312 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDA_H +#define _CORESIGHT_CORESIGHT_TPDA_H + +#define TPDA_CR (0x000) +#define TPDA_Pn_CR(n) (0x004 + (n * 4)) +/* Aggregator port enable bit */ +#define TPDA_Pn_CR_ENA BIT(0) + +#define TPDA_MAX_INPORTS 32 + +/* Bits 6 ~ 12 is for atid value */ +#define TPDA_CR_ATID GENMASK(12, 6) + +/** + * struct tpda_drvdata - specifics associated to an TPDA component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @spinlock: lock for the drvdata value. + * @enable: enable status of the component. + */ +struct tpda_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + u8 atid; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDA_H */ From patchwork Fri Jan 6 09:21:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13091194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B13ABC677F0 for ; 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Fri, 6 Jan 2023 01:21:37 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson , Rob Herring Subject: [PATCH v16 7/8] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Date: Fri, 6 Jan 2023 01:21:18 -0800 Message-ID: <20230106092119.20449-8-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3c-OsY1NHAUsve4f-_RK4-aN7BEv9ctR X-Proofpoint-GUID: 3c-OsY1NHAUsve4f-_RK4-aN7BEv9ctR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds new coresight-tpda.yaml file describing the bindings required to define tpda in the device trees. Acked-by: Suzuki K Poulose Reviewed-by: Rob Herring Reviewed-by: Mike Leach Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/qcom,coresight-tpda.yaml | 129 ++++++++++++++++++ MAINTAINERS | 2 +- 2 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml new file mode 100644 index 000000000000..2ec9b5b24d73 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Aggregator - TPDA + +description: | + TPDAs are responsible for packetization and timestamping of data sets + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or + more attached TPDM and pushing the resultant (packetized) data out a + master ATB interface. Performing an arbitrated ATB interleaving (funneling) + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). + + There is no strict binding between TPDM and TPDA. TPDA can have multiple + TPDMs connect to it. But There must be only one TPDA in the path from the + TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or + connect to funnel which will connect to TPDA's inport. + + We can use the commands are similar to the below to validate TPDMs. + Enable coresight sink first. + + echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink + echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source + echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test + echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test + + The test data will be collected in the coresight sink which is enabled. + If rwp register of the sink is keeping updating when do integration_test + (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM + to sink. + +maintainers: + - Mao Jinlong + - Tao Zhang + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tpda + required: + - compatible + +properties: + $nodename: + pattern: "^tpda(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpda + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + type: object + description: | + Input connections from TPDM to TPDA + $ref: /schemas/graph.yaml#/properties/ports + + out-ports: + type: object + description: | + Output connections from the TPDA to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: + Output connection from the TPDA to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + # minimum tpda definition. + - | + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x6004000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 92e7805bf2e3..d7d22becc647 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2124,7 +2124,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml -F: Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/trace/coresight/* From patchwork Fri Jan 6 09:21:19 2023 Content-Type: text/plain; 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Fri, 6 Jan 2023 09:21:38 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 6 Jan 2023 01:21:38 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v16 8/8] arm64: dts: qcom: sm8250: Add tpdm mm/prng Date: Fri, 6 Jan 2023 01:21:19 -0800 Message-ID: <20230106092119.20449-9-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106092119.20449-1-quic_jinlmao@quicinc.com> References: <20230106092119.20449-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SQr5ULAies88irEmmtjHRosA0QTxoeBg X-Proofpoint-ORIG-GUID: SQr5ULAies88irEmmtjHRosA0QTxoeBg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-06_05,2023-01-05_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 mlxlogscore=934 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301060073 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Signed-off-by: Mao Jinlong Acked-by: Suzuki K Poulose --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 164 +++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..221fcbdb47a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2746,6 +2746,73 @@ stm_out: endpoint { }; }; + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0 0x06004000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@9 { + reg = <9>; + tpda_9_in_tpdm_mm: endpoint { + remote-endpoint = <&tpdm_mm_out_tpda9>; + }; + }; + + port@17 { + reg = <23>; + tpda_23_in_tpdm_prng: endpoint { + remote-endpoint = <&tpdm_prng_out_tpda_23>; + }; + }; + }; + }; + + funnel@6005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06005000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint = <&tpda_out_funnel_qatb>; + }; + }; + }; + }; + funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; @@ -2765,6 +2832,13 @@ in-ports { #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint = <&funnel_qatb_out_funnel_in0>; + }; + }; + port@7 { reg = <7>; funnel0_in7: endpoint { @@ -2882,6 +2956,22 @@ etr_in: endpoint { }; }; + tpdm@684c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0 0x0684c000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_23: endpoint { + remote-endpoint = <&tpda_23_in_tpdm_prng>; + }; + }; + }; + }; + funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; arm,primecell-periphid = <0x000bb908>; @@ -2966,6 +3056,80 @@ replicator_in: endpoint { }; }; + tpdm@6c08000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0 0x06c08000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_mm_out_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; + }; + }; + }; + }; + + funnel@6c0b000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06c0b000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_dl_mm_out_funnel_dl_center: endpoint { + remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + funnel_dl_mm_in_tpdm_mm: endpoint { + remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; + }; + }; + }; + }; + + funnel@6c2d000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06c2d000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port { + tpdm_mm_out_tpda9: endpoint { + remote-endpoint = <&tpda_9_in_tpdm_mm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_dl_center_in_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; + }; + }; + }; + }; + etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>;