From patchwork Mon Jan 9 14:38:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B67DFC54EBD for ; Mon, 9 Jan 2023 14:44:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A14110E1FB; Mon, 9 Jan 2023 14:44:08 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7198710E0A7 for ; Mon, 9 Jan 2023 14:44:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=9648VuOhk39mU4vg9P8mrkFGTnpgxLJ7uh8m6YPwrNA=; b=NMPPemoP+IGrVEVN7n9QvaBAEc xnsdpArCjxljyG+xkK+NSzx9kcYcpp3MM+SCH1sHSIbB5AgNnYpzlcp91xRyIRwPemLFkOPT2j1Ij esfPb4u2z3zDGc4+6PQRvGeQHd4z0HwXF3ihgULOT6P/Ycs8AnNWWEFdR0vIZi+QG6w+ajnffhBdD x/gbiBJ+/HYn/QiFKmRWbk3toGrzTI1WMs+rJZvZvKyVgM2qP+HYIJWlugxU1TyEadmjGrL0rIg35 RjzFh06bbyRZBk5lBk4cayR6G6m1BO/nbjWUxExXKNvOQoxgxi+kvUGXmijc+b5GM+oyAxVwwvZxA W9d3LIMw==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNL-003TyM-DW; Mon, 09 Jan 2023 15:43:47 +0100 From: Melissa Wen To: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 01/18] drm: Add 3D LUT mode and its attributes Date: Mon, 9 Jan 2023 13:38:29 -0100 Message-Id: <20230109143846.1966301-2-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, Shashank Sharma , alex.hung@amd.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, seanpaul@chromium.org, kernel-dev@igalia.com, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Alex Hung A struct is defined for 3D LUT modes to be supported by hardware. The elements includes lut_size, lut_stride, bit_depth, color_format and flags. Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- include/uapi/drm/drm_mode.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index fa953309d9ce..fddb86dad4db 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -849,6 +849,23 @@ struct drm_color_lut { __u16 reserved; }; +/* + * struct drm_mode_lut3d_mode - 3D LUT mode information. + * @lut_size: number of valid points on every dimension of 3D LUT. + * @lut_stride: number of points on every dimension of 3D LUT. + * @bit_depth: number of bits of RGB. If color_mode defines entries with higher + * bit_depth the least significant bits will be truncated. + * @color_format: fourcc values, ex. DRM_FORMAT_XRGB16161616 or DRM_FORMAT_XBGR16161616. + * @flags: flags for hardware-sepcific features + */ +struct drm_mode_lut3d_mode { + __u16 lut_size; + __u16 lut_stride[3]; + __u16 bit_depth; + __u32 color_format; + __u32 flags; +}; + /** * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data. * From patchwork Mon Jan 9 14:38:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDCD7C54EBE for ; Mon, 9 Jan 2023 14:44:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9309810E20D; Mon, 9 Jan 2023 14:44:13 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7709C10E20D for ; Mon, 9 Jan 2023 14:44:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=7CfsYtEI18MX2i5Kgmt0jdgzbdIqqCHC3Q3agzts8+c=; b=UL3SEY9MNm/HRAKaMOiG/xmouZ nJE2ZeA7LGNDnge+AfX5rDtZxdQADFu/s0tBBYtXi3aWuyFDqF52dGmPw0CsbtVDBZH00EViWc0T+ Un/e+ipU7hHiQmwpqF0OU/p6n31/LPV3wXBwWQttPk6cixPZz478nsgJLUmJV/Ys/X6ZRPcDyeXux UStywPZtxU5KTxlBEUeust2jYLyW0JCrtRsN0HEI1ElSZWj4ps/dpZ99mekh/DJdd8rVVWiF4ae6w fFaAGdEncCudi3rcCTnPXQQjTxU2RhJcQQWRFjI97JTqgzlvMth5LB/oWi+cesiVflyD8yYicJbg+ x0XCFixg==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNP-003TyM-Pi; Mon, 09 Jan 2023 15:43:51 +0100 From: Melissa Wen To: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 02/18] drm/drm_color_mgmt: add shaper LUT to color mgmt properties Date: Mon, 9 Jan 2023 13:38:30 -0100 Message-Id: <20230109143846.1966301-3-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, Shashank Sharma , alex.hung@amd.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Melissa Wen , seanpaul@chromium.org, kernel-dev@igalia.com, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Shaper LUT is used to shape the content after blending, i.e., de-linearize or normalize space before applying a 3D LUT color correction. In the next patch, we add 3D LUT property to DRM color management after this shaper LUT and before the current gamma LUT. Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ drivers/gpu/drm/drm_atomic_uapi.c | 10 ++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 18 ++++++++++++++++++ drivers/gpu/drm/drm_fb_helper.c | 3 +++ drivers/gpu/drm/drm_mode_config.c | 14 ++++++++++++++ include/drm/drm_crtc.h | 14 ++++++++++++-- include/drm/drm_mode_config.h | 12 ++++++++++++ include/drm/drm_mode_object.h | 2 +- 8 files changed, 74 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index bf31b9d92094..4bc860d6cf75 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -141,8 +141,11 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, drm_property_blob_get(state->degamma_lut); if (state->ctm) drm_property_blob_get(state->ctm); + if (state->shaper_lut) + drm_property_blob_get(state->shaper_lut); if (state->gamma_lut) drm_property_blob_get(state->gamma_lut); + state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -214,6 +217,7 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) drm_property_blob_put(state->mode_blob); drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); + drm_property_blob_put(state->shaper_lut); drm_property_blob_put(state->gamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 79730fa1dd8e..5339350c858d 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -430,6 +430,14 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == config->shaper_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->shaper_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->gamma_lut_property) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->gamma_lut, @@ -481,6 +489,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; else if (property == config->ctm_property) *val = (state->ctm) ? state->ctm->base.id : 0; + else if (property == config->shaper_lut_property) + *val = (state->shaper_lut) ? state->shaper_lut->base.id : 0; else if (property == config->gamma_lut_property) *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; else if (property == config->prop_out_fence_ptr) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index d021497841b8..cf6a998b4298 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -69,6 +69,24 @@ * boot-up state too. Drivers can access the blob for the color conversion * matrix through &drm_crtc_state.ctm. * + * “SHAPER_LUT”: + * Blob property to set the shaper lut shaping pixel data after the color + * transformation matrix and before applying 3D Lookup Table (3D LUT). It + * can be used to delinearize content to get an effective 3D LUT mapping. + * The data is interpreted as an array of &struct drm_color_lut elements. + * + * Setting this to NULL (blob property value set to 0) means the output + * color is identical to the input color. This is generally the driver + * boot-up state too. Drivers can access this blob through + * &drm_crtc_state.gamma_lut. + * + * “SHAPER_LUT_SIZE”: + * Unsigned range property to give the size of the shaper lookup table to + * be set on the SHAPER_LUT property (the size depends on the underlying + * hardware). If drivers support multiple LUT sizes then they should + * publish the largest size, and sub-sample smaller sized LUTs + * appropriately. + * * “GAMMA_LUT”: * Blob property to set the gamma lookup table (LUT) mapping pixel data * after the transformation matrix to data sent to the connector. The diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 71edb80fe0fb..f8b4611cbb4a 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -1129,8 +1129,11 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct fb_info *info) replaced = drm_property_replace_blob(&crtc_state->degamma_lut, NULL); replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); + replaced |= drm_property_replace_blob(&crtc_state->shaper_lut, + NULL); replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, gamma_lut); + crtc_state->color_mgmt_changed |= replaced; } diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index 939d621c9ad4..6468cecc7081 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -354,6 +354,20 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.ctm_property = prop; + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, + "SHAPER_LUT", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.shaper_lut_property = prop; + + prop = drm_property_create_range(dev, + DRM_MODE_PROP_IMMUTABLE, + "SHAPER_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + dev->mode_config.shaper_lut_size_property = prop; + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "GAMMA_LUT", 0); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8e1cbc75143e..7f289e0153aa 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -152,8 +152,9 @@ struct drm_crtc_state { bool zpos_changed : 1; /** * @color_mgmt_changed: Color management properties have changed - * (@gamma_lut, @degamma_lut or @ctm). Used by the atomic helpers and - * drivers to steer the atomic commit control flow. + * (@shaper_lut, @gamma_lut, @degamma_lut or @ctm). Used by + * the atomic helpers and drivers to steer the atomic commit control + * flow. */ bool color_mgmt_changed : 1; @@ -279,6 +280,15 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; + /** + * @shaper_lut: + * + * Lookup table used to de-linearize pixel data for gamma correction. + * See drm_crtc_enable_color_mgmt(). The blob (if not NULL) is an array + * of &struct drm_color_lut. + */ + struct drm_property_blob *shaper_lut; + /** * @target_vblank: * diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 6b5e01295348..c174d3a7c951 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -800,6 +800,18 @@ struct drm_mode_config { * degamma LUT. */ struct drm_property *ctm_property; + + /** + * @shaper_lut_property: Optional CRTC property to set the shaper LUT used to + * convert colors before 3D LUT conversion. + */ + struct drm_property *shaper_lut_property; + /** + * @shaper_lut_size_property: Optional CRTC property for the size of the + * shaper LUT as supported by the driver (read-only). + */ + struct drm_property *shaper_lut_size_property; + /** * @gamma_lut_property: Optional CRTC property to set the LUT used to * convert the colors, after the CTM matrix, to the gamma space of the diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index 912f1e415685..5e75b51936e6 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { void (*free_cb)(struct kref *kref); }; -#define DRM_OBJECT_MAX_PROPERTY 24 +#define DRM_OBJECT_MAX_PROPERTY 26 /** * struct drm_object_properties - property tracking for &drm_mode_object */ From patchwork Mon Jan 9 14:38:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBD6AC5479D for ; Mon, 9 Jan 2023 14:44:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95A0210E42E; Mon, 9 Jan 2023 14:44:16 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id ABBF310E1FB for ; Mon, 9 Jan 2023 14:44:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=jMSYSfJzahufrlrBXYv6MHo37VWug9MHt0sn3JWK32A=; b=NbUuCutEZIA1CwE6LAAMFEoZvo V7T66kPVPBJ2c3VViNxi5izJ06I1fqOjNTWi2MBZwDPZmueA1qRGMuLAHnLBAt0V1+VHqHxQTFX5e LlFeTCoV8QNyCDpt+BiNLAvBuvU/SxRiopzVBJ1/DWQI4DSZ+CF8HUi1YrbQp97+JVETnc3ubjd7/ icdu0RAUCs17eNqdV/RLG1bkQfhW32Nic/ywJBIm0I7WSt80PHDDijgrJqNDgugjQ7aHadxjD1McV jG14ZDLm1FzBWDrhTwiYxxImFNqw0SCqa8GDaG7hOaeb1FERtmI1mVG/QUDEaEAy4sXj0eWFbjF/O OOMruEcg==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNS-003TyM-LS; Mon, 09 Jan 2023 15:43:54 +0100 From: Melissa Wen To: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 03/18] drm/drm_color_mgmt: add 3D LUT props to DRM color mgmt Date: Mon, 9 Jan 2023 13:38:31 -0100 Message-Id: <20230109143846.1966301-4-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, Shashank Sharma , alex.hung@amd.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Melissa Wen , seanpaul@chromium.org, kernel-dev@igalia.com, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add 3D LUT for gammar correction using a 3D lookup table. The position in the color correction pipeline where 3D LUT is applied depends on hw design, being after CTM or gamma. If just after CTM, a shaper lut must be set to shape the content for a non-linear space. That details should be handled by the driver according to its color capabilities. --- v3: - refactor CRTC 3D LUT API to use Alex Hung proposal for planes Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++ drivers/gpu/drm/drm_atomic_uapi.c | 14 ++++++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 19 +++++++++++++++++++ drivers/gpu/drm/drm_fb_helper.c | 2 ++ drivers/gpu/drm/drm_mode_config.c | 7 +++++++ include/drm/drm_crtc.h | 20 +++++++++++++++++++- include/drm/drm_mode_config.h | 13 +++++++++++++ include/drm/drm_mode_object.h | 2 +- 8 files changed, 78 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 4bc860d6cf75..6e70f08e2f44 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -143,6 +143,8 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, drm_property_blob_get(state->ctm); if (state->shaper_lut) drm_property_blob_get(state->shaper_lut); + if (state->lut3d) + drm_property_blob_get(state->lut3d); if (state->gamma_lut) drm_property_blob_get(state->gamma_lut); @@ -218,6 +220,7 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); drm_property_blob_put(state->shaper_lut); + drm_property_blob_put(state->lut3d); drm_property_blob_put(state->gamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 5339350c858d..29297badf028 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -438,6 +438,16 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == config->lut3d_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->lut3d, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; + } else if (property == config->lut3d_mode_property) { + state->lut3d_mode = val; } else if (property == config->gamma_lut_property) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->gamma_lut, @@ -491,6 +501,10 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->ctm) ? state->ctm->base.id : 0; else if (property == config->shaper_lut_property) *val = (state->shaper_lut) ? state->shaper_lut->base.id : 0; + else if (property == config->lut3d_property) + *val = (state->lut3d) ? state->lut3d->base.id : 0; + else if (property == config->lut3d_mode_property) + *val = state->lut3d_mode; else if (property == config->gamma_lut_property) *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; else if (property == config->prop_out_fence_ptr) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index cf6a998b4298..f92633b3b67e 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -87,6 +87,25 @@ * publish the largest size, and sub-sample smaller sized LUTs * appropriately. * + * “LUT3D”: + * Blob property to set the 3D LUT mapping pixel data after the color + * transformation matrix and before gamma 1D lut correction. The + * data is interpreted as an array of &struct drm_color_lut elements. + * Hardware might choose not to use the full precision of the LUT + * elements. + * + * Setting this to NULL (blob property value set to 0) means a the output + * color is identical to the input color. This is generally the driver + * boot-up state too. Drivers can access this blob through + * &drm_crtc_state.gamma_lut. + * + * “LUT3D_MODE”: + * Enum property to give the mode of the 3D lookup table to be set on the + * LUT3D property. A mode specifies size, stride, bit depth and color + * format and depends on the underlying hardware). If drivers support + * multiple 3D LUT modes, they should be declared in a array of + * drm_color_lut3d_mode and they will be advertised as an enum. + * * “GAMMA_LUT”: * Blob property to set the gamma lookup table (LUT) mapping pixel data * after the transformation matrix to data sent to the connector. The diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index f8b4611cbb4a..6130c44c79f6 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -1131,6 +1131,8 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct fb_info *info) replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); replaced |= drm_property_replace_blob(&crtc_state->shaper_lut, NULL); + replaced |= drm_property_replace_blob(&crtc_state->lut3d, + NULL); replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, gamma_lut); diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index 6468cecc7081..5c37d84cdabf 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -368,6 +368,13 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.shaper_lut_size_property = prop; + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, + "LUT3D", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.lut3d_property = prop; + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "GAMMA_LUT", 0); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 7f289e0153aa..805a50c36a70 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -152,7 +152,7 @@ struct drm_crtc_state { bool zpos_changed : 1; /** * @color_mgmt_changed: Color management properties have changed - * (@shaper_lut, @gamma_lut, @degamma_lut or @ctm). Used by + * (@shaper_lut, @lut3d, @gamma_lut, @degamma_lut or @ctm). Used by * the atomic helpers and drivers to steer the atomic commit control * flow. */ @@ -289,6 +289,24 @@ struct drm_crtc_state { */ struct drm_property_blob *shaper_lut; + /** + * @lut3d: + * + * 3D Lookup table for converting pixel data. Position where it takes + * place depends on hw design, after @ctm or @gamma_lut. See + * drm_crtc_enable_color_mgmt(). The blob (if not NULL) is an array of + * &struct drm_color_lut. + */ + struct drm_property_blob *lut3d; + + /** + * @lut3d_mode: + * This is a blob_id and exposes the platform capabilities wrt + * various 3dlut. This also helps user select a 3dlut mode amongst + * the supported ones. + */ + u32 lut3d_mode; + /** * @target_vblank: * diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index c174d3a7c951..6cb96f403de2 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -812,6 +812,19 @@ struct drm_mode_config { */ struct drm_property *shaper_lut_size_property; + /** + * @lut3d_property: Optional CRTC property to set the 3D LUT used to + * convert colors; before or after gamma conversion depends on hw + * design. A shaper LUT can be used to delinearize content before apply + * 3D LUT correction. + */ + struct drm_property *lut3d_property; + /** + * @lut3d_mode_property: Optional CRTC property to describe 3D LUT modes + * supported by the driver. + */ + struct drm_property *lut3d_mode_property; + /** * @gamma_lut_property: Optional CRTC property to set the LUT used to * convert the colors, after the CTM matrix, to the gamma space of the diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index 5e75b51936e6..d39ee21f26db 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { void (*free_cb)(struct kref *kref); }; -#define DRM_OBJECT_MAX_PROPERTY 26 +#define DRM_OBJECT_MAX_PROPERTY 28 /** * struct drm_object_properties - property tracking for &drm_mode_object */ From patchwork Mon Jan 9 14:38:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F012C54EBD for ; Mon, 9 Jan 2023 14:44:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2067610E20F; Mon, 9 Jan 2023 14:44:11 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E65310E20D for ; Mon, 9 Jan 2023 14:44:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=OWwQ8u7sFMDvTmb5fE9F6XuAX0AS2r8sgD2pqpPqgV4=; b=kAFclU16RCUbRS43TnofiwMD4I 88haYRtghBErhgU7N0Vs3/2oMPK0osGqyXOle7pnwfTdPC8zxA7afgyaxB847zmvzZZS5YR9QJxBt SYeGP6aRLiGt3gcVIG27e6YTKlj6fvtgBT57xGhAth6lUdKlbUIgRycghvWcnECWiWPT522+cAICU sjm/VokbHlvGZuBpICqX0vG79oWW06ljrIZfkvQutAr6IwuHZU81nfyFC7Wsi814RIYhBvuynavZ8 MfZ8/y0ypnhMKZCYbV/aRhb7WHLaXhQA3Dz/QpgNM3vgt4RFrrDvZMZD8jNJr8B6C5XNfU4FkPMVX tcpMWhsA==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNV-003TyM-Oo; Mon, 09 Jan 2023 15:43:57 +0100 From: Melissa Wen To: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 04/18] drm/drm_color_mgmt: add function to create 3D LUT modes supported Date: Mon, 9 Jan 2023 13:38:32 -0100 Message-Id: <20230109143846.1966301-5-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, Shashank Sharma , alex.hung@amd.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Melissa Wen , seanpaul@chromium.org, kernel-dev@igalia.com, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DRM color function to create modes for lut3d mode property from an array of drm_color_lut3d_mode modes supported by the HW and advertise to userspace. Userspace can get the description of a specific mode in the enum list from its blob data. Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_color_mgmt.c | 43 +++++++++++++++++++++++++++++++- include/drm/drm_color_mgmt.h | 4 +++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index f92633b3b67e..6ce48007cdd4 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -104,7 +104,7 @@ * LUT3D property. A mode specifies size, stride, bit depth and color * format and depends on the underlying hardware). If drivers support * multiple 3D LUT modes, they should be declared in a array of - * drm_color_lut3d_mode and they will be advertised as an enum. + * drm_mode_lut3d_mode and they will be advertised as an enum. * * “GAMMA_LUT”: * Blob property to set the gamma lookup table (LUT) mapping pixel data @@ -228,6 +228,47 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_crtc_enable_color_mgmt); +int drm_crtc_create_lut3d_mode_property(struct drm_crtc *crtc, + const struct drm_mode_lut3d_mode modes[], + unsigned int num_modes) +{ + struct drm_device *dev = crtc->dev; + struct drm_property_blob *blob; + struct drm_property *prop; + char *name; + int ret; + + if (dev->mode_config.lut3d_mode_property) + return 0; + + prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, "LUT3D_MODE", num_modes); + if (!prop) + return -EINVAL; + + for (int i = 0; i < num_modes; i++) { + blob = drm_property_create_blob(dev, sizeof(modes[i]), &modes[i]); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + name = kasprintf(GFP_KERNEL, "lut3d_%d_%dbit", + modes[i].lut_size, modes[i].bit_depth); + if (!name) + return -ENOMEM; + + ret = drm_property_add_enum(prop, blob->base.id, name); + if (ret) { + drm_property_blob_put(blob); + kfree(name); + return ret; + } + kfree(name); + } + dev->mode_config.lut3d_mode_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_lut3d_mode_property); + /** * drm_mode_crtc_set_gamma_size - set the gamma table size * @crtc: CRTC to set the gamma table size for diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 81c298488b0c..af9305925572 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -59,6 +59,10 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, bool has_ctm, uint gamma_lut_size); +int drm_crtc_create_lut3d_mode_property(struct drm_crtc *crtc, + const struct drm_mode_lut3d_mode modes[], + unsigned int num_modes); + int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, int gamma_size); From patchwork Mon Jan 9 14:38:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14A9EC63797 for ; Mon, 9 Jan 2023 14:45:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6182E10E446; Mon, 9 Jan 2023 14:44:45 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDE8810E20D for ; Mon, 9 Jan 2023 14:44:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; 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Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_color_mgmt.c | 35 ++++++++++++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 3 +++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 6ce48007cdd4..06503f693ecd 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -269,6 +269,41 @@ int drm_crtc_create_lut3d_mode_property(struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_crtc_create_lut3d_mode_property); +/** + * drm_crtc_enable_lut3d - enable 3D LUT properties + * @crtc: DRM CRTC + * @shaper_lut_size: the size of shaper lut + * + * This function lets the driver enable the 3D LUT color correction property + * on a CRTC. This includes 3D LUT and also a shaper LUT, if set. The shaper + * LUT property is only attached if its size is not 0 and 3D LUT is set, being + * therefore optional. + */ +void drm_crtc_enable_lut3d(struct drm_crtc *crtc, + uint shaper_lut_size) +{ + struct drm_device *dev = crtc->dev; + struct drm_mode_config *config = &dev->mode_config; + + if (!config->lut3d_mode_property) + return; + + drm_object_attach_property(&crtc->base, + config->lut3d_property, 0); + drm_object_attach_property(&crtc->base, + config->lut3d_mode_property, 0); + + if (!shaper_lut_size) + return; + + drm_object_attach_property(&crtc->base, + config->shaper_lut_property, 0); + drm_object_attach_property(&crtc->base, + config->shaper_lut_size_property, + shaper_lut_size); +} +EXPORT_SYMBOL(drm_crtc_enable_lut3d); + /** * drm_mode_crtc_set_gamma_size - set the gamma table size * @crtc: CRTC to set the gamma table size for diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index af9305925572..db2026dc825e 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -63,6 +63,9 @@ int drm_crtc_create_lut3d_mode_property(struct drm_crtc *crtc, const struct drm_mode_lut3d_mode modes[], unsigned int num_modes); +void drm_crtc_enable_lut3d(struct drm_crtc *crtc, + uint shaper_lut_size); + int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, int gamma_size); From patchwork Mon Jan 9 14:38:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1377C677F1 for ; Mon, 9 Jan 2023 14:44:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 87A8010E439; Mon, 9 Jan 2023 14:44:40 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1806510E20D for ; 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Mon, 09 Jan 2023 15:44:03 +0100 From: Melissa Wen To: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 06/18] drm/drm_color_mgmt: set first lut3d mode as default Date: Mon, 9 Jan 2023 13:38:34 -0100 Message-Id: <20230109143846.1966301-7-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, Shashank Sharma , alex.hung@amd.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Melissa Wen , seanpaul@chromium.org, kernel-dev@igalia.com, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_color_mgmt.c | 18 ++++++++++++++++-- include/drm/drm_color_mgmt.h | 3 ++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 06503f693ecd..d6283f049881 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -280,18 +280,32 @@ EXPORT_SYMBOL(drm_crtc_create_lut3d_mode_property); * therefore optional. */ void drm_crtc_enable_lut3d(struct drm_crtc *crtc, - uint shaper_lut_size) + uint shaper_lut_size, + bool first_value_as_default) { struct drm_device *dev = crtc->dev; struct drm_mode_config *config = &dev->mode_config; + struct drm_property_enum *prop; + uint init_value = 0; if (!config->lut3d_mode_property) return; drm_object_attach_property(&crtc->base, config->lut3d_property, 0); + + if (first_value_as_default) { + prop = list_first_entry_or_null(&config->lut3d_mode_property->enum_list, + typeof(*prop), head); + init_value = prop ? prop->value : 0; + } + drm_object_attach_property(&crtc->base, - config->lut3d_mode_property, 0); + config->lut3d_mode_property, + init_value); + + if (crtc->state && prop) + crtc->state->lut3d_mode = init_value; if (!shaper_lut_size) return; diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index db2026dc825e..d13e99e2e877 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -64,7 +64,8 @@ int drm_crtc_create_lut3d_mode_property(struct drm_crtc *crtc, unsigned int num_modes); void drm_crtc_enable_lut3d(struct drm_crtc *crtc, - uint shaper_lut_size); + uint shaper_lut_size, + bool first_value_as_default); int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, int gamma_size); From patchwork Mon Jan 9 14:38:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9980C54EBD for ; Mon, 9 Jan 2023 14:44:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4003610E434; Mon, 9 Jan 2023 14:44:27 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9510F10E431; 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Mon, 09 Jan 2023 15:44:06 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 07/18] drm/amd/display: remove unused regamma condition Date: Mon, 9 Jan 2023 13:38:35 -0100 Message-Id: <20230109143846.1966301-8-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The function __set_output_tf is only called by amdgpu_dm_update_crtc_color_mgmt() when using atomic regamma. In this situation, func->tf == TRANSFER_FUNCTION_LINEAR (the original if condition) and it never falls into tf != LINEAR (the else condition). Therefore, remove unused condition to avoid misunderstandings here. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 32 ++++++------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index a4cb23d059bd..10a29d131424 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -255,14 +255,13 @@ static int __set_legacy_tf(struct dc_transfer_func *func, * @func: transfer function * @lut: lookup table that defines the color space * @lut_size: size of respective lut - * @has_rom: if ROM can be used for hardcoded curve * * Returns: * 0 in case of success. -ENOMEM if fails. */ static int __set_output_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size, - bool has_rom) + const struct drm_color_lut *lut, + uint32_t lut_size) { struct dc_gamma *gamma = NULL; struct calculate_buffer cal_buffer = {0}; @@ -279,24 +278,13 @@ static int __set_output_tf(struct dc_transfer_func *func, gamma->num_entries = lut_size; __drm_lut_to_dc_gamma(lut, gamma, false); - if (func->tf == TRANSFER_FUNCTION_LINEAR) { - /* - * Color module doesn't like calculating regamma params - * on top of a linear input. But degamma params can be used - * instead to simulate this. - */ - gamma->type = GAMMA_CUSTOM; - res = mod_color_calculate_degamma_params(NULL, func, - gamma, true); - } else { - /* - * Assume sRGB. The actual mapping will depend on whether the - * input was legacy or not. - */ - gamma->type = GAMMA_CS_TFM_1D; - res = mod_color_calculate_regamma_params(func, gamma, false, - has_rom, NULL, &cal_buffer); - } + /* + * Color module doesn't like calculating regamma params + * on top of a linear input. But degamma params can be used + * instead to simulate this. + */ + gamma->type = GAMMA_CUSTOM; + res = mod_color_calculate_degamma_params(NULL, func, gamma, true); dc_gamma_release(&gamma); @@ -450,7 +438,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; r = __set_output_tf(stream->out_transfer_func, regamma_lut, - regamma_size, has_rom); + regamma_size); if (r) return r; } else { From patchwork Mon Jan 9 14:38:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7B7DC677F1 for ; Mon, 9 Jan 2023 14:44:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 404AD10E433; Mon, 9 Jan 2023 14:44:26 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4464310E431; Mon, 9 Jan 2023 14:44:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=yZ+XADzHjwvGta78ZXBVQh4OGwv1Wat6G9lgsepYSyM=; b=A/BXeZXWL4HuH8i/jEvBcxdnAv ZDsm7EoqvVho9tRzSvxMx5l4aPf22MNse6N3kGsUoap3ZhaioKJwEu3AabOZ0SCuQyzQGjymoJIxn dFdeJ+/UaZT78/RRF8hzAL1vgoSkiPYc5W4WBtxJoxrYZiRDqvs5IYjuvy9m3P20Om7NgHGfBXYoj onOeJwyXdUwGEwix+YsVHbjprxp2c85esOC/K8ZvQLYJfkACHj/FfyRZRJaFyZxT5djIDBXBWjRqu V5K9X5grXuwBaSqY27q01RexqFEuzv9eQLEUnWCmEAvOZgoZ3vLyR5UG1fFFg247+d0p1ghdRQOQg djDdGOsA==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNh-003TyM-5k; Mon, 09 Jan 2023 15:44:09 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 08/18] drm/amd/display: add comments to describe DM crtc color mgmt behavior Date: Mon, 9 Jan 2023 13:38:36 -0100 Message-Id: <20230109143846.1966301-9-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Describe some expected behavior of the AMD DM color mgmt programming. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 10a29d131424..b54ef1392895 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -428,12 +428,23 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + /* Note: even if we pass has_rom as parameter here, we never + * actually use ROM because the color module only takes the ROM + * path if transfer_func->type == PREDEFINED. + * + * See more in mod_color_calculate_regamma_params() + */ r = __set_legacy_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); if (r) return r; } else if (has_regamma) { - /* If atomic regamma, CRTC RGM goes into RGM LUT. */ + /* CRTC RGM goes into RGM LUT. + * + * Note: here there is no implicit sRGB regamma. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; From patchwork Mon Jan 9 14:38:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 566BFC54EBD for ; Mon, 9 Jan 2023 14:44:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2876A10E42F; Mon, 9 Jan 2023 14:44:27 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id A16BF10E432; Mon, 9 Jan 2023 14:44:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Dv8TSHDNAro72IZgP4TBGST9tD70PdSgMAoaPaXFYjA=; b=dMseIfbldn976aWH7M42s84hjC e/k/kalfXPDw9ej+Ie0mXfYT7p+QWyIG3OK5iNBnnTFZeMj+/Ux/pSceAd7QiJWyTCFIG65houhAm znB5K2uIJkvZZxFV2LhaGj4LEc5OKtofnFuI8IU7JXbveSk7bPGgmtt3WOs3YyzD1teQbdGVHWpE6 sqq6G/LyZE6kWa6Uc+kGlaZEbMN5fW6BgFzsBycjV7xZCxU1HtxP62hNeN0hjT82DPNHYMU7DDc0S 755Wku2S7ww5JOdcfmh/QA9bD237HYOU6uX2LB3u8z1GuHAeJ0vsqv+bG4uiJUx+HmERR9OMDzLXB u3mEW2kQ==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNk-003TyM-1d; Mon, 09 Jan 2023 15:44:12 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 09/18] drm/amd/display: encapsulate atomic regamma operation Date: Mon, 9 Jan 2023 13:38:37 -0100 Message-Id: <20230109143846.1966301-10-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We are introducing DRM 3D LUT property to DM color pipeline in the next patch, but so far, only for atomic interface. By checking .set_output_transfer_func in DC drivers with MPC 3D LUT support, we can verify that regamma is only programmed when 3D LUT programming fails. As a groundwork to introduce 3D LUT programming and better understand each step, detach atomic regamma programming from the crtc colocr updating code. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ++++++++++++------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index b54ef1392895..54d95745f0f0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -291,6 +291,36 @@ static int __set_output_tf(struct dc_transfer_func *func, return res ? 0 : -ENOMEM; } +static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, + const struct drm_color_lut *regamma_lut, + uint32_t regamma_size) +{ + int ret = 0; + + if (regamma_size) { + /* CRTC RGM goes into RGM LUT. + * + * Note: here there is no implicit sRGB regamma. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + + ret = __set_output_tf(stream->out_transfer_func, regamma_lut, + regamma_size); + } else { + /* + * No CRTC RGM means we can just put the block into bypass + * since we don't have any plane level adjustments using it. + */ + stream->out_transfer_func->type = TF_TYPE_BYPASS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + return ret; +} + /** * __set_input_tf - calculates the input transfer function based on expected * input space. @@ -438,27 +468,11 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) regamma_size, has_rom); if (r) return r; - } else if (has_regamma) { - /* CRTC RGM goes into RGM LUT. - * - * Note: here there is no implicit sRGB regamma. We are using - * degamma calculation from color module to calculate the curve - * from a linear base. - */ - stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - - r = __set_output_tf(stream->out_transfer_func, regamma_lut, - regamma_size); + } else { + regamma_size = has_regamma ? regamma_size : 0; + r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, regamma_size); if (r) return r; - } else { - /* - * No CRTC RGM means we can just put the block into bypass - * since we don't have any plane level adjustments using it. - */ - stream->out_transfer_func->type = TF_TYPE_BYPASS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; } /* From patchwork Mon Jan 9 14:38:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B31B4C54EBE for ; Mon, 9 Jan 2023 14:45:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC8C810E4A2; Mon, 9 Jan 2023 14:44:47 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8ECC010E438; Mon, 9 Jan 2023 14:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=nDAiETVpEvUgb7mqS6Y9TlEIy67mC7r1XqqTtdFTtiY=; b=kHyTtVGwbnVzhzXBtMOs71gktY Ie73QRlCKbRBdTSjXoGo/ArajaRk41KPu+1YdmWbhgvc2qKOFPK3gQsrtSiqOq1cgPsTp4WZmJO+4 0qcBRxvxrKMYIFzdGx6gGfLUUWZ/VHDF31/5SBXqVADhdo2hxhQmfl3CNbOkWWSn9PZ7QQR2hwamb 6AP2zQ3IHyOs7SBrkeEms8rtNK1ot7SfTdo2gaYYKAzEH6YviSli630lSGSoOaQlohu2svXmQN141 reDGPodRElCD2SUYzfrqxPWeOJVzTOJZ/NnrOCoq8D8DKiSRZzHoGbNAoHMAUC4lCYx8WMhunx3lb yDsf57Yg==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNm-003TyM-TO; Mon, 09 Jan 2023 15:44:15 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 10/18] drm/amd/display: update lut3d and shaper lut to stream Date: Mon, 9 Jan 2023 13:38:38 -0100 Message-Id: <20230109143846.1966301-11-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It follows the same path of out_transfer_func for stream updates, since shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func() and this function is called in the atomic commit_tail when update_flags.bits.out_tf is set. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 2c18c8527079..88f1130c3b83 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2562,7 +2562,7 @@ static enum surface_update_type check_update_surfaces_for_stream( stream_update->integer_scaling_update) su_flags->bits.scaling = 1; - if (stream_update->out_transfer_func) + if (stream_update->out_transfer_func || stream_update->lut3d_func) su_flags->bits.out_tf = 1; if (stream_update->abm_level) @@ -2911,6 +2911,14 @@ static void copy_stream_update_to_stream(struct dc *dc, sizeof(struct dc_transfer_func_distributed_points)); } + if (update->func_shaper && + stream->func_shaper != update->func_shaper) + stream->func_shaper = update->func_shaper; + + if (update->lut3d_func && + stream->lut3d_func != update->lut3d_func) + stream->lut3d_func = update->lut3d_func; + if (update->hdr_static_metadata) stream->hdr_static_metadata = *update->hdr_static_metadata; From patchwork Mon Jan 9 14:38:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D858C54EBD for ; Mon, 9 Jan 2023 14:44:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 390E510E43D; Mon, 9 Jan 2023 14:44:42 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E62710E436; Mon, 9 Jan 2023 14:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=JvdJXnslHHYsgYx1+6dyB2NO+WCy/ybpW/Ce1OI2Y1Y=; b=oFeG4//hpK2jBA7q7YDjh9O3MP MrTl+XG5rT7dFkVcuflFVAxGYcHkBStWwZEn1I+g1hKW44inrZscTIF89dliIBAmFAp9Yht9FBzCZ yK0OGg9D8EjtcmRb9ofCB3z12mqk7T8cVO645dW7vr8E886R+/0VMdLhkJ5S94PrlFBXVwTkBiX46 +FjtlTsZze7KVLJivFkCIIzlqKFebegFw6to/HBPRPCFveVo1kTYCqXTDjyWFZ0yeD8m/h22MWLvq If3wd1EvsviA/NSTlQhIkXMQXfoKVzQ+BqM/+nYHaaqXPUX6snH1qwqjaOF55XJbpJYqQxwTkbG68 Ka8ZgSmg==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNp-003TyM-JJ; Mon, 09 Jan 2023 15:44:17 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 11/18] drm/amd/display: handle MPC 3D LUT resources for a given context Date: Mon, 9 Jan 2023 13:38:39 -0100 Message-Id: <20230109143846.1966301-12-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In the original dc_acquire_release_mpc_3dlut(), only current ctx is considered, which doesn't fit the steps for atomic checking new ctx. Therefore, create a function to handle 3D LUT resource for a given context, so that we can check resources availability in atomic_check time and handle failures properly. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 8 +++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 88f1130c3b83..76270d21286a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2085,6 +2085,45 @@ bool dc_acquire_release_mpc_3dlut( return ret; } +bool +dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc, + bool acquire, + struct dc_state *state, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper) +{ + int pipe_idx; + bool ret = false; + bool found_pipe_idx = false; + const struct resource_pool *pool = dc->res_pool; + struct resource_context *res_ctx = &state->res_ctx; + int mpcc_id = 0; + + if (pool && res_ctx) { + if (acquire) { + /*find pipe idx for the given stream*/ + for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { + if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { + found_pipe_idx = true; + mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; + break; + } + } + } else + found_pipe_idx = true;/*for release pipe_idx is not required*/ + + if (found_pipe_idx) { + if (acquire && pool->funcs->acquire_post_bldn_3dlut) + ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); + else if (!acquire && pool->funcs->release_post_bldn_3dlut) + ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper); + } + } + return ret; +} + + static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 72963617553e..a5abf7f308c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1345,6 +1345,14 @@ bool dc_acquire_release_mpc_3dlut( struct dc_3dlut **lut, struct dc_transfer_func **shaper); +bool +dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc, + bool acquire, + struct dc_state *state, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + void dc_resource_state_copy_construct( const struct dc_state *src_ctx, struct dc_state *dst_ctx); From patchwork Mon Jan 9 14:38:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BC9FC63797 for ; Mon, 9 Jan 2023 14:44:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B04710E448; Mon, 9 Jan 2023 14:44:45 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 427B410E436; Mon, 9 Jan 2023 14:44:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=cKIgQ2NkBMGH8emqa7YtqDB/L0xQKuwdjNrEqIF3P4M=; b=KydMXJYozSRjwD7sxmrNzx74C+ RMz3tPCTbB6hNYG1aEeMkMGEAJLl8mjAsTqD/ewUWWEN1piHTlumNaX3yKfqdSRmJgnbXep+7GcEL 75jfb/AilU3RnAbKzZNU/oMuaA5lrQmfhR5SInbLz9PhFdwzo5Tsj0kf2kNFDReaIdOAb1/3yk7oo 2Gt3+ixBw9Ju92ttxATxODpwBvQel9wTng+5qq37UpRnFrf7MfzCtJ2VHmlSBl9yGR5I9eksK+H76 o0V9quBXJG6DFp1WArCbriL876r71WmZHe8iLga0rc/QGK1OZjV6zTznB8ffpyc7YQA8yaDIrV28M hU+Er4dQ==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNs-003TyM-8H; Mon, 09 Jan 2023 15:44:20 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 12/18] drm/amd/display: acquire/release 3D LUT resources for ctx on DCN301 Date: Mon, 9 Jan 2023 13:38:40 -0100 Message-Id: <20230109143846.1966301-13-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Acquire and release 3D LUT and shaper LUT every time we create/remove a new ctx and add/remove stream to/from it. 3D LUT acquire/release can fail and therefore we should check its availability during atomic check considering the new context created not the current one. Signed-off-by: Melissa Wen --- .../amd/display/dc/dcn301/dcn301_resource.c | 47 ++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c index ee62ae3eb98f..5bae0972bd5e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -1260,6 +1260,49 @@ static struct display_stream_compressor *dcn301_dsc_create( return &dsc->base; } +static enum dc_status +dcn301_add_stream_to_ctx(struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) +{ + enum dc_status result = DC_ERROR_UNEXPECTED; + struct dc_3dlut *lut3d_func_new = NULL; + struct dc_transfer_func *func_shaper_new = NULL; + + result = dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream); + if (result != DC_OK) + return result; + + if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, true, new_ctx, dc_stream, + &lut3d_func_new, &func_shaper_new)) + return DC_ERROR_UNEXPECTED; + + dc_stream->lut3d_func = lut3d_func_new; + dc_stream->func_shaper = func_shaper_new; + + return DC_OK; +} + +static enum dc_status +dcn301_remove_stream_from_ctx(struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) +{ + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *func_shaper; + + lut3d_func = (struct dc_3dlut *)dc_stream->lut3d_func; + func_shaper = (struct dc_transfer_func *)dc_stream->func_shaper; + + if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, false, new_ctx, dc_stream, + &lut3d_func, &func_shaper)) + return DC_ERROR_UNEXPECTED; + + dc_stream->lut3d_func = lut3d_func; + dc_stream->func_shaper = func_shaper; + + return dcn20_remove_stream_from_ctx(dc, new_ctx, dc_stream); +} static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1406,9 +1449,9 @@ static struct resource_funcs dcn301_res_pool_funcs = { .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, - .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_stream_to_ctx = dcn301_add_stream_to_ctx, .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, - .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .remove_stream_from_ctx = dcn301_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, From patchwork Mon Jan 9 14:38:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82AD5C5479D for ; Mon, 9 Jan 2023 14:44:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D0E610E43E; Mon, 9 Jan 2023 14:44:43 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A12410E436; Mon, 9 Jan 2023 14:44:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=cUoeBdofxkXT9xFOFSawmIrJOWQdaUxVUBcCykFvQKk=; b=PbpZ4nD0OTMS3q3O0nQsr54b3O GqC9EJeBrL8zeqDYc6S74QTyTMFncpixOmXOs+QL71atJRURwswLPZ3rkffhW6th+uJefkjfvPauc nzuvo9Znfu+d/uybFmKXDkwG/qlQyv7pjEyyc8DkWC4ZskaIJcJXw4RhL22kho7U5aLcyAKSFPfJh sG3B/0blpbXjNxJNmFQcyr8tcpLhsmjRCCCdYZbeg/3fYR+/yvOav9W9rDFj9qeH2xM1kFeR1D0WL P6SRgKAIY2xPlKhUlPK/kcdRGw9L2IQIxHbL7micTwx9852i3bEHw8AHXVl0K5pDyU3gpqL3aqcNp s+1cN9Tg==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNu-003TyM-OC; Mon, 09 Jan 2023 15:44:22 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 13/18] drm/amd/display: Define 3D LUT struct for HDR planes Date: Mon, 9 Jan 2023 13:38:41 -0100 Message-Id: <20230109143846.1966301-14-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Alex Hung Add a 3D LUT mode supported by amdgpu driver. Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/modules/color/color_gamma.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h index 2893abf48208..8e159b1eb9c6 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h @@ -27,6 +27,7 @@ #define COLOR_MOD_COLOR_GAMMA_H_ #include "color_table.h" +#include struct dc_transfer_func; struct dc_gamma; @@ -35,6 +36,17 @@ struct dc_rgb_fixed; struct dc_color_caps; enum dc_transfer_func_predefined; +/* + * 3D LUT mode for 17x17x17 LUT and 12 bits of color depth + */ +static const struct drm_mode_lut3d_mode lut3d_mode_17_12bit = { + .lut_size = 17, + .lut_stride = {17, 17, 18}, + .bit_depth = 12, + .color_format = DRM_FORMAT_XRGB16161616, + .flags = 0, +}; + /* For SetRegamma ADL interface support * Must match escape type */ From patchwork Mon Jan 9 14:38:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 864BDC5479D for ; Mon, 9 Jan 2023 14:45:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 93A5210E43A; Mon, 9 Jan 2023 14:44:51 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0CB8110E439; Mon, 9 Jan 2023 14:44:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=TnpDW0+fbBbPza9wMiMd8HlnPnuskPiG6Rgbq1iBi8g=; b=TWlBIDGPLku7ghz50n9qdn+SRR rSsoJ5irFxQwjH15eFYk2IYJNrqpRurnCYXnxw8WGxnaWVqs7UDlgQyYIBvLG24rYFugu5wijcoZv D0f6aZZUucwt2K6Z8czdhtetq5QjYHLt51W5IrZuwDpY0zWIa8YnszsUXY/aF8qtWcguCFcJ+L14a X89hvd3/m7fir50TxzHQv1WUOJfvo4JiUrZMeQt9uNvQf6xeUrKn9r+fuIGn43F4m6BQRYWY1LPoa 45WaPqH8IRnEpNo9jpedCoIFIWWrEiWODP/gUFrutpPMPqb06Dt/vkFD/F0gu1cjz6kCdboGFe/fX xiBK5j1w==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtNx-003TyM-HA; Mon, 09 Jan 2023 15:44:25 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 14/18] drm/amd/display: expand array of supported 3D LUT modes Date: Mon, 9 Jan 2023 13:38:42 -0100 Message-Id: <20230109143846.1966301-15-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" AMD MPC block support 3D LUTs of dimensions 17 and 9, and also bit depth 12 and 10, therefore, advertise them to the userspace. Signed-off-by: Melissa Wen --- .../amd/display/modules/color/color_gamma.h | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h index 8e159b1eb9c6..69b9a1aa6dd4 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h @@ -47,6 +47,37 @@ static const struct drm_mode_lut3d_mode lut3d_mode_17_12bit = { .flags = 0, }; +static const struct drm_mode_lut3d_mode amdgpu_lut3d_modes[] = { + { + .lut_size = 17, + .lut_stride = {17, 17, 18}, + .bit_depth = 12, + .color_format = DRM_FORMAT_XRGB16161616, + .flags = 0, + }, + { + .lut_size = 17, + .lut_stride = {17, 17, 18}, + .bit_depth = 10, + .color_format = DRM_FORMAT_XRGB16161616, + .flags = 0, + }, + { + .lut_size = 9, + .lut_stride = {9, 9, 10}, + .bit_depth = 12, + .color_format = DRM_FORMAT_XRGB16161616, + .flags = 0, + }, + { + .lut_size = 9, + .lut_stride = {9, 9, 10}, + .bit_depth = 10, + .color_format = DRM_FORMAT_XRGB16161616, + .flags = 0, + }, +}; + /* For SetRegamma ADL interface support * Must match escape type */ From patchwork Mon Jan 9 14:38:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2183BC5479D for ; Mon, 9 Jan 2023 14:44:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF4AA10E43C; Mon, 9 Jan 2023 14:44:44 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 406B010E439; Mon, 9 Jan 2023 14:44:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZCptQBuswI/6532/AawbFb3j3pOVVg8UESVSw9Oz040=; b=SDt7HTphwrkTub4quSZqs591ga 4Jw6+A1lhiJFBpNOyXWDMWLY7/5ryJtWJib04JB3DOmjHR7xgb2fj1HuZXTBNrrLrhaKqlJll18lR YmTbvoiQdsQyjrh+yX6jy7WYFU4uR/1wdGNy5nr75+6ZymZMHV1fw7RjDTXJv8P53HAKkUEcA5+SD A4wjPQWyC9JceRKtjgwZSDacBQ+OH4jCQEwHhEERAIcUWJPm0odQeGIGqF5eGl2blWyKCdFG/9KBS 54/5U1QAHEOjru/135okKr08d9XXdOIHrHrXzi1iPzjcXnEgjZe8cTQ+dVp5wUIVgQNo9g5Ez9uAS 95uVWtaw==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtO0-003TyM-EC; Mon, 09 Jan 2023 15:44:28 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 15/18] drm/amd/display: enable 3D-LUT DRM properties if supported Date: Mon, 9 Jan 2023 13:38:43 -0100 Message-Id: <20230109143846.1966301-16-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable DRM crtc properties related to 3D LUT resources (shaper LUT, 3D LUT and 3D LUT modes) if it's supported by DCN HW, that means DCN families 3.0+ Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 25 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index abbbb3813c1e..6f04719d0c1f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -786,6 +786,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); void amdgpu_dm_init_color_mod(void); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); +void amdgpu_dm_enable_lut3d_prop(struct amdgpu_display_manager *dm, struct drm_crtc *crtc); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct dc_plane_state *dc_plane_state); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 54d95745f0f0..c547957acd73 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -388,6 +388,31 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) return 0; } +static bool has_mpc_lut3d_caps(struct amdgpu_display_manager *dm) +{ + return dm->dc->caps.color.mpc.num_3dluts ? true : false; +} + +/** + * amdgpu_dm_enable_lut3d_prop - enable 3D LUT DRM props if HW supports + * @crtc: DRM crtc + * @dm: amdgpu display manager + */ +void amdgpu_dm_enable_lut3d_prop(struct amdgpu_display_manager *dm, struct drm_crtc *crtc) +{ + int res; + + if (!has_mpc_lut3d_caps(dm)) + return; + + res = drm_crtc_create_lut3d_mode_property(crtc, amdgpu_lut3d_modes, + ARRAY_SIZE(amdgpu_lut3d_modes)); + if (res) + drm_dbg(crtc->dev, "CRTC init: Failed to create LUT 3D mode properties\n"); + + drm_crtc_enable_lut3d(crtc, MAX_COLOR_LUT_ENTRIES, true); +} + /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. * @crtc: amdgpu_dm crtc state diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 22125daf9dcf..96494f72a6f4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -461,6 +461,8 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, true, MAX_COLOR_LUT_ENTRIES); + amdgpu_dm_enable_lut3d_prop(dm, &acrtc->base); + drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); return 0; From patchwork Mon Jan 9 14:38:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DF63C54EBD for ; Mon, 9 Jan 2023 14:45:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80E1510E44A; Mon, 9 Jan 2023 14:44:52 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFB9010E43C; Mon, 9 Jan 2023 14:44:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=HeVvASVwSPvTBBOKCtKle28VHGRGJ5Bf1epIXUPS7F8=; b=GybGvlWqfm6ovfBUhiN4m7QaBC yHuX0i7B2fggXdbV1+pVjWEQsWb0TktWrKmzjra1hUFrJDs6eE96WES99JfRnWQCl0F+/KCwwq2j7 GKD5aBqcho/K+4Cxd83yHeqoVDtDIbydeZypcMhT3c/ymRGzJZ1K2ClwagI4jkb3Pf/M2n5jUY+wT E+iA9/x7RF/TX476mmK/Ft7sWH6Py8Bm/fsryd3cuVCnn5B2j6rV7eRDnHU7+XS69DTn7lumiTuey aO8Vz4vjJo5/GoCb3RVfI7LGvg6JwzELF1C7NzoylJysyMxyF+ZkQtuhrlQCWCCj0FjQS2D9Kv7NB Zm3+bUUw==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtO4-003TyM-6y; Mon, 09 Jan 2023 15:44:32 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 16/18] drm/amd/display: add user 3D LUT support to the amdgpu_dm color pipeline Date: Mon, 9 Jan 2023 13:38:44 -0100 Message-Id: <20230109143846.1966301-17-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Map DRM 3D LUT in the atomic color mgmt pipeline to DC. 3D LUT works better in a non-linear color space, therefore using a degamma to linearize the input space may produce unexpected results. The next patch introduces shaper LUT support that can be used to delinearize the color space before applying 3D LUT conversion. Note that there is no implicit sRGB degamma/regamma in the current implementation for DRM atomic color mgmt. Atomic degamma/regamma 1D LUT is applied considering a linear base. For reference, see IGT test amdgpu/amd_color and commit cf020d49b3c4 ("drm/amd/display: Rework CRTC color management") dc_acquire_release_mpc_3dlut initializes the bits required to program 3DLUT in DC MPC hw block, that is applied by set_output_transfer_func(). I still need to double check the timing to acquire and release shaper and 3D LUTs from the resource pool. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 189 ++++++++++++++++++ 3 files changed, 197 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b8638f0508b0..7aa41dd2143b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9704,6 +9704,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } + ret = amdgpu_dm_verify_lut3d_size(adev, new_crtc_state); + if (ret) { + DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); + goto fail; + } + if (!new_crtc_state->enable) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 6f04719d0c1f..59ab1b8f7b05 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -786,6 +786,8 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); void amdgpu_dm_init_color_mod(void); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); +int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state); void amdgpu_dm_enable_lut3d_prop(struct amdgpu_display_manager *dm, struct drm_crtc *crtc); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index c547957acd73..0fb1244c8aef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -413,6 +413,175 @@ void amdgpu_dm_enable_lut3d_prop(struct amdgpu_display_manager *dm, struct drm_c drm_crtc_enable_lut3d(crtc, MAX_COLOR_LUT_ENTRIES, true); } +static void __to_dc_lut3d_color(struct dc_rgb *rgb, + const struct drm_color_lut lut, + int bit_precision) +{ + rgb->red = drm_color_lut_extract(lut.red, bit_precision); + rgb->green = drm_color_lut_extract(lut.green, bit_precision); + rgb->blue = drm_color_lut_extract(lut.blue, bit_precision); +} + +static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut, + uint32_t lut3d_size, + struct tetrahedral_params *params, + bool use_tetrahedral_9, + int bit_depth) +{ + struct dc_rgb *lut0; + struct dc_rgb *lut1; + struct dc_rgb *lut2; + struct dc_rgb *lut3; + int lut_i, i; + + + if (use_tetrahedral_9) { + lut0 = params->tetrahedral_9.lut0; + lut1 = params->tetrahedral_9.lut1; + lut2 = params->tetrahedral_9.lut2; + lut3 = params->tetrahedral_9.lut3; + } else { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + } + + for (lut_i = 0, i = 0; i < lut3d_size - 4; lut_i++, i += 4) { + /* We should consider the 3dlut RGB values are distributed + * along four arrays lut0-3 where the first sizes 1229 and the + * other 1228. The bit depth supported for 3dlut channel is + * 12-bit, but DC also supports 10-bit. + * + * TODO: improve color pipeline API to enable the userspace set + * bit depth and 3D LUT size/stride, as specified by VA-API. + */ + __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); + __to_dc_lut3d_color(&lut1[lut_i], lut[i + 1], bit_depth); + __to_dc_lut3d_color(&lut2[lut_i], lut[i + 2], bit_depth); + __to_dc_lut3d_color(&lut3[lut_i], lut[i + 3], bit_depth); + } + /* lut0 has 1229 points (lut_size/4 + 1) */ + __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); +} + +/* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream + * @stream: DC stream state to set shaper LUT and 3D LUT + * @drm_lut3d: DRM CRTC (user) 3D LUT + * @drm_lut3d_size: size of 3D LUT + * @lut3d: DC 3D LUT + * + * Map DRM CRTC 3D LUT to DC 3D LUT and all necessary bits to program it + * on DCN MPC accordingly. + */ +static void amdgpu_dm_atomic_lut3d(struct dc_stream_state *stream, + const struct drm_color_lut *drm_lut, + uint32_t drm_lut3d_size, + const struct drm_mode_lut3d_mode *mode, + struct dc_3dlut *lut) +{ + int size = mode->lut_size * mode->lut_size * mode->lut_size; + + ASSERT(lut && drm_lut3d_size == size); + + /* Stride and bit depth is not programmable by API so far. Therefore, + * only supports 17x17x17 3D LUT with 12-bit. + */ + lut->lut_3d.use_tetrahedral_9 = mode->lut_size == 9; + lut->lut_3d.use_12bits = mode->bit_depth == 12; + lut->state.bits.initialized = 1; + + __drm_3dlut_to_dc_3dlut(drm_lut, size, &lut->lut_3d, + lut->lut_3d.use_tetrahedral_9, mode->bit_depth); + + stream->lut3d_func = lut; +} + +/* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC + * interface + * @dc: Display Core control structure + * @stream: DC stream state to set shaper LUT and 3D LUT + * @drm_lut3d: DRM CRTC (user) 3D LUT + * @drm_lut3d_size: size of 3D LUT + * + * Returns: + * 0 on success. + */ +static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, + struct dc_stream_state *stream, + const struct drm_color_lut *drm_lut3d, + uint32_t drm_lut3d_size, + const struct drm_mode_lut3d_mode *mode) +{ + struct dc_3dlut *lut3d_func_new; + struct dc_transfer_func *func_shaper_new; + + lut3d_func_new = (struct dc_3dlut *) stream->lut3d_func; + func_shaper_new = (struct dc_transfer_func *) stream->func_shaper; + + /* We don't get DRM shaper LUT yet. We assume the input color space is + * already delinearized, so we don't need a shaper LUT and we can just + * BYPASS. + */ + func_shaper_new->type = TF_TYPE_BYPASS; + func_shaper_new->tf = TRANSFER_FUNCTION_LINEAR; + stream->func_shaper = func_shaper_new; + + amdgpu_dm_atomic_lut3d(stream, drm_lut3d, drm_lut3d_size, + mode, lut3d_func_new); + + return 0; +} + +static const struct drm_mode_lut3d_mode * +get_lut3d_mode(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state) +{ + struct drm_property_blob *blob; + + if (!has_mpc_lut3d_caps(&adev->dm)) + return NULL; + + blob = drm_property_lookup_blob(crtc_state->state->dev, + crtc_state->lut3d_mode); + + return blob ? (const struct drm_mode_lut3d_mode *)blob->data : NULL; +} + +/** + * amdgpu_dm_verify_lut3d_size - verifies if 3D LUT is supported and if DRM 3D + * LUT matches the hw supported size + * @adev: amdgpu device + * @crtc_state: the DRM CRTC state + * + * Verifies if post-blending (MPC) 3D LUT is supported by the HW (DCN 3.0 or + * newer) and if the DRM 3D LUT matches the supported size. + * + * Returns: + * 0 on success. -EINVAL if lut size are invalid. + */ +int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state) +{ + const struct drm_color_lut *lut3d = NULL; + const struct drm_mode_lut3d_mode *mode; + uint32_t exp_size, size; + + mode = get_lut3d_mode(adev, crtc_state); + exp_size = mode ? mode->lut_size * mode->lut_size * mode->lut_size : 0; + + lut3d = __extract_blob_lut(crtc_state->lut3d, &size); + + if (lut3d && size != exp_size) { + DRM_DEBUG_DRIVER("Invalid Gamma 3D LUT size. Should be %u but got %u.\n", + exp_size, size); + return -EINVAL; + } + + return 0; +} + + /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. * @crtc: amdgpu_dm crtc state @@ -442,8 +611,11 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) bool has_rom = adev->asic_type <= CHIP_RAVEN; struct drm_color_ctm *ctm = NULL; const struct drm_color_lut *degamma_lut, *regamma_lut; + const struct drm_color_lut *lut3d; uint32_t degamma_size, regamma_size; + uint32_t lut3d_size; bool has_regamma, has_degamma; + bool has_lut3d; bool is_legacy; int r; @@ -451,12 +623,19 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) if (r) return r; + r = amdgpu_dm_verify_lut3d_size(adev, &crtc->base); + if (r) + return r; + degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); + lut3d = __extract_blob_lut(crtc->base.lut3d, &lut3d_size); regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); has_degamma = degamma_lut && !__is_lut_linear(degamma_lut, degamma_size); + has_lut3d = lut3d != NULL; + has_regamma = regamma_lut && !__is_lut_linear(regamma_lut, regamma_size); @@ -494,6 +673,16 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) if (r) return r; } else { + if (has_lut3d) { + r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, stream, lut3d, lut3d_size, + get_lut3d_mode(adev, &crtc->base)); + if (r) + return r; + } + /* Note: OGAM is disabled if 3D LUT is successfully programmed. + * See params and set_output_gamma in + * dcn30_set_output_transfer_func() + */ regamma_size = has_regamma ? regamma_size : 0; r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, regamma_size); if (r) From patchwork Mon Jan 9 14:38:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47830C5479D for ; Mon, 9 Jan 2023 14:45:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D31F10E4A7; Mon, 9 Jan 2023 14:45:04 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7091310E451; Mon, 9 Jan 2023 14:44:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=2zK6khS89ThpmVaHiRDcsbcddbtTFdwhm1vSRQdPNqQ=; b=f1FH40gSKxdQJGhbFNvdkdwPo2 2X2NSIOskXk+ypl8si36Usf3NWqtJqUwuak0ujIcj1akVquJuy5uooBVl5gdOtYW15GVUP5eQl4Rv 41f/Ukbr7PJ6dGpgqi4hcQd4siyK38kSRKkaIenpC0PszhAy5cXygnEYs1RdODCMHI/rC+qeqVFNF 9rcB8IeJ7za8s1OKx6lQTdK/b5dI9hw/gqb7TIEkJkWkkO0K0TAnH2RhdO6wgC4lqa8ss2yH0avGO gNuDzcLqnZbA/WVl+FD5QCfdavInGcUBEFB4eLZBPFJxQO/b4qB0WYroX+S9NM07+VHO3qZah/O2g JI1IZbZA==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtO7-003TyM-73; Mon, 09 Jan 2023 15:44:35 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 17/18] drm/amd/display: decouple steps to reuse in shaper LUT support Date: Mon, 9 Jan 2023 13:38:45 -0100 Message-Id: <20230109143846.1966301-18-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Decouple steps of shaper LUT setup and LUT size validation according to HW caps as a preparation for shaper LUT support. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 0fb1244c8aef..8a930f9bce60 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -497,6 +497,19 @@ static void amdgpu_dm_atomic_lut3d(struct dc_stream_state *stream, stream->lut3d_func = lut; } +static int amdgpu_dm_atomic_shaper_lut(struct dc_stream_state *stream, + struct dc_transfer_func *func_shaper_new) +{ + /* We don't get DRM shaper LUT yet. We assume the input color space is already + * delinearized, so we don't need a shaper LUT and we can just BYPASS + */ + func_shaper_new->type = TF_TYPE_BYPASS; + func_shaper_new->tf = TRANSFER_FUNCTION_LINEAR; + stream->func_shaper = func_shaper_new; + + return 0; +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -519,18 +532,11 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, lut3d_func_new = (struct dc_3dlut *) stream->lut3d_func; func_shaper_new = (struct dc_transfer_func *) stream->func_shaper; - /* We don't get DRM shaper LUT yet. We assume the input color space is - * already delinearized, so we don't need a shaper LUT and we can just - * BYPASS. - */ - func_shaper_new->type = TF_TYPE_BYPASS; - func_shaper_new->tf = TRANSFER_FUNCTION_LINEAR; - stream->func_shaper = func_shaper_new; amdgpu_dm_atomic_lut3d(stream, drm_lut3d, drm_lut3d_size, mode, lut3d_func_new); - return 0; + return amdgpu_dm_atomic_shaper_lut(stream, func_shaper_new); } static const struct drm_mode_lut3d_mode * From patchwork Mon Jan 9 14:38:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13093676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A047EC54EBD for ; Mon, 9 Jan 2023 14:45:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D009B10E4A6; Mon, 9 Jan 2023 14:45:03 +0000 (UTC) Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6D5C010E44A; Mon, 9 Jan 2023 14:44:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=qSDyQmdE5bEHApGBRVBbuA6qGY5F6QCsHw91603xSjI=; b=KMTWCybUZ+YkUUT62lAo6SbkVV 6OHaMQn50EPHQJgSxAqHag3gg0B+/lxw009HeBHyRgzWWXAJhlDtCOsx5EThomWvNX0Wsy5uQDX3h oMdMJMuNCWnU6KfWoDNGnAoU2noWDMybh702kg/8QyLTihZCFgAamCGTd5QybGiamrLGoEaNhWfuX oYk78oRwZj0i9HvLi6at0HFV2NZ0XO1ivQbDYK6K4WmyomusE0J1dPnwfi9Kf19sQQ/MgkqUJrrTQ sLIDtYKMZQTG8wkfVs+S5uAfLR9jRHuDJGL5bD39SbxQLAiUnqsiV5RicGSJ0v7iFSbYxFTzKBp+F NbVewx4A==; Received: from [41.74.137.107] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pEtO9-003TyM-Nv; Mon, 09 Jan 2023 15:44:37 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Subject: [RFC PATCH v2 18/18] drm/amd/display: add user shaper LUT support to amdgpu_dm color pipeline Date: Mon, 9 Jan 2023 13:38:46 -0100 Message-Id: <20230109143846.1966301-19-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, kernel-dev@igalia.com, Shashank Sharma , alex.hung@amd.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Melissa Wen , seanpaul@chromium.org, tzimmermann@suse.de, amd-gfx@lists.freedesktop.org, bhawanpreet.lakha@amd.com, nicholas.kazlauskas@amd.com, Joshua Ashton , sungjoon.kim@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now, we can use shaper LUT to delinearize and/or normalize the color space for a more efficient 3D LUT support (so far, only for DRM atomic color mgmt). If a degamma 1D LUT is passed to linearize the color space, a custom shaper 1D LUT can be used before applying 3D LUT. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 95 ++++++++++++++++--- 1 file changed, 83 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 8a930f9bce60..81b20ac9ff19 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -497,14 +497,62 @@ static void amdgpu_dm_atomic_lut3d(struct dc_stream_state *stream, stream->lut3d_func = lut; } +static int __set_func_shaper(struct dc_transfer_func *shaper_func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma = NULL; + struct calculate_buffer cal_buffer = {0}; + bool res; + + ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); + + cal_buffer.buffer_index = -1; + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, false); + + /* + * Color module doesn't like calculating gamma params + * on top of a linear input. But degamma params can be used + * instead to simulate this. + */ + gamma->type = GAMMA_CUSTOM; + res = mod_color_calculate_degamma_params(NULL, shaper_func, gamma, true); + + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + static int amdgpu_dm_atomic_shaper_lut(struct dc_stream_state *stream, + const struct drm_color_lut *shaper_lut, + uint32_t shaper_size, struct dc_transfer_func *func_shaper_new) { - /* We don't get DRM shaper LUT yet. We assume the input color space is already + /* If no DRM shaper LUT, we assume the input color space is already * delinearized, so we don't need a shaper LUT and we can just BYPASS */ - func_shaper_new->type = TF_TYPE_BYPASS; - func_shaper_new->tf = TRANSFER_FUNCTION_LINEAR; + if (!shaper_size) { + func_shaper_new->type = TF_TYPE_BYPASS; + func_shaper_new->tf = TRANSFER_FUNCTION_LINEAR; + } else { + int r; + + /* If DRM shaper LUT is set, we assume a linear color space + * (linearized by DRM degamma 1D LUT or not) + */ + func_shaper_new->type = TF_TYPE_DISTRIBUTED_POINTS; + func_shaper_new->tf = TRANSFER_FUNCTION_LINEAR; + + r = __set_func_shaper(func_shaper_new, shaper_lut, shaper_size); + if (r) + return r; + } + stream->func_shaper = func_shaper_new; return 0; @@ -514,6 +562,8 @@ static int amdgpu_dm_atomic_shaper_lut(struct dc_stream_state *stream, * interface * @dc: Display Core control structure * @stream: DC stream state to set shaper LUT and 3D LUT + * @drm_shaper_lut: DRM CRTC (user) shaper LUT + * @drm_shaper_size: size of shaper LUT * @drm_lut3d: DRM CRTC (user) 3D LUT * @drm_lut3d_size: size of 3D LUT * @@ -522,6 +572,8 @@ static int amdgpu_dm_atomic_shaper_lut(struct dc_stream_state *stream, */ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, struct dc_stream_state *stream, + const struct drm_color_lut *drm_shaper_lut, + uint32_t drm_shaper_size, const struct drm_color_lut *drm_lut3d, uint32_t drm_lut3d_size, const struct drm_mode_lut3d_mode *mode) @@ -532,11 +584,11 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, lut3d_func_new = (struct dc_3dlut *) stream->lut3d_func; func_shaper_new = (struct dc_transfer_func *) stream->func_shaper; - amdgpu_dm_atomic_lut3d(stream, drm_lut3d, drm_lut3d_size, mode, lut3d_func_new); - return amdgpu_dm_atomic_shaper_lut(stream, func_shaper_new); + return amdgpu_dm_atomic_shaper_lut(stream, drm_shaper_lut, + drm_shaper_size, func_shaper_new); } static const struct drm_mode_lut3d_mode * @@ -569,13 +621,23 @@ get_lut3d_mode(struct amdgpu_device *adev, int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, const struct drm_crtc_state *crtc_state) { - const struct drm_color_lut *lut3d = NULL; + const struct drm_color_lut *shaper = NULL, *lut3d = NULL; const struct drm_mode_lut3d_mode *mode; uint32_t exp_size, size; + /* shaper LUT is only available if 3D LUT color caps*/ + exp_size = has_mpc_lut3d_caps(&adev->dm) ? MAX_COLOR_LUT_ENTRIES : 0; + shaper = __extract_blob_lut(crtc_state->shaper_lut, &size); + + if (shaper && size != exp_size) { + DRM_DEBUG_DRIVER( + "Invalid Shaper LUT size. Should be %u but got %u.\n", + exp_size, size); + return -EINVAL; + } + mode = get_lut3d_mode(adev, crtc_state); exp_size = mode ? mode->lut_size * mode->lut_size * mode->lut_size : 0; - lut3d = __extract_blob_lut(crtc_state->lut3d, &size); if (lut3d && size != exp_size) { @@ -617,11 +679,11 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) bool has_rom = adev->asic_type <= CHIP_RAVEN; struct drm_color_ctm *ctm = NULL; const struct drm_color_lut *degamma_lut, *regamma_lut; - const struct drm_color_lut *lut3d; + const struct drm_color_lut *shaper_lut, *lut3d; uint32_t degamma_size, regamma_size; - uint32_t lut3d_size; + uint32_t lut3d_size, shaper_size; bool has_regamma, has_degamma; - bool has_lut3d; + bool has_lut3d, has_shaper_lut; bool is_legacy; int r; @@ -634,12 +696,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) return r; degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); + shaper_lut = __extract_blob_lut(crtc->base.shaper_lut, &shaper_size); lut3d = __extract_blob_lut(crtc->base.lut3d, &lut3d_size); regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); has_degamma = degamma_lut && !__is_lut_linear(degamma_lut, degamma_size); + has_shaper_lut = shaper_lut != NULL; has_lut3d = lut3d != NULL; has_regamma = @@ -680,10 +744,17 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) return r; } else { if (has_lut3d) { - r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, stream, lut3d, lut3d_size, + /* enable 3D LUT only for DRM atomic color mgmt */ + shaper_size = has_shaper_lut ? shaper_size : 0; + + r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, stream, + shaper_lut, shaper_size, + lut3d, lut3d_size, get_lut3d_mode(adev, &crtc->base)); - if (r) + if (r) { + DRM_DEBUG_DRIVER("Failed to set shaper and 3D LUT\n"); return r; + } } /* Note: OGAM is disabled if 3D LUT is successfully programmed. * See params and set_output_gamma in