From patchwork Mon Jan 9 18:26:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13094104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80606C54EBD for ; Mon, 9 Jan 2023 18:41:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:Cc:To:Subject: Message-ID:Date:From:MIME-Version:Reply-To:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=mcw6TST58e8Q0uX2FzOQBem/d4q8P5QHY7UX1B18UwA=; b=lhx1drN1Aifk29KRwUqLjbWkMv dA0c3ISWjF36ffhDPUkhR0lnN9LQxCXEzuXQBHEyhFnMgeeBm0iSDUp2L6KLAjP6S7lM0fLUxP+hM THYBjgn88kUJkUPkJ7xJqsP3qT3Vqw4vDm8eHaq8u+CQvnA5mTpRAKWVFBLnUQJgz3lUaaFgUAdA6 I6zDXGhPk9s1IWkM5sjKyA/v6M7gcbIiutALnKbIAXvqC6eaypOXXUuqrwmNApgCe8ICVE4cQBjz4 11fTnxKDgxE3111kExQ6AXTrzYS3ZAjx701wDTwPqIJJbbglo39WIQIcNh3n2VrVTkcTdMpKRuBxe oORgRIZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pEx4w-003NFq-2T; Mon, 09 Jan 2023 18:41:02 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pEwqv-003GwD-8y for linux-mediatek@lists.infradead.org; Mon, 09 Jan 2023 18:26:39 +0000 Received: by mail-pj1-x1029.google.com with SMTP id z4-20020a17090a170400b00226d331390cso10589597pjd.5 for ; Mon, 09 Jan 2023 10:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=mcw6TST58e8Q0uX2FzOQBem/d4q8P5QHY7UX1B18UwA=; b=PDpK/5o6LQb6tGxUuuzLarQFE5Avm1G7pdkXRnv3WVdrNO1mzU77JBhHe7FlekMFI0 apXnVpw+Zj+dHNUJYshbu1yOPI69RWkCzhziRmdlofm9Z58V/s6eWEPGo/8Xtn2zvNiC twJgrjHQGqiEeSXlAKae6YJlZ+195u8CU1h+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=mcw6TST58e8Q0uX2FzOQBem/d4q8P5QHY7UX1B18UwA=; b=h2lAPpFtC7J6L6uvWW8kbbF19ZXAZTLF2nOJHtry6W5mukOWoH4AIqYWERdVsD4yAs DBbheaJc0z7PhbLyclpu76jY2KKhLbY2R78+uf/JIglVG8rqpygzP7cohrsvyz7TcVOI XILiZPCKkDDqlShtCgvBMwvrbTrsfT/ZSUdPm8/YB4GR7rTIqihqdHEFvYvm/MUQpV/B +xrmZUjavotaBYhsBx2HqQhinRLDW66Icz3D2mNqYdF0z1o1uzjFjtdLM8A7q2fHGDCn YhxAyiNDEfTUruft3xYGwxu2R4DTkUfQKLM0zqLX2l2FdHqWBVUWk3kganKIN41Tzvi6 VVlg== X-Gm-Message-State: AFqh2kpvLs8OeKJ6k2zVDh8JEv7smimkgBO4Oe6FZVVxXSi04BbzHnXe PaqtUfRhA5bsHIfH6gAxeB5IM9vFaupT1dPwo4T6446AzxK8tnWv X-Google-Smtp-Source: AMrXdXs+felrXn71fDQFUAwQfKnX/2KTbDbWSMzFuSrTO/C5+epcXgDL/JBzogwsfdEgh1GHupmnDQ0/7vM2CglPvro= X-Received: by 2002:a17:902:cf0f:b0:193:373e:513e with SMTP id i15-20020a170902cf0f00b00193373e513emr247496plg.23.1673288784142; Mon, 09 Jan 2023 10:26:24 -0800 (PST) MIME-Version: 1.0 From: Justin Green Date: Mon, 9 Jan 2023 13:26:13 -0500 Message-ID: Subject: [RESEND PATCH] drm/mediatek: Add support for AR30 and BA30 To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: AngeloGioacchino Del Regno , jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, Chen-Yu Tsai , Chun-Kuang Hu , p.zabel@pengutronix.de, airlied@linux.ie, matthias.bgg@gmail.com, daniel@ffwll.ch, Daniel Stone , Justin Green X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230109_102634_120610_C3DADB7F X-CRM114-Status: GOOD ( 16.07 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver. Tested using "modetest -P" on an MT8195. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 29 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +++++++++++- drivers/gpu/drm/mediatek/mtk_drm_plane.c | 38 ++++++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 +- 4 files changed, 81 insertions(+), 7 deletions(-) -- 2.38.1.431.g37b22c650d-goog diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 002b0f6cae1a..be1dfc82aab2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -38,6 +38,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) @@ -56,6 +57,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -175,6 +180,26 @@ void mtk_ovl_stop(struct device *dev) } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -289,9 +314,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -346,6 +373,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ADDR(ovl, idx)); + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); + mtk_ovl_layer_on(dev, idx, cmdq_pkt); } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 42cc7052b050..b2b944344c7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -843,6 +843,21 @@ enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, } +static const char *ovls_with_10bit_cap[] = { + "mediatek,mt8195-disp-ovl", +}; + +static bool is_10bit_cap_device(void) +{ + for (int i = 0; i < ARRAY_SIZE(ovls_with_10bit_cap); i++) { + if (of_find_compatible_node(NULL, NULL, + ovls_with_10bit_cap[i])) + return true; + } + + return false; +} + static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, struct mtk_drm_crtc *mtk_crtc, int comp_idx, int pipe) @@ -850,6 +865,7 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; int i, ret; + bool supports_10bit = is_10bit_cap_device(); for (i = 0; i < num_planes; i++) { ret = mtk_plane_init(drm_dev, @@ -857,7 +873,8 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, BIT(pipe), mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, num_planes), - mtk_ddp_comp_supported_rotations(comp)); + mtk_ddp_comp_supported_rotations(comp), + supports_10bit); if (ret) return ret; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index 5c0d9ce69931..2726344b5696 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -19,7 +20,7 @@ #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" -static const u32 formats[] = { +static const u32 default_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_BGRX8888, @@ -33,6 +34,22 @@ static const u32 formats[] = { DRM_FORMAT_YUYV, }; +static const u32 formats_with_10bit_cap[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + static void mtk_plane_reset(struct drm_plane *plane) { struct mtk_plane_state *state; @@ -248,13 +265,24 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations) + unsigned int supported_rotations, bool supports_10bit) { int err; - err = drm_universal_plane_init(dev, plane, possible_crtcs, - &mtk_plane_funcs, formats, - ARRAY_SIZE(formats), NULL, type, NULL); + if (supports_10bit) { + err = drm_universal_plane_init(dev, plane, possible_crtcs, + &mtk_plane_funcs, + formats_with_10bit_cap, + ARRAY_SIZE(formats_with_10bit_cap), + NULL, type, NULL); + } else { + err = drm_universal_plane_init(dev, plane, possible_crtcs, + &mtk_plane_funcs, + default_formats, + ARRAY_SIZE(default_formats), + NULL, type, NULL); + } + if (err) { DRM_ERROR("failed to initialize plane\n"); return err; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 2d5ec66e3df1..49737153f0a6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -40,6 +40,6 @@ to_mtk_plane_state(struct drm_plane_state *state) int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations); + unsigned int supported_rotations, bool supports_10bit); #endif