From patchwork Tue Jan 10 18:58:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 13095541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE36EC678DA for ; Tue, 10 Jan 2023 18:59:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239544AbjAJS7P (ORCPT ); Tue, 10 Jan 2023 13:59:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239781AbjAJS6g (ORCPT ); Tue, 10 Jan 2023 13:58:36 -0500 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAECC5F44 for ; Tue, 10 Jan 2023 10:58:28 -0800 (PST) Received: by mail-pf1-x449.google.com with SMTP id b13-20020a056a000a8d00b0057348c50123so5618082pfl.18 for ; Tue, 10 Jan 2023 10:58:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=aZj5nkPmUZ/+3WFmXIOMi6myvBqiEyZ2i8jBeyd2yO4=; b=kNaE2hOuqT1CeKskGFJKoOqj1OzySQvfQXderb/BCwvvYx5sqali1h75XgPDEKkhUn VIT5fTYFceymj4MKly4dsmGYvDWMP8DpxCmir5/1KFrjl5S/fR0WTxv9jfUF+acTIsNv ui49EcL2pMQodBk+nFC4Q3oGR//qesADTZKOUHNq5sKuEFL55iNAMpbVIj25BCy+XAr+ HoVRJR/O1nOBZhHQZbbL9+Cz0f52tZQIgSqWtmjeT4AavJb7pCjzOUo8bUIOktA2HDpu 9SAcCVSZBoVGOcHUMOwpS8hmbKGUgVjMNMFOg2O/zaSSiUG1MbimdKOOqUyOlHXCRVhJ 5hDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=aZj5nkPmUZ/+3WFmXIOMi6myvBqiEyZ2i8jBeyd2yO4=; b=VFo2v8UhSZUYNGkTMMe1Pa0wcqtm1xFKdap6CYCspLf2XLDLOS/Bxk0SM3vuxw1aZj 12MRe0K26w9GK9AcxdfD3xOg3RhZqF9DyDZYYE+75Pj3Z4esMEWRm7HOgznS9vtZ+pNT mAXP5PVd3TIfid2uiVfJpA9cIY3APx9WKAGS7ZKdDxeZa90Xgc65ig2bOtXIcBx9wAQq kKbGs6fZNfW9T8eZoBuukE58p29CmsbN713hI1yWDZvOuyVyTmWZibF95V2VTYF0Ocql 98DhY/d6424D6CqlVkpPCnc+RnZXTbLA29VKaEj3JlOKTktYy2svaCjDmQ6+IR8a2SQu 8hHw== X-Gm-Message-State: AFqh2krhsGAYjZP8aKezs5WqkoDpPeK0yYePRGtfnoQD33iyop2AbiOi P0dsaQkwbIKS+9qi0cKX+UGLCzJ3JiV1qdNoI6Yd5fB68f8zLpKPtaS0YQJDLlWpy98cR3ltpSS ++B0lp4wPC29BXeNyrcfCcop4sNo/NX82hr1GIOIKtFDijGOyuaOm9D6SPt6I X-Google-Smtp-Source: AMrXdXvyoUSwXlUO5pXnq5Ua+mF8JjUX4N0DGfLpaVZ4To5sCi/zqM0lnsKKgUwndriaRWcXrSpxR4UeBkn8 X-Received: from mizhang-super.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1071]) (user=mizhang job=sendgmr) by 2002:a17:902:e045:b0:193:1c8f:1835 with SMTP id x5-20020a170902e04500b001931c8f1835mr899892plx.62.1673377108205; Tue, 10 Jan 2023 10:58:28 -0800 (PST) Reply-To: Mingwei Zhang Date: Tue, 10 Jan 2023 18:58:20 +0000 In-Reply-To: <20230110185823.1856951-1-mizhang@google.com> Mime-Version: 1.0 References: <20230110185823.1856951-1-mizhang@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230110185823.1856951-2-mizhang@google.com> Subject: [PATCH 1/4] KVM: selftests: x86: Fix an error in comment of amx_test From: Mingwei Zhang To: kvm@vger.kernel.org Cc: linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Venkatesh Srinivas , Aaron Lewis , Mingwei Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org After the execution of __tilerelease(), AMX component will be in INIT state. Therefore, execution of xsavec saving the AMX state into memory will cause the XSTATE_BV[18] cleared in xheader. However, the XCOMP_BV[18] will remain set. Fix the error in comment. Cc: Jim Mattson Cc: Venkatesh Srinivas Cc: Aaron Lewis Signed-off-by: Mingwei Zhang --- tools/testing/selftests/kvm/x86_64/amx_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c index bd72c6eb3b67..16533949a189 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -204,7 +204,7 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg, GUEST_SYNC(4); __tilerelease(); GUEST_SYNC(5); - /* bit 18 not in the XCOMP_BV after xsavec() */ + /* bit 18 not in the XSTATE_BV after xsavec() */ set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA); __xsavec(xsave_data, XFEATURE_MASK_XTILEDATA); GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0); From patchwork Tue Jan 10 18:58:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 13095538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 033DBC677F1 for ; Tue, 10 Jan 2023 18:59:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235339AbjAJS7J (ORCPT ); Tue, 10 Jan 2023 13:59:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234968AbjAJS6h (ORCPT ); Tue, 10 Jan 2023 13:58:37 -0500 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 683016322 for ; Tue, 10 Jan 2023 10:58:30 -0800 (PST) Received: by mail-pl1-x649.google.com with SMTP id f8-20020a170902ce8800b00190c6518e21so8915539plg.1 for ; Tue, 10 Jan 2023 10:58:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=3Kllhy+XCjHqoEtvfgHpVkDHrVNguIhBfnG2gA6pKcs=; b=bePXYChwkQOZNK0AQ+5TcDEnhI5FHwYYdzXTv5PELbTA80AbZGfbPgADOF0yr/OMjf H3g5h1RaztZ1SlWgdgAs1x/EmvJ819PgotnllZnKdfYLCGBhMh9MhVSQyBQCTypSE2tR aV7mM1Zi3YO6IXtApA1uq2WW3PEfDn0U9AllV0N4aTqcRUsMZEC1MWVCSZqWJ8QOoOO+ PvItS+Cwhm24ba4DROZfoWv2w924oEmPULO2nDFF1vok3QsdEMF5yPTD4JopsLWWA7Kq Rs/1aqJf1oac3hB/X/0kOTngPb97uywso+p8Qat27rZAgf4+9S2HaArrSz0cF1PRKGCm l1bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3Kllhy+XCjHqoEtvfgHpVkDHrVNguIhBfnG2gA6pKcs=; b=LuB83Jou5eHGE+U9rrIG4z13uVQmczaGn5qk8A6jYpWhu6cI8A4fZzu9ARQfkKC+Nw H0RKPWBLmkTPpzJUpCO0nyTA+K4m9iJK6Q30rmSx6DNF+d24zsP05E2Id+13QZf41xl8 gLgJimYhD80KmTHUb5wO8bJTK3Bb6suKi0oRJKHs8zTC2WY+Q7ymeiRWn7b61vMfm8z5 i+jRG9q6775XRlVSQpqetBJpsBgrnPJjzyFQEwYnt5Fo1iy82nnBAgODB0eg/l//roi8 JetAyHpKUHWs5ypjaIPFsqMrE9wj07/tfHSSEJgnEtl3tkrNVNkrv4rO2Y8YB8gEezUG GJ5w== X-Gm-Message-State: AFqh2kpPsG/2xpfbkJBJebqQ0jBrRUlfHO0xpC/Oaov9ofTDDpxt98KQ RY3cgdazYeYBgvanGSueYQLgR/siLuBt1n1xX1VVZwMA7AE0p7aZ7TOTIHvMT901CGvrRNsXRaD 1EDM/Wej7YIR0YNcctSxj4uQ3TeOi7D3si0peeVhBzGWqCfFIL7fIUZfOUPAb X-Google-Smtp-Source: AMrXdXveAeZkWD48dEoeZW9phbriGh3x782ZfSYB3GzyNWru3H6hHA3HPgQplWv8D1OkeYRKd2NNsqJ/+O1f X-Received: from mizhang-super.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1071]) (user=mizhang job=sendgmr) by 2002:a17:902:ef95:b0:192:97d1:a4d8 with SMTP id iz21-20020a170902ef9500b0019297d1a4d8mr3704144plb.74.1673377109836; Tue, 10 Jan 2023 10:58:29 -0800 (PST) Reply-To: Mingwei Zhang Date: Tue, 10 Jan 2023 18:58:21 +0000 In-Reply-To: <20230110185823.1856951-1-mizhang@google.com> Mime-Version: 1.0 References: <20230110185823.1856951-1-mizhang@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230110185823.1856951-3-mizhang@google.com> Subject: [PATCH 2/4] KVM: selftests: x86: Add check of IA32_XFD in amx_test From: Mingwei Zhang To: kvm@vger.kernel.org Cc: linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Venkatesh Srinivas , Aaron Lewis , Mingwei Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When #NM is triggered, the handler needs to ensure the exception is triggered by AMX by checking IA32_XFD_ERR and not because of CR0.TS[bit 3] is 1. Note that the value of IA32_XFD_ERR comes from "the logical AND of the IA32_XFD MSR and the bitmap corresponding to the state components required by the faulting instruction." (Intel SDM vol 1. Section 13.14) Add the missing check of CR0.TS before checking the value of IA32_XFD_ERR. In addition, add an extra check to IA32_XFD to ensure the behavior is consistent with the AMX archtecture. In addition, repeat the checks across context switch to ensure the values of IA32_XFD and IA32_XFD_ERR are well preserved. Signed-off-by: Mingwei Zhang --- tools/testing/selftests/kvm/x86_64/amx_test.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c index 16533949a189..b2369f956fea 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -226,9 +226,12 @@ void guest_nm_handler(struct ex_regs *regs) { /* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */ GUEST_SYNC(7); + GUEST_ASSERT((get_cr0() & X86_CR0_TS) == 0); GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT((rdmsr(MSR_IA32_XFD) & XFEATURE_MASK_XTILEDATA) == XFEATURE_MASK_XTILEDATA); GUEST_SYNC(8); GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT((rdmsr(MSR_IA32_XFD) & XFEATURE_MASK_XTILEDATA) == XFEATURE_MASK_XTILEDATA); /* Clear xfd_err */ wrmsr(MSR_IA32_XFD_ERR, 0); /* xfd=0, enable amx */ From patchwork Tue Jan 10 18:58:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 13095539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 565DEC678D7 for ; Tue, 10 Jan 2023 18:59:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239082AbjAJS7L (ORCPT ); Tue, 10 Jan 2023 13:59:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239785AbjAJS6i (ORCPT ); Tue, 10 Jan 2023 13:58:38 -0500 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B54219010 for ; Tue, 10 Jan 2023 10:58:32 -0800 (PST) Received: by mail-pg1-x54a.google.com with SMTP id 23-20020a630017000000b0048d84f2cbbeso5531788pga.9 for ; Tue, 10 Jan 2023 10:58:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=upUt0tkjVVo5kujG2THDyS9VuwSTirZ5ySsbyf+a2Vk=; b=TDmjeQs1Nx35Pnj9WFsSWVj6CGe4OuCAxxe9Uj2I0XxxteOWSUQ6lF/oPghE4q3D1E zLr973gqSe9z0IT9vS+MLR6tJHwSAReg7cX1R0FW9HzOmYqWOnnKZyG9AahfgNdgDw6S h6hq8qaNf1+r6Cr1qpROqlUJvqnhKvoWtp2O3jC9HoSUkRA/6IS0v1JCetsS+LSO2RRE M+8g4WfEY2Wp+9GCiMMWfWpZ5CNkBnaXtCVGULRsRLZg9MguZNelTRpUpFVODgGVBEG/ sxSvq2ZKnVgjntV7aDOe7nBsabkzLnN/4K7FYwOozz3+oGwXJgovNqB8/VtqFEGS7KTM ZZ2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=upUt0tkjVVo5kujG2THDyS9VuwSTirZ5ySsbyf+a2Vk=; b=Ws2zGKFr0vhBwpt+Jgg9FMZYAR8kXvYdId9vCO2ujkPLXV5Z4R7/e9iuePtXcmsVzt T8qUZFWDYlEbHNCZprYJH8ZAcZAbqGiK2IL62WQERcb0ADd15Os5dYG8YDvdto0OCXpe Qg1x8dqaceSLBHxKA9So5H4fNQtujOOF/J/XSoczdGKoZnlYAsooHihiTUy4Zz0HXzmy 64a4MwRdaYybXbnmTbqdvZaeeM98o4MvBe8KEKIcN8keb+9TRdR2Kt2O7+rX4yAllSzg iNqc8PMfTgGmE22WDSp4hJnRjPOLAxNzQqk0A+P6PAVoFHJ2iyvGwdcBFvXYHJ7kJyLb pPSQ== X-Gm-Message-State: AFqh2kq6yMrrCw4teemSP7dvUiEQlycPcT2ylbpoqBW9+wcOlTTzhvyJ d2YR37tUL261BiHEVlA1AeoXREFM48xSDar/FwqaTMaUnYCkJ28IUX+IvsdFEtvM7S0O5K8SvNA DImRIo7keppDKxIfdD3zUC0c8mD6/hkgfKUeL8hEmkbo3r7R6viEadIOP7qBp X-Google-Smtp-Source: AMrXdXu1jQvfizmHt7HFd3EUElImxYYeXPAtpgr6GxJXnxViMI1A72B4Pd96A1woQGVdxKuC1tSbqdNthWJP X-Received: from mizhang-super.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1071]) (user=mizhang job=sendgmr) by 2002:a17:90a:d350:b0:223:fa07:7bfb with SMTP id i16-20020a17090ad35000b00223fa077bfbmr5690650pjx.38.1673377111533; Tue, 10 Jan 2023 10:58:31 -0800 (PST) Reply-To: Mingwei Zhang Date: Tue, 10 Jan 2023 18:58:22 +0000 In-Reply-To: <20230110185823.1856951-1-mizhang@google.com> Mime-Version: 1.0 References: <20230110185823.1856951-1-mizhang@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230110185823.1856951-4-mizhang@google.com> Subject: [PATCH 3/4] KVM: selftests: x86: Enable checking on xcomp_bv in amx_test From: Mingwei Zhang To: kvm@vger.kernel.org Cc: linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Venkatesh Srinivas , Aaron Lewis , Mingwei Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org After tilerelease instruction, AMX tiles are in INIT state. According to Intel SDM vol 1. 13.10: "If RFBM[i] = 1, XSTATE_BV[i] is set to the value of XINUSE[i].", XSTATE_BV[18] should be cleared after xsavec. On the other hand, according to Intel SDM vol 1. 13.4.3: "If XCOMP_BV[i] = 1, state component i is located at a byte offset locationI from the base address of the XSAVE area". Since at the time of xsavec, XCR0[18] is set indicating AMX tile data component is still enabled, xcomp_bv[18] should be set. Complete the checks by adding the assert to xcomp_bv[18] after xsavec. Signed-off-by: Mingwei Zhang --- tools/testing/selftests/kvm/x86_64/amx_test.c | 30 +++++++++++++++++-- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c index b2369f956fea..18203e399e9d 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -41,6 +41,12 @@ #define XSAVE_HDR_OFFSET 512 +struct xstate_header { + u64 xfeatures; + u64 xcomp_bv; + u64 reserved[6]; +} __packed; + struct xsave_data { u8 area[XSAVE_SIZE]; } __aligned(64); @@ -160,12 +166,26 @@ static void set_tilecfg(struct tile_config *cfg) static void set_xstatebv(void *data, uint64_t bv) { - *(uint64_t *)(data + XSAVE_HDR_OFFSET) = bv; + struct xstate_header *header = + (struct xstate_header *)(data + XSAVE_HDR_OFFSET); + + header->xfeatures = bv; } static u64 get_xstatebv(void *data) { - return *(u64 *)(data + XSAVE_HDR_OFFSET); + struct xstate_header *header = + (struct xstate_header *)(data + XSAVE_HDR_OFFSET); + + return header->xfeatures; +} + +static u64 get_xcompbv(void *data) +{ + struct xstate_header *header = + (struct xstate_header *)(data + XSAVE_HDR_OFFSET); + + return header->xcomp_bv; } static void init_regs(void) @@ -204,10 +224,14 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg, GUEST_SYNC(4); __tilerelease(); GUEST_SYNC(5); - /* bit 18 not in the XSTATE_BV after xsavec() */ + /* + * After xsavec() bit 18 is cleared in the XSTATE_BV but is set in + * the XCOMP_BV. + */ set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA); __xsavec(xsave_data, XFEATURE_MASK_XTILEDATA); GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0); + GUEST_ASSERT((get_xcompbv(xsave_data) & XFEATURE_MASK_XTILEDATA) == XFEATURE_MASK_XTILEDATA); /* xfd=0x40000, disable amx tiledata */ wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA); From patchwork Tue Jan 10 18:58:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 13095542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E57EC54EBE for ; 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Tue, 10 Jan 2023 10:58:33 -0800 (PST) Reply-To: Mingwei Zhang Date: Tue, 10 Jan 2023 18:58:23 +0000 In-Reply-To: <20230110185823.1856951-1-mizhang@google.com> Mime-Version: 1.0 References: <20230110185823.1856951-1-mizhang@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230110185823.1856951-5-mizhang@google.com> Subject: [PATCH 4/4] KVM: selftests: x86: Repeat the checking of xheader when IA32_XFD[18] is set in amx_test From: Mingwei Zhang To: kvm@vger.kernel.org Cc: linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Venkatesh Srinivas , Aaron Lewis , Mingwei Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Repeat the checking of AMX component in xheader after xsavec when IA32_XFD[18] is set. This check calibrates the functionality scope of IA32_XFD: it does not intercept the XSAVE state management. Regardless of the values in IA32_XFD, AMX component state will still be managed by XSAVE* and XRSTOR* as long as XCR[18:17] are set. Signed-off-by: Mingwei Zhang --- tools/testing/selftests/kvm/x86_64/amx_test.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c index 18203e399e9d..9a80a59b64e6 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -235,6 +235,16 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg, /* xfd=0x40000, disable amx tiledata */ wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA); + + /* + * Bit 18 is cleared in XSTATE_BV but set in XCOMP_BV, this property + * remains the same even when IA32_XFD disables amx tiledata. + */ + set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA); + __xsavec(xsave_data, XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0); + GUEST_ASSERT((get_xcompbv(xsave_data) & XFEATURE_MASK_XTILEDATA) == XFEATURE_MASK_XTILEDATA); + GUEST_SYNC(6); GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA); set_tilecfg(amx_cfg);