From patchwork Wed Jan 11 00:56:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08A76C54EBC for ; Wed, 11 Jan 2023 00:56:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0745210E06D; Wed, 11 Jan 2023 00:56:52 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B554210E06D; Wed, 11 Jan 2023 00:56:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673398610; x=1704934610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z9jY9ApRJfNRepgkR3ECDh+4/H9mgg6PKxpblab1qks=; b=belTuWwUJIDP3XbNtDOwe8YG5ZyvOhFxiBm7Sn6p9CdsRqopnhVNO/gv kkfhihrBzhDmyXWIrXJGm5AccYt/MtqWVUi8RSImRvetepmSexXFYyGRg YDntGVOystvGHmGGGOv8GxMTqNIGkG3jcGZ/Hl2G6WDW36w4XeWMOqtjE NdkS6OqvYz9qyj9U2laR0TyyEjxCp1YEGe5jcovpdFlp77VdC0c8sfaG9 jlqSWIf3l7ArQgmsPLyhbvdjuWM3kgFeJputLsAub6PHif7+IY+2yO9KP jKsROgA1O3nEJB44FsYgzBhSnpCzO4ner5/RcC0mcyvBNgN1ppb6e9y4E Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="325307078" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307078" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175638" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175638" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:50 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/9] drm/i915/pxp: Add MTL PXP GSC-CS back-end skeleton Date: Tue, 10 Jan 2023 16:56:31 -0800 Message-Id: <20230111005642.300761-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MTL PXP GSC-CS back-end stub functions hook them up from PXP front-end and PXP session management functions. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 19 +++++++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 23 ++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h | 18 +++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 ++++- drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 +++++ 6 files changed, 69 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f47f00b162a4..eae4325310e8 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -330,6 +330,7 @@ i915-y += \ i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp_cmd.o \ pxp/intel_pxp_debugfs.o \ + pxp/intel_pxp_gsccs.o \ pxp/intel_pxp_irq.o \ pxp/intel_pxp_pm.o \ pxp/intel_pxp_session.o diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index cfc9af8b3d21..be52bf92e847 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "intel_pxp.h" +#include "intel_pxp_gsccs.h" #include "intel_pxp_irq.h" #include "intel_pxp_session.h" #include "intel_pxp_tee.h" @@ -132,7 +133,10 @@ static void pxp_init_full(struct intel_pxp *pxp) if (ret) return; - ret = intel_pxp_tee_component_init(pxp); + if (pxp->uses_gsccs) + ret = intel_pxp_gsccs_init(pxp); + else + ret = intel_pxp_tee_component_init(pxp); if (ret) goto out_context; @@ -157,6 +161,11 @@ static struct intel_gt *find_gt_for_required_teelink(struct drm_i915_private *i9 return NULL; } +static bool pxp_has_gsccs(struct drm_i915_private *i915) +{ + return (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0)); +} + static struct intel_gt *find_gt_for_required_protected_content(struct drm_i915_private *i915) { if (!IS_ENABLED(CONFIG_DRM_I915_PXP) || !INTEL_INFO(i915)->has_pxp) @@ -167,7 +176,7 @@ static struct intel_gt *find_gt_for_required_protected_content(struct drm_i915_p * on the media GT. NOTE: if we have a media-tile with a GSC-engine, * the VDBOX is already present so skip that check */ - if (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0)) + if (pxp_has_gsccs(i915)) return i915->media_gt; /* @@ -208,6 +217,7 @@ int intel_pxp_init(struct drm_i915_private *i915) return -ENOMEM; i915->pxp->ctrl_gt = gt; + i915->pxp->uses_gsccs = pxp_has_gsccs(i915); /* * If full PXP feature is not available but HuC is loaded by GSC on pre-MTL @@ -229,7 +239,10 @@ void intel_pxp_fini(struct drm_i915_private *i915) i915->pxp->arb_is_valid = false; - intel_pxp_tee_component_fini(i915->pxp); + if (i915->pxp->uses_gsccs) + intel_pxp_gsccs_fini(i915->pxp); + else + intel_pxp_tee_component_fini(i915->pxp); destroy_vcs_context(i915->pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c new file mode 100644 index 000000000000..21400650fc86 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2023 Intel Corporation. + */ + +#include "i915_drv.h" +#include "intel_pxp_types.h" +#include "intel_pxp_gsccs.h" + +int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, + int arb_session_id) +{ + return -ENODEV; +} + +void intel_pxp_gsccs_fini(struct intel_pxp *pxp) +{ +} + +int intel_pxp_gsccs_init(struct intel_pxp *pxp) +{ + return 0; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h new file mode 100644 index 000000000000..967f8fc3b5b5 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2022, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_GSCCS_H__ +#define __INTEL_PXP_GSCCS_H__ + +#include + +struct intel_pxp; + +int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, + int arb_session_id); +void intel_pxp_gsccs_fini(struct intel_pxp *pxp); +int intel_pxp_gsccs_init(struct intel_pxp *pxp); + +#endif /*__INTEL_PXP_GSCCS_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c index ae413580b81a..080aa2209c5b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -7,6 +7,7 @@ #include "intel_pxp.h" #include "intel_pxp_cmd.h" +#include "intel_pxp_gsccs.h" #include "intel_pxp_session.h" #include "intel_pxp_tee.h" #include "intel_pxp_types.h" @@ -66,7 +67,10 @@ static int pxp_create_arb_session(struct intel_pxp *pxp) return -EEXIST; } - ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION); + if (pxp->uses_gsccs) + ret = intel_pxp_gsccs_create_session(pxp, ARB_SESSION); + else + ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION); if (ret) { drm_err(>->i915->drm, "tee cmd for arb session creation failed\n"); return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index 7dc5f08d1583..43aa61c26de5 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -26,6 +26,12 @@ struct intel_pxp { */ struct intel_gt *ctrl_gt; + /** + * @uses_gsccs: PXP interface for firmware access and pxp-session controls is + * via the GSC-CS engine. This is for MTL+ platforms. + */ + bool uses_gsccs; + /** * @pxp_component: i915_pxp_component struct of the bound mei_pxp * module. Only set and cleared inside component bind/unbind functions, From patchwork Wed Jan 11 00:56:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DFB3C54EBC for ; Wed, 11 Jan 2023 00:57:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA01910E6AE; Wed, 11 Jan 2023 00:56:55 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 249F310E065; Wed, 11 Jan 2023 00:56:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673398611; x=1704934611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=99LwWWbj9sGrCwj1kyX+9Bhw14fR1D48Erpg2TgfQyc=; b=dVeY1wEGhxwsfBnwxZ+rLz8qmglKWbCHy5aSMRCaEjI5iIXmhy8QcDS7 tpNUaBcgP3ppcJ20OPEZA39uKu0m5sLQ+uYWChlm9R12mDqTT0AgxId5W TuKysTLWSPr3sUEQWAIkIXVrxmPbcQB99n8OizzOvjuF85g1fzVhPCj0h HW34eac1ooXF0T1mzEupzUQnErUzP9GZXd+qG+YMzsZEnwWIdFzooJhQH iNq/HaDIeEeAV96XtKlxQCcI02a0pP6HyBYIZ41LH6/+fqQEYQFfYdVWG AhdlAzlYCQpUHc2Kgc65LzoVXO4oHBua67n2h/O0aatt+yE8s9iYlzcs7 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="325307080" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307080" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175642" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175642" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:50 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/9] drm/i915/pxp: Add GSC-CS back-end resource init and cleanup Date: Tue, 10 Jan 2023 16:56:32 -0800 Message-Id: <20230111005642.300761-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For MTL, PXP transport back-end uses the GSC engine to submit HECI packets for PXP arb session management. The command submission that uses non-priveleged mode requires us to allocate (or free) a set of execution submission resources (buffer-object, batch-buffer and context). Thus, do this one time allocation of resources in GSC-CS init and clean them up in fini. Signed-off-by: Alan Previn --- .../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 6 +- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 216 +++++++++++++++++- drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 + 3 files changed, 225 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index ad67e3f49c20..52b9a61bcdd4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -10,7 +10,11 @@ #include "intel_pxp_cmd_interface_cmn.h" /* PXP-Cmd-Op definitions */ -#define PXP43_CMDID_START_HUC_AUTH 0x0000003A +#define PXP43_CMDID_START_HUC_AUTH 0x0000003A + +/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */ +#define PXP43_MAX_HECI_IN_SIZE (SZ_32K) +#define PXP43_MAX_HECI_OUT_SIZE (SZ_32K) /* PXP-Input-Packet: HUC-Authentication */ struct pxp43_start_huc_auth_in { diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c index 21400650fc86..97ca187e6fde 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c @@ -3,9 +3,41 @@ * Copyright(c) 2023 Intel Corporation. */ +#include "gem/i915_gem_internal.h" + +#include "gt/intel_context.h" + #include "i915_drv.h" -#include "intel_pxp_types.h" +#include "intel_pxp_cmd_interface_43.h" #include "intel_pxp_gsccs.h" +#include "intel_pxp_types.h" + +struct gsccs_session_resources { + struct mutex cmd_mutex; /* Protects submission for arb session */ + u64 host_session_handle; /* used by firmware to link commands to sessions */ + + struct intel_context *ce; /* context for gsc command submission */ + struct i915_ppgtt *ppgtt; /* ppgtt for gsc command submission */ + + struct drm_i915_gem_object *pkt_obj; /* PXP HECI message packet buffer */ + struct i915_vma *pkt_vma; /* PXP HECI message packet vma */ + void *pkt_vaddr; /* PXP HECI message packet virt memory pointer */ + + /* Buffer info for GSC engine batch buffer: */ + struct drm_i915_gem_object *bb_obj; /* batch buffer object */ + struct i915_vma *bb_vma; /* batch buffer vma */ + void *bb_vaddr; /* batch buffer virtual memory pointer */ +}; + +struct gsccs_teelink_priv { + /** @arb_exec_res: resources for arb-session GSC-CS PXP command submission */ + struct gsccs_session_resources arb_exec_res; +}; + +static inline struct gsccs_teelink_priv *pxp_to_gsccs_priv(struct intel_pxp *pxp) +{ + return (struct gsccs_teelink_priv *)pxp->gsccs_priv; +} int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id) @@ -13,11 +45,193 @@ int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, return -ENODEV; } +static void +gsccs_destroy_buffer(struct drm_i915_private *i915, struct i915_vma *vma, + struct drm_i915_gem_object *obj) +{ + int err; + + i915_vma_unpin(vma); + err = i915_vma_unbind(vma); + if (err) + drm_dbg(&i915->drm, "Unexpected failure when vma-unbinding = %d\n", err); + + i915_gem_object_unpin_map(obj); + i915_gem_object_unpin_pages(obj); + i915_gem_object_put(obj); +} + +static int +gsccs_create_buffer(struct drm_i915_private *i915, const char *bufname, + size_t size, struct i915_ppgtt *ppgtt, + struct drm_i915_gem_object **obj, + struct i915_vma **vma, void **map) +{ + int err = 0; + + *obj = i915_gem_object_create_internal(i915, size); + if (IS_ERR(*obj)) { + drm_err(&i915->drm, "Failed to allocate gsccs backend %s.\n", bufname); + err = PTR_ERR(*obj); + goto out_none; + } + + *vma = i915_vma_instance(*obj, &ppgtt->vm, NULL); + if (IS_ERR(*vma)) { + drm_err(&i915->drm, "Failed to vma-instance gsccs backend %s.\n", bufname); + err = PTR_ERR(*vma); + goto out_put; + } + + err = i915_gem_object_pin_pages_unlocked(*obj); + if (err) { + drm_err(&i915->drm, "Failed to pin gsccs backend %s.\n", bufname); + goto out_put; + } + + /* map to the virtual memory pointer */ + *map = i915_gem_object_pin_map_unlocked(*obj, i915_coherent_map_type(i915, *obj, true)); + if (IS_ERR(*map)) { + drm_err(&i915->drm, "Failed to map gsccs backend %s.\n", bufname); + err = PTR_ERR(*map); + goto out_unpin; + } + + /* all PXP sessions commands are treated as non-priveleged */ + err = i915_vma_pin(*vma, 0, 0, PIN_USER); + if (err) { + drm_err(&i915->drm, "Failed to vma-pin gsccs backend %s.\n", bufname); + goto out_unmap; + } + + return 0; + +out_unmap: + i915_gem_object_unpin_map(*obj); +out_unpin: + i915_gem_object_unpin_pages(*obj); +out_put: + i915_gem_object_put(*obj); +out_none: + *obj = NULL; + *vma = NULL; + *map = NULL; + + return err; +} + +static void +gsccs_destroy_execution_resource(struct intel_pxp *pxp, + struct gsccs_session_resources *strm_res) +{ + if (strm_res->ce) + intel_context_put(strm_res->ce); + if (strm_res->bb_obj) + gsccs_destroy_buffer(pxp->ctrl_gt->i915, strm_res->bb_vma, strm_res->bb_obj); + if (strm_res->pkt_obj) + gsccs_destroy_buffer(pxp->ctrl_gt->i915, strm_res->pkt_vma, strm_res->pkt_obj); + if (strm_res->ppgtt) + i915_vm_put(&strm_res->ppgtt->vm); + + memset(strm_res, 0, sizeof(*strm_res)); +} + +static int +gsccs_allocate_execution_resource(struct intel_pxp *pxp, + struct gsccs_session_resources *strm_res) +{ + struct intel_gt *gt = pxp->ctrl_gt; + struct intel_engine_cs *engine = gt->engine[GSC0]; + struct i915_ppgtt *ppgtt; + struct intel_context *ce; + int err = 0; + + /* + * First, ensure the GSC engine is present. + * NOTE: Backend should would only be called with the correct gt. + */ + if (!engine) + return -ENODEV; + + mutex_init(&strm_res->cmd_mutex); + + ppgtt = i915_ppgtt_create(gt, 0); + if (IS_ERR(ppgtt)) + return PTR_ERR(ppgtt); + + strm_res->ppgtt = ppgtt; + + /* + * Now, allocate, pin and map two objects, one for the heci message packet + * and another for the batch buffer we submit into GSC engine (that includes the packet). + * NOTE: GSC-CS backend is currently only supported on MTL, so we allocate shmem. + */ + err = gsccs_create_buffer(pxp->ctrl_gt->i915, "Heci Packet", + PXP43_MAX_HECI_IN_SIZE + PXP43_MAX_HECI_OUT_SIZE, + strm_res->ppgtt, + &strm_res->pkt_obj, &strm_res->pkt_vma, + &strm_res->pkt_vaddr); + if (err) { + gsccs_destroy_execution_resource(pxp, strm_res); + return err; + } + + err = gsccs_create_buffer(pxp->ctrl_gt->i915, "Batch Buffer", + PAGE_SIZE, strm_res->ppgtt, + &strm_res->bb_obj, &strm_res->bb_vma, + &strm_res->bb_vaddr); + if (err) { + gsccs_destroy_execution_resource(pxp, strm_res); + return err; + } + /* + * TODO: Consider optimization of pre-populating batch buffer + * with the send-HECI instruction now at init and reuse through its life. + */ + + /* Finally, create an intel_context to be used during the submission */ + ce = intel_context_create(engine); + if (IS_ERR(ce)) { + drm_err(>->i915->drm, "Failed creating gsccs backend ctx\n"); + gsccs_destroy_execution_resource(pxp, strm_res); + return PTR_ERR(ce); + } + i915_vm_put(ce->vm); + ce->vm = i915_vm_get(&ppgtt->vm); + + strm_res->ce = ce; + + return 0; +} + void intel_pxp_gsccs_fini(struct intel_pxp *pxp) { + struct gsccs_teelink_priv *gsccs = pxp_to_gsccs_priv(pxp); + + if (!gsccs) + return; + + gsccs_destroy_execution_resource(pxp, &gsccs->arb_exec_res); + kfree(gsccs); + pxp->gsccs_priv = NULL; } int intel_pxp_gsccs_init(struct intel_pxp *pxp) { + struct gsccs_teelink_priv *gsccs; + int ret; + + gsccs = kzalloc(sizeof(*gsccs), GFP_KERNEL); + if (!gsccs) + return -ENOMEM; + + ret = gsccs_allocate_execution_resource(pxp, &gsccs->arb_exec_res); + if (ret) { + kfree(gsccs); + return ret; + } + + pxp->gsccs_priv = gsccs; + return 0; } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index 43aa61c26de5..fdcb9a66f691 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -32,6 +32,11 @@ struct intel_pxp { */ bool uses_gsccs; + /** + * @gsccs_priv: GSC-CS based tee-link private context. + */ + void *gsccs_priv; + /** * @pxp_component: i915_pxp_component struct of the bound mei_pxp * module. Only set and cleared inside component bind/unbind functions, From patchwork Wed Jan 11 00:56:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05860C54EBC for ; Wed, 11 Jan 2023 00:57:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6408110E6AD; Wed, 11 Jan 2023 00:56:55 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8E10010E065; Wed, 11 Jan 2023 00:56:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673398612; x=1704934612; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fjecOUVgXS8xG4Kss6ca1QBC/wO9qqrzOpN/iirj/dk=; b=SsiOZfW+uKHJCOE3MiIFwkSRvF6yP6AIy0QMBRne1tq9IDr3VXrgtI8u kK3hQBwMCyPFmUIWnPd8qb1XnBJJaUcETo8LAHc2lg5WR8KfE+CujCfot ZucyDPVCpVh86EDrEPwsJvCKWNi6AOngO4PoAPu4AwJFnZtj0LZRCqUlW RcxM9zdRrBCnpJ23EDLvHGmUh7d/6MTVhA8CetsPFodaLSNMSObqbMFDj CFnubRjvpUHtpvXOz0x++HPAjqbXN9ho4Txk40c0v8iXMJEvcbDBcHL+v peCHda+gTjgSiCrKGBYR9hrWxBrx+raoXFA790+fY60gRi2k/LzkfIHm0 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="325307082" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307082" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175645" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175645" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:50 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/9] drm/i915/pxp: Add MTL hw-plumbing enabling for KCR operation Date: Tue, 10 Jan 2023 16:56:33 -0800 Message-Id: <20230111005642.300761-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MTL hw-plumbing enabling for KCR operation under PXP which includes: 1. Updating 'pick-gt' to get the media tile for KCR interrupt handling 2. Adding MTL's KCR registers for PXP operation (init, status-checking, etc.). While doing #2, lets create a separate registers header file for PXP to be consistent with other i915 global subsystems. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 35 ++++++++++++-------- drivers/gpu/drm/i915/pxp/intel_pxp_regs.h | 26 +++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 29 +++++++++++----- 4 files changed, 70 insertions(+), 23 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_regs.h diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 8fac2660e16b..957fa11373fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -100,7 +100,8 @@ static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) case VIDEO_ENHANCEMENT_CLASS: return media_gt; case OTHER_CLASS: - if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0)) + if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) && + HAS_ENGINE(media_gt, GSC0)) return media_gt; fallthrough; default: diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index be52bf92e847..809b49f59594 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -14,6 +14,7 @@ #include "intel_pxp.h" #include "intel_pxp_gsccs.h" #include "intel_pxp_irq.h" +#include "intel_pxp_regs.h" #include "intel_pxp_session.h" #include "intel_pxp_tee.h" #include "intel_pxp_types.h" @@ -61,21 +62,30 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp) return IS_ENABLED(CONFIG_DRM_I915_PXP) && pxp && pxp->arb_is_valid; } -/* KCR register definitions */ -#define KCR_INIT _MMIO(0x320f0) -/* Setting KCR Init bit is required after system boot */ -#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) +static i915_reg_t get_kcr_reg(const struct intel_pxp *pxp) +{ + if (pxp->gsccs_priv) + return MTL_KCR_INIT; + return GEN12_KCR_INIT; +} -static void kcr_pxp_enable(struct intel_gt *gt) +static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable) { - intel_uncore_write(gt->uncore, KCR_INIT, - _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); + i915_reg_t reg = get_kcr_reg(pxp); + u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + + intel_uncore_write(pxp->ctrl_gt->uncore, reg, val); } -static void kcr_pxp_disable(struct intel_gt *gt) +static void kcr_pxp_enable(const struct intel_pxp *pxp) { - intel_uncore_write(gt->uncore, KCR_INIT, - _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); + kcr_pxp_set_status(pxp, true); +} + +static void kcr_pxp_disable(const struct intel_pxp *pxp) +{ + kcr_pxp_set_status(pxp, false); } static int create_vcs_context(struct intel_pxp *pxp) @@ -323,14 +333,13 @@ int intel_pxp_start(struct intel_pxp *pxp) void intel_pxp_init_hw(struct intel_pxp *pxp) { - kcr_pxp_enable(pxp->ctrl_gt); + kcr_pxp_enable(pxp); intel_pxp_irq_enable(pxp); } void intel_pxp_fini_hw(struct intel_pxp *pxp) { - kcr_pxp_disable(pxp->ctrl_gt); - + kcr_pxp_disable(pxp); intel_pxp_irq_disable(pxp); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h new file mode 100644 index 000000000000..dd4131903d4e --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2023, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_REGS_H__ +#define __INTEL_PXP_REGS_H__ + +#include "i915_reg_defs.h" + +/* KCR enable/disable control */ +#define GEN12_KCR_INIT _MMIO(0x320f0) +#define MTL_KCR_INIT _MMIO(0x3860f0) + +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) + +/* KCR hwdrm session in play status 0-31 */ +#define GEN12_KCR_SIP _MMIO(0x32260) +#define MTL_KCR_SIP _MMIO(0x386260) + +/* PXP global terminate register for session termination */ +#define GEN12_KCR_GLOBAL_TERMINATE _MMIO(0x320f8) +#define MTL_KCR_GLOBAL_TERMINATE _MMIO(0x3860f8) + +#endif /* __INTEL_PXP_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c index 080aa2209c5b..7bb06e67b155 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -11,23 +11,25 @@ #include "intel_pxp_session.h" #include "intel_pxp_tee.h" #include "intel_pxp_types.h" +#include "intel_pxp_regs.h" #define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */ -#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */ - -/* PXP global terminate register for session termination */ -#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8) - static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id) { struct intel_uncore *uncore = pxp->ctrl_gt->uncore; intel_wakeref_t wakeref; + i915_reg_t reg; u32 sip = 0; /* if we're suspended the session is considered off */ - with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) - sip = intel_uncore_read(uncore, GEN12_KCR_SIP); + with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) { + if (pxp->gsccs_priv) + reg = MTL_KCR_SIP; + else + reg = GEN12_KCR_SIP; + sip = intel_uncore_read(uncore, reg); + } return sip & BIT(id); } @@ -37,6 +39,7 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla struct intel_uncore *uncore = pxp->ctrl_gt->uncore; intel_wakeref_t wakeref; u32 mask = BIT(id); + i915_reg_t reg; int ret; /* if we're suspended the session is considered off */ @@ -44,8 +47,13 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla if (!wakeref) return in_play ? -ENODEV : 0; + if (pxp->gsccs_priv) + reg = MTL_KCR_SIP; + else + reg = GEN12_KCR_SIP; + ret = intel_wait_for_register(uncore, - GEN12_KCR_SIP, + reg, mask, in_play ? mask : 0, 100); @@ -112,7 +120,10 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp) return ret; } - intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1); + if (pxp->gsccs_priv) + intel_uncore_write(gt->uncore, MTL_KCR_GLOBAL_TERMINATE, 1); + else + intel_uncore_write(gt->uncore, GEN12_KCR_GLOBAL_TERMINATE, 1); return ret; } From patchwork Wed Jan 11 00:56:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB302C46467 for ; Wed, 11 Jan 2023 00:57:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A60D410E0F2; Wed, 11 Jan 2023 00:56:55 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6BDEE10E0F2; Wed, 11 Jan 2023 00:56:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673398612; x=1704934612; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=obOZtik4n2a2Q2wiaBfxzSUQ/UTVHfE1h2n/RrkK/5c=; b=CO+2k11qh+/vs//qlK/Z6PbCRdzBppFzRtnAUBUnlJxMf8nwIBRYuyGX eqg9AUGAHF6eCtEOxmSUxmtfepvddehoY9mRR6vHeL1xIkd4SnHYayB3i enou+rJXRmw4H10yh4+t37ch2m2jVmQHpflahBOeuNRKtBIEVjQhVQR0y QGSyzPWKIoTKsy7AmOx75BcNzxrUNGlqnRHSo4j2nGHqhJxNONxiDjicN 1amOuRjE48+23aAEqx1xsrXfSRvhDPy22TMo1UVNS68UysPhnDBIcZH13 pJnVHrtBNw/micsHnXUTQIxvjmWGvA+C5kb1GMxWXVOPHzBywO/7EcD96 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="325307084" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307084" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175649" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175649" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:51 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/9] drm/i915/pxp: Add MTL helpers to submit Heci-Cmd-Packet to GSC Date: Tue, 10 Jan 2023 16:56:34 -0800 Message-Id: <20230111005642.300761-5-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add helper functions into (new) common heci-packet-submission files to handle generating the MTL GSC-CS Memory-Header and emitting of the Heci-Cmd-Packet instructions that gets submitted to the engine. NOTE1: This common functions for heci-packet-submission will be used by different i915 callers: 1- GSC-SW-Proxy: This is pending upstream publication awaiting a few remaining opens 2- MTL-HDCP: An equivalent patch has also been published at: https://patchwork.freedesktop.org/series/111876/. (Patch 1) 3- PXP: This series. NOTE2: A difference in this patch vs what is appearing is in bullet 2 above is that HDCP (and SW-Proxy) will be using priveleged submission (GGTT and common gsc-uc-context) while PXP will be using non-priveleged PPGTT, context and batch buffer. Therefore this patch will only slightly overlap with the MTL-HDCP patches despite have very similar function names (emit_foo vs emit_nonpriv_foo). This is because HECI_CMD_PKT instructions require very different flows and hw-specific code when done via PPGTT based submission (not different from other engines). MTL-HDCP contains the same intel_gsc_mtl_header_t structures as this but the helpers there are different. Both add the same new file names. NOTE3: Additional clarity about the heci-cmd-pkt layout and where the common helpers come in: - When an internal subsystem needs to send a command request to the security firmware on MTL onwards, it will send that via the GSC-engine-command-streamer. - However those commands, (lets call them "gsc_specific_fw_api" calls), are not understood by the GSC command streamer hw. - The command streamer DOES understand GSC_HECI_CMD_PKT but requires an additional header before the "gsc_specific_fw_api" is sent by the hw engine to the firmware (with additional metadata). - Thus, the structural layout of the request submitted would need to look like the diagram below (for non-priv PXP). - In the diagram, the common helper for HDCP, (GSC-Sw-Proxy) and PXP (i.e. new function intel_gsc_uc_heci_cmd_emit_mtl_header) will populate blob (C) while additional helpers different for GGTT (not in this series) vs PPGTT (this patch) will populate blobs (A) and (B) below. ___________________________________________________________ (A) | MI_BATCH_BUFFER_START (ppgtt, batchbuff-addr, ...) | | | | | _|________________________________________________ | | (B)| GSC_HECI_CMD_PKT (pkt-addr-in, pkt-size-in, | | | | pkt-addr-out, pkt-size-out) |-------- | | MI_BATCH_BUFFER_END | | | | |________________________________________________| | | | | | |_________________________________________________________| | | --------------------------------------------------------- | \|/ ______V___________________________________________ | _________________________________________ | |(C)| | | | | struct intel_gsc_mtl_header { | | | | validity marker | | | | heci_clent_id | | | | ... | | | | } | | | |_______________________________________| | |(D)| | | | | struct gsc_fw_specific_api_foobar { | | | | ... | | | | For an example, see | | | | 'struct pxp43_create_arb_in' at | | | | intel_pxp_cmd_interface_43.h | | | | | | | | } | | | | Struture depends on command type | | | | struct gsc_fw_specific_api_foobar { | | | |_______________________________________| | |________________________________________________| That said, this patch provides basic helpers but leaves the PXP subsystem (i.e. the caller) to handle everything else from input/output packet size verification to handling the responses from security firmware (such as requiring a retry). Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 + .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 128 ++++++++++++++++++ .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 74 ++++++++++ 4 files changed, 205 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index eae4325310e8..7dc18554da10 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -194,6 +194,7 @@ i915-y += \ i915-y += \ gt/uc/intel_gsc_fw.o \ gt/uc/intel_gsc_uc.o \ + gt/uc/intel_gsc_uc_heci_cmd_submit.o \ gt/uc/intel_guc.o \ gt/uc/intel_guc_ads.o \ gt/uc/intel_guc_capture.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 2af1ae3831df..454179884801 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -439,6 +439,8 @@ #define GSC_FW_LOAD GSC_INSTR(1, 0, 2) #define HECI1_FW_LIMIT_VALID (1 << 31) +#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6) + /* * Used to convert any address to canonical form. * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c new file mode 100644 index 000000000000..2d6c7faf1794 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +#include + +#include "i915_drv.h" +#include "i915_vma.h" + +#include "gt/intel_gpu_commands.h" +#include "gt/intel_context.h" +#include "gt/intel_gt.h" +#include "gt/intel_ring.h" + +#include "intel_gsc_fw.h" +#include "intel_gsc_uc.h" +#include "intel_gsc_uc_heci_cmd_submit.h" + +void +intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header, + u8 heci_client_id, u32 msg_size, + u64 host_session_handle, u32 flags) +{ + int hdr_size = sizeof(struct intel_gsc_mtl_header); + + header->validity_marker = MTL_HECI_VALIDITY_MARKER; + header->header_version = MTL_HECI_HEADER_VERSION; + header->message_size = msg_size + hdr_size; + header->heci_client_id = heci_client_id; + header->flags = flags; + + header->host_session_handle = FIELD_GET(MTL_GSC_HDR_CALLER_SESSION_ID_MASK, + host_session_handle); + + switch (heci_client_id) { + default: + fallthrough; + case MTL_HECI_CLIENT_PXP: + header->host_session_handle |= FIELD_PREP(MTL_GSC_HDR_SESSION_HANDLE_USAGE_MASK, + MTL_GSC_HSH_USAGE_PXP); + break; + case MTL_HECI_CLIENT_ME_PROXY: + header->host_session_handle |= FIELD_PREP(MTL_GSC_HDR_SESSION_HANDLE_USAGE_MASK, + MTL_GSC_HSH_USAGE_PROXY); + break; + case MTL_HECI_CLIENT_HDCP: + header->host_session_handle |= FIELD_PREP(MTL_GSC_HDR_SESSION_HANDLE_USAGE_MASK, + MTL_GSC_HSH_USAGE_HDCP); + break; + } +} + +#define GSC_HECI_CMD_PKT_NONPRIV_SIZE 8 + +static void +emit_gsc_heci_pkt_nonpriv(u32 *cs, struct intel_gsc_heci_non_priv_pkt *pkt) +{ + *cs++ = GSC_HECI_CMD_PKT; + *cs++ = lower_32_bits(pkt->addr_in); + *cs++ = upper_32_bits(pkt->addr_in); + *cs++ = pkt->size_in; + *cs++ = lower_32_bits(pkt->addr_out); + *cs++ = upper_32_bits(pkt->addr_out); + *cs++ = pkt->size_out; + *cs++ = 0; + *cs++ = MI_BATCH_BUFFER_END; +} + +int +intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc, + struct intel_context *ce, + struct intel_gsc_heci_non_priv_pkt *pkt, + u32 *cs, int timeout_ms) +{ + struct intel_engine_cs *eng; + struct i915_request *rq; + int err; + + rq = intel_context_create_request(ce); + if (IS_ERR(rq)) + return PTR_ERR(rq); + + emit_gsc_heci_pkt_nonpriv(cs, pkt); + + i915_vma_lock(pkt->bb_vma); + err = i915_vma_move_to_active(pkt->bb_vma, rq, EXEC_OBJECT_WRITE); + i915_vma_unlock(pkt->bb_vma); + + if (!err) { + i915_vma_lock(pkt->heci_pkt_vma); + err = i915_vma_move_to_active(pkt->heci_pkt_vma, rq, EXEC_OBJECT_WRITE); + i915_vma_unlock(pkt->heci_pkt_vma); + } + + eng = rq->context->engine; + if (!err && eng->emit_init_breadcrumb) + err = eng->emit_init_breadcrumb(rq); + + if (!err) + err = eng->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0); + + if (err) { + i915_request_add(rq); + return err; + } + + i915_request_get(rq); + + i915_request_add(rq); + if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, + msecs_to_jiffies(timeout_ms)) < 0) { + i915_request_put(rq); + return -ETIME; + } + + i915_request_put(rq); + + err = ce->engine->emit_flush(rq, 0); + if (err) + drm_err(&gsc_uc_to_gt(gsc)->i915->drm, + "Failed emit-flush for gsc-heci-non-priv-pkterr=%d\n", err); + + if (unlikely(err)) + i915_request_set_error_once(rq, err); + + return err; +} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h new file mode 100644 index 000000000000..394d9929529a --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef _INTEL_GSC_UC_HECI_CMD_H_ +#define _INTEL_GSC_UC_HECI_CMD_H_ + +#include + +struct i915_vma; +struct intel_context; +struct intel_gsc_uc; + +struct intel_gsc_mtl_header { + u32 validity_marker; +#define MTL_HECI_VALIDITY_MARKER 0xA578875A + + u8 heci_client_id; +#define MTL_HECI_CLIENT_ME_PROXY 10 +#define MTL_HECI_CLIENT_PXP 17 +#define MTL_HECI_CLIENT_HDCP 18 + + u8 reserved1; + + u16 header_version; +#define MTL_HECI_HEADER_VERSION 1 + + u64 host_session_handle; /* avoid collision across subsystem users, define format: */ +#define MTL_GSC_HDR_SESSION_HANDLE_USAGE_MASK GENMASK(63, 56) /* caller leaves empty */ +#define MTL_GSC_HSH_USAGE_PROXY 0x1 +#define MTL_GSC_HSH_USAGE_HDCP 0x2 +#define MTL_GSC_HSH_USAGE_PXP 0x3 +#define MTL_GSC_HDR_CALLER_SESSION_ID_MASK GENMASK(55, 0) + + u64 gsc_message_handle; + + u32 message_size; /* lower 20 bits only, upper 12 are reserved */ + + /* + * Flags mask: + * Bit 0: Pending + * Bit 1: Session Cleanup; + * Bits 2-15: Flags + * Bits 16-31: Extension Size + */ + u32 flags; +#define MTL_GSC_HDR_FLAG_MSG_PENDING BIT(0) +#define MTL_GSC_HDR_FLAG_MSG_CLEANUP BIT(1) + + u32 status; +} __packed; + +struct intel_gsc_heci_non_priv_pkt { + u64 addr_in; + u32 size_in; + u64 addr_out; + u32 size_out; + struct i915_vma *heci_pkt_vma; + struct i915_vma *bb_vma; +}; + +void +intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header, + u8 heci_client_id, u32 msg_size, + u64 host_session_handle, u32 flags); + +int +intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc, + struct intel_context *ce, + struct intel_gsc_heci_non_priv_pkt *pkt, + u32 *cs, int timeout_ms); + +#endif From patchwork Wed Jan 11 00:56:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91415C46467 for ; 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a="325307086" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307086" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175654" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175654" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:51 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/9] drm/i915/pxp: Add GSC-CS backend-teelink for send-message function Date: Tue, 10 Jan 2023 16:56:35 -0800 Message-Id: <20230111005642.300761-6-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Populate the backend-teelink abstraction layer using GSC-CS engine for MTL (and future) products. The PXP backend for sending messages Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c index 97ca187e6fde..84045e18591e 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c @@ -6,6 +6,7 @@ #include "gem/i915_gem_internal.h" #include "gt/intel_context.h" +#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h" #include "i915_drv.h" #include "intel_pxp_cmd_interface_43.h" @@ -39,6 +40,97 @@ static inline struct gsccs_teelink_priv *pxp_to_gsccs_priv(struct intel_pxp *pxp return (struct gsccs_teelink_priv *)pxp->gsccs_priv; } +static int gsccs_send_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_size_max, + size_t *msg_out_len) +{ + struct intel_gt *gt = pxp->ctrl_gt; + struct drm_i915_private *i915 = gt->i915; + struct gsccs_session_resources *exec = &pxp_to_gsccs_priv(pxp)->arb_exec_res; + struct intel_gsc_mtl_header *header = exec->pkt_vaddr; + struct intel_gsc_heci_non_priv_pkt pkt; + size_t max_msg_size; + u32 reply_size; + int ret; + + if (!intel_uc_uses_gsc_uc(>->uc)) + return -ENODEV; + + if (!exec->ce) + return -ENODEV; + + max_msg_size = PXP43_MAX_HECI_IN_SIZE - sizeof(*header); + + if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size) + return -ENOSPC; + + mutex_lock(&exec->cmd_mutex); + + if (!exec->pkt_vma || !exec->bb_vma) + return -ENOENT; + + memset(header, 0, sizeof(*header)); + intel_gsc_uc_heci_cmd_emit_mtl_header(header, MTL_HECI_CLIENT_PXP, msg_in_size, + exec->host_session_handle, 0); + + memcpy(exec->pkt_vaddr + sizeof(*header), msg_in, msg_in_size); + + pkt.addr_in = i915_vma_offset(exec->pkt_vma); + pkt.size_in = header->message_size; + pkt.addr_out = pkt.addr_in + PXP43_MAX_HECI_IN_SIZE; + pkt.size_out = msg_out_size_max + sizeof(*header); + pkt.heci_pkt_vma = exec->pkt_vma; + pkt.bb_vma = exec->bb_vma; + + ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&pxp->ctrl_gt->uc.gsc, + exec->ce, &pkt, exec->bb_vaddr, 500); + if (ret) { + drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret); + goto unlock; + } + + /* we keep separate location for reply, so get the response header loc first */ + header = exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE; + + /* Response validity marker, status and busyness */ + if (header->validity_marker != MTL_HECI_VALIDITY_MARKER) { + drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n"); + ret = -EINVAL; + goto unlock; + } + if (header->status != 0) { + drm_dbg(&i915->drm, "gsc PXP reply status has error = 0x%08x\n", + header->status); + ret = -EINVAL; + goto unlock; + } + if (header->flags & MTL_GSC_HDR_FLAG_MSG_PENDING) { + drm_dbg(&i915->drm, "gsc PXP reply is busy\n"); + ret = -EAGAIN; + goto unlock; + } + + reply_size = header->message_size - sizeof(*header); + if (reply_size > msg_out_size_max) { + drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n", + reply_size, msg_out_size_max); + reply_size = msg_out_size_max; + } else if (reply_size != msg_out_size_max) { + drm_dbg(&i915->drm, "caller unexpected PXP reply size %u (%ld)\n", + reply_size, msg_out_size_max); + } + + memcpy(msg_out, exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE + sizeof(*header), + reply_size); + if (msg_out_len) + *msg_out_len = reply_size; + +unlock: + mutex_unlock(&exec->cmd_mutex); + return ret; +} + int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id) { From patchwork Wed Jan 11 00:56:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 289E2C677F1 for ; Wed, 11 Jan 2023 00:57:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F13D10E6C1; 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10 Jan 2023 16:56:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175660" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175660" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:52 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 6/9] drm/i915/pxp: Add ARB session creation with new PXP API Ver4.3 Date: Tue, 10 Jan 2023 16:56:37 -0800 Message-Id: <20230111005642.300761-8-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MTL's function for ARB session creation using PXP firmware version 4.3 ABI structure format. Before checking the return status, look at the GSC-CS-Mem-Header's pending-bit which means the GSC firmware is busy and we should resubmit. Signed-off-by: Alan Previn --- .../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 21 +++++++ drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 56 ++++++++++++++++++- 2 files changed, 74 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index 52b9a61bcdd4..ee78c0817ba1 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -11,6 +11,7 @@ /* PXP-Cmd-Op definitions */ #define PXP43_CMDID_START_HUC_AUTH 0x0000003A +#define PXP43_CMDID_INIT_SESSION 0x00000036 /* PXP-Packet sizes for MTL's GSCCS-HECI instruction */ #define PXP43_MAX_HECI_IN_SIZE (SZ_32K) @@ -27,4 +28,24 @@ struct pxp43_start_huc_auth_out { struct pxp_cmd_header header; } __packed; +/* PXP-Input-Packet: Init PXP session */ +struct pxp43_create_arb_in { + struct pxp_cmd_header header; + /* header.stream_id fields for vesion 4.3 of Init PXP session: */ + #define PXP43_INIT_SESSION_VALID GENMASK(0, 0) + #define PXP43_INIT_SESSION_APPTYPE GENMASK(1, 1) + #define PXP43_INIT_SESSION_APPID GENMASK(17, 2) + u32 protection_mode; + #define PXP43_INIT_SESSION_PROTECTION_ARB 0x2 + u32 sub_session_id; + u32 init_flags; + u32 rsvd[12]; +} __packed; + +/* PXP-Input-Packet: Init PXP session */ +struct pxp43_create_arb_out { + struct pxp_cmd_header header; + u32 rsvd[8]; +} __packed; + #endif /* __INTEL_PXP_FW_INTERFACE_43_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c index 84045e18591e..9fe30516eced 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c @@ -43,7 +43,8 @@ static inline struct gsccs_teelink_priv *pxp_to_gsccs_priv(struct intel_pxp *pxp static int gsccs_send_message(struct intel_pxp *pxp, void *msg_in, size_t msg_in_size, void *msg_out, size_t msg_out_size_max, - size_t *msg_out_len) + size_t *msg_out_len, + u64 *gsc_msg_handle_retry) { struct intel_gt *gt = pxp->ctrl_gt; struct drm_i915_private *i915 = gt->i915; @@ -74,6 +75,9 @@ static int gsccs_send_message(struct intel_pxp *pxp, intel_gsc_uc_heci_cmd_emit_mtl_header(header, MTL_HECI_CLIENT_PXP, msg_in_size, exec->host_session_handle, 0); + /* copy caller provided gsc message handle if this is polling for a prior msg completion */ + header->gsc_message_handle = *gsc_msg_handle_retry; + memcpy(exec->pkt_vaddr + sizeof(*header), msg_in, msg_in_size); pkt.addr_in = i915_vma_offset(exec->pkt_vma); @@ -90,7 +94,7 @@ static int gsccs_send_message(struct intel_pxp *pxp, goto unlock; } - /* we keep separate location for reply, so get the response header loc first */ + /* we keep separate location for reply, so go to the response header now */ header = exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE; /* Response validity marker, status and busyness */ @@ -107,6 +111,13 @@ static int gsccs_send_message(struct intel_pxp *pxp, } if (header->flags & MTL_GSC_HDR_FLAG_MSG_PENDING) { drm_dbg(&i915->drm, "gsc PXP reply is busy\n"); + /* + * When the GSC firmware replies with pending bit, it means that the requested + * operation has begun but the completion is pending and the caller needs + * to re-request with the gsc_message_handle that was returned by the firmware. + * until the pending bit is turned off. + */ + *gsc_msg_handle_retry = header->gsc_message_handle; ret = -EAGAIN; goto unlock; } @@ -134,7 +145,46 @@ static int gsccs_send_message(struct intel_pxp *pxp, int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id) { - return -ENODEV; + struct gsccs_session_resources *exec = &pxp_to_gsccs_priv(pxp)->arb_exec_res; + struct pxp43_create_arb_in msg_in = {0}; + struct pxp43_create_arb_out msg_out = {0}; + u64 gsc_session_retry = 0; + int insize, outsize, ret, tries = 0; + void *inptr, *outptr; + + /* get a unique host-session-handle (used later in HW cmds) at time of session creation */ + get_random_bytes(&exec->host_session_handle, sizeof(exec->host_session_handle)); + + msg_in.header.api_version = PXP_APIVER(4, 3); + msg_in.header.command_id = PXP43_CMDID_INIT_SESSION; + msg_in.header.stream_id = (FIELD_PREP(PXP43_INIT_SESSION_APPID, arb_session_id) | + FIELD_PREP(PXP43_INIT_SESSION_VALID, 1) | + FIELD_PREP(PXP43_INIT_SESSION_APPTYPE, 0)); + msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); + msg_in.protection_mode = PXP43_INIT_SESSION_PROTECTION_ARB; + + inptr = &msg_in; + outptr = &msg_out; + insize = sizeof(msg_in); + outsize = sizeof(msg_out); + + /* + * Keep sending request if GSC firmware was busy. + * Based on test data, we expects a worst case delay of 250 milisecs. + */ + do { + ret = gsccs_send_message(pxp, + inptr, insize, + outptr, outsize, NULL, + &gsc_session_retry); + /* Only try again if gsc says so */ + if (ret != -EAGAIN) + break; + + msleep(20); + } while (++tries < 12); + + return ret; } static void From patchwork Wed Jan 11 00:56:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC23AC54EBC for ; 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a="325307097" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307097" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175664" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175664" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:53 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 7/9] drm/i915/pxp: MTL-KCR interrupt ctrl's are in GT-0 Date: Tue, 10 Jan 2023 16:56:38 -0800 Message-Id: <20230111005642.300761-9-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Despite KCR subsystem being in the media-tile (close to the GSC-CS), the IRQ controls for it are on GT-0 with other global IRQ controls. Thus, add a helper for KCR hw interrupt enable/disable functions to get the correct gt structure (for uncore) for MTL. In the helper, we get GT-0's handle for uncore when touching IRQ registers despite the pxp->ctrl_gt being the media-tile. No difference for legacy of course. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 23 +++++++++++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +++++++ 3 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4b8e70caa3ad..9f6e300486b4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -44,7 +44,7 @@ static int pxp_terminate_get(void *data, u64 *val) static int pxp_terminate_set(void *data, u64 val) { struct intel_pxp *pxp = data; - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); if (!intel_pxp_is_active(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index 91e9622c07d0..2eef0c19e91a 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -8,6 +8,7 @@ #include "gt/intel_gt_regs.h" #include "gt/intel_gt_types.h" +#include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" @@ -17,6 +18,22 @@ #include "intel_pxp_types.h" #include "intel_runtime_pm.h" +/** + * intel_pxp_get_irq_gt - Find the correct GT that owns KCR interrupts + * @pxp: pointer to pxp struct + * + * For platforms with a single GT, we return the pxp->ctrl_gt (as expected) + * but for MTL+ that has a media-tile, although the KCR engine is in the + * media-tile (i.e. pxp->ctrl_gt), the IRQ controls are on the root tile. + */ +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) +{ + if (pxp->uses_gsccs) + return to_gt(pxp->ctrl_gt->i915); + + return pxp->ctrl_gt; +} + /** * intel_pxp_irq_handler - Handles PXP interrupts. * @pxp: pointer to pxp struct @@ -29,7 +46,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) return; - gt = pxp->ctrl_gt; + gt = intel_pxp_get_irq_gt(pxp); lockdep_assert_held(gt->irq_lock); @@ -68,7 +85,7 @@ static inline void pxp_irq_reset(struct intel_gt *gt) void intel_pxp_irq_enable(struct intel_pxp *pxp) { - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); spin_lock_irq(gt->irq_lock); @@ -83,7 +100,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp) void intel_pxp_irq_disable(struct intel_pxp *pxp) { - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); /* * We always need to submit a global termination when we re-enable the diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h index 8c292dc86f68..117159e19e94 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h @@ -9,6 +9,7 @@ #include struct intel_pxp; +struct intel_gt; #define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1) #define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2) @@ -23,6 +24,8 @@ struct intel_pxp; void intel_pxp_irq_enable(struct intel_pxp *pxp); void intel_pxp_irq_disable(struct intel_pxp *pxp); void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp); + #else static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { @@ -35,6 +38,11 @@ static inline void intel_pxp_irq_enable(struct intel_pxp *pxp) static inline void intel_pxp_irq_disable(struct intel_pxp *pxp) { } + +struct intel_gt *gt intel_pxp_get_irq_gt(struct intel_pxp *pxp) +{ + return NULL; +} #endif #endif /* __INTEL_PXP_IRQ_H__ */ From patchwork Wed Jan 11 00:56:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11433C678D5 for ; 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a="325307107" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307107" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175678" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175678" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:54 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 8/9] drm/i915/pxp: On MTL, KCR HW can be enabled instantly Date: Tue, 10 Jan 2023 16:56:41 -0800 Message-Id: <20230111005642.300761-12-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On legacy platforms, KCR HW enabling is done at the time the mei component interface is loaded. It's also disabled during unbind. For MTL onwards, we don't need a separate component driver to send FW messages via GSC-CS. Thus, immediately enable KCR HW on PXP's init, fini and resume. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 52 ++++++++++++++++++------ drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 10 ++--- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 13 +----- 4 files changed, 49 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 809b49f59594..90e739345924 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -143,10 +143,12 @@ static void pxp_init_full(struct intel_pxp *pxp) if (ret) return; - if (pxp->uses_gsccs) + if (pxp->uses_gsccs) { ret = intel_pxp_gsccs_init(pxp); - else + intel_pxp_init_hw(pxp, true); + } else { ret = intel_pxp_tee_component_init(pxp); + } if (ret) goto out_context; @@ -249,10 +251,12 @@ void intel_pxp_fini(struct drm_i915_private *i915) i915->pxp->arb_is_valid = false; - if (i915->pxp->uses_gsccs) + if (i915->pxp->uses_gsccs) { + intel_pxp_fini_hw(i915->pxp, true); intel_pxp_gsccs_fini(i915->pxp); - else + } else { intel_pxp_tee_component_fini(i915->pxp); + } destroy_vcs_context(i915->pxp); @@ -304,8 +308,9 @@ int intel_pxp_start(struct intel_pxp *pxp) if (!intel_pxp_is_enabled(pxp)) return -ENODEV; - if (wait_for(pxp_component_bound(pxp), 250)) - return -ENXIO; + if (!pxp->uses_gsccs) + if (wait_for(pxp_component_bound(pxp), 250)) + return -ENXIO; mutex_lock(&pxp->arb_mutex); @@ -331,16 +336,39 @@ int intel_pxp_start(struct intel_pxp *pxp) return ret; } -void intel_pxp_init_hw(struct intel_pxp *pxp) +static void +intel_pxp_hw_state_change(struct intel_pxp *pxp, bool enable, + bool skip_if_runtime_pm_off) +{ + intel_wakeref_t wakeref; + + if (skip_if_runtime_pm_off) { + /* if we are suspended, the HW will be re-initialized on resume */ + wakeref = intel_runtime_pm_get_if_in_use(&pxp->ctrl_gt->i915->runtime_pm); + if (!wakeref) + return; + } + + if (enable) { + kcr_pxp_enable(pxp); + intel_pxp_irq_enable(pxp); + } else { + kcr_pxp_disable(pxp); + intel_pxp_irq_disable(pxp); + } + + if (skip_if_runtime_pm_off) + intel_runtime_pm_put(&pxp->ctrl_gt->i915->runtime_pm, wakeref); +} + +void intel_pxp_init_hw(struct intel_pxp *pxp, bool skip_if_runtime_pm_off) { - kcr_pxp_enable(pxp); - intel_pxp_irq_enable(pxp); + intel_pxp_hw_state_change(pxp, true, skip_if_runtime_pm_off); } -void intel_pxp_fini_hw(struct intel_pxp *pxp) +void intel_pxp_fini_hw(struct intel_pxp *pxp, bool skip_if_runtime_pm_off) { - kcr_pxp_disable(pxp); - intel_pxp_irq_disable(pxp); + intel_pxp_hw_state_change(pxp, false, skip_if_runtime_pm_off); } int intel_pxp_key_check(struct intel_pxp *pxp, diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 04440fada711..6c1fe3f0a20c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -20,8 +20,8 @@ bool intel_pxp_is_active(const struct intel_pxp *pxp); int intel_pxp_init(struct drm_i915_private *i915); void intel_pxp_fini(struct drm_i915_private *i915); -void intel_pxp_init_hw(struct intel_pxp *pxp); -void intel_pxp_fini_hw(struct intel_pxp *pxp); +void intel_pxp_init_hw(struct intel_pxp *pxp, bool skip_if_runtime_pm_off); +void intel_pxp_fini_hw(struct intel_pxp *pxp, bool skip_if_runtime_pm_off); void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 892d39cc61c1..94c1b2fe1eb2 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -29,7 +29,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) return; with_intel_runtime_pm(&pxp->ctrl_gt->i915->runtime_pm, wakeref) { - intel_pxp_fini_hw(pxp); + intel_pxp_fini_hw(pxp, false); pxp->hw_state_invalidated = false; } } @@ -40,14 +40,14 @@ void intel_pxp_resume(struct intel_pxp *pxp) return; /* - * The PXP component gets automatically unbound when we go into S3 and + * On Pre-MTL, PXP component gets automatically unbound when we go into S3 and * re-bound after we come out, so in that scenario we can defer the * hw init to the bind call. */ - if (!pxp->pxp_component) + if (!pxp->uses_gsccs & !pxp->pxp_component) return; - intel_pxp_init_hw(pxp); + intel_pxp_init_hw(pxp, false); } void intel_pxp_runtime_suspend(struct intel_pxp *pxp) @@ -57,7 +57,7 @@ void intel_pxp_runtime_suspend(struct intel_pxp *pxp) pxp->arb_is_valid = false; - intel_pxp_fini_hw(pxp); + intel_pxp_fini_hw(pxp, false); pxp->hw_state_invalidated = false; } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index d50354bfb993..9b34f2056b19 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -141,16 +141,9 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, } } - /* if we are suspended, the HW will be re-initialized on resume */ - wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm); - if (!wakeref) - return 0; - /* the component is required to fully start the PXP HW */ if (intel_pxp_is_enabled(pxp)) - intel_pxp_init_hw(pxp); - - intel_runtime_pm_put(&i915->runtime_pm, wakeref); + intel_pxp_init_hw(pxp, true); return ret; } @@ -160,11 +153,9 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915->pxp; - intel_wakeref_t wakeref; if (intel_pxp_is_enabled(pxp)) - with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) - intel_pxp_fini_hw(pxp); + intel_pxp_fini_hw(pxp, true); mutex_lock(&pxp->tee_mutex); pxp->pxp_component = NULL; From patchwork Wed Jan 11 00:56:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13095826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 595BFC54EBC for ; Wed, 11 Jan 2023 00:57:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EE9B10E6BD; Wed, 11 Jan 2023 00:57:08 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8552C10E065; Wed, 11 Jan 2023 00:56:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673398615; x=1704934615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b5YoYp4OrK2eHLtUuRciAHVkS2Lhay1cagFw4CeHzhc=; b=GzRRBoKcfWAP//5kIF5oCM41qKg9SWMr2SdCo/6UTprbxE+c7fn5UwHJ BPs+AF0ohpVgFu+FsrtJyDQDhII+8Zu2AwSORFY1mkjp12ahDOrXRJtS8 MLn7BQRuyh7kBlfWfNh83RhQ9skLvnz9veMNhHZgfAl0fZXlLixuMMaI+ LjGdQYxnOEdrfDajUMjslIkbOvyz8MjlGWT4o85BTk+Bp3nfSxdxkkuhA FKg015ke0D/P9o1khN12BAkxlf+ZN0Qd1KfQCxFk0l93zQubkBLqFcSo5 dsxkxDoh/hk3XtflCIa+kMEfH5u2CT38g18x7iXvI14Ad+L4iXj7pcev+ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="325307110" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325307110" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2023 16:56:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831175682" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="831175682" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 10 Jan 2023 16:56:54 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH 9/9] drm/i915/pxp: Enable PXP with MTL-GSC-CS Date: Tue, 10 Jan 2023 16:56:42 -0800 Message-Id: <20230111005642.300761-13-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> References: <20230111005642.300761-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable PXP with MTL-GSC-CS: add the has_pxp into device info and increase the timeouts for new GSC-CS + firmware specs. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6cc65079b18d..a461db7ac2af 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1149,6 +1149,7 @@ static const struct intel_device_info mtl_info = { .has_guc_deprivilege = 1, .has_mslice_steering = 0, .has_snoop = 1, + .has_pxp = 1, .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), .require_force_probe = 1, diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c index 7bb06e67b155..e4e60e3b9216 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c @@ -56,7 +56,7 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla reg, mask, in_play ? mask : 0, - 100); + 250); intel_runtime_pm_put(uncore->rpm, wakeref);