From patchwork Thu Jan 24 20:21:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BE4614E5 for ; Thu, 24 Jan 2019 20:23:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 69FC128EC2 for ; Thu, 24 Jan 2019 20:23:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5DB802EFA9; Thu, 24 Jan 2019 20:23:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C13D328EC2 for ; Thu, 24 Jan 2019 20:23:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728439AbfAXUWT (ORCPT ); Thu, 24 Jan 2019 15:22:19 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:52890 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726040AbfAXUWS (ORCPT ); Thu, 24 Jan 2019 15:22:18 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0DA8B60CA5; Thu, 24 Jan 2019 20:22:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361337; bh=zaruU3IgIUz/nxpIq1WfW9wyVxVMCUZsHVSm1uZdDRo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NxkbGPNL7gH2WH95z3ObmeRflOuy0OikdIIXB1lF6RyMLr93jey51NXzNV97uiFtm hs31pyrEzHcwb9GpZzyjFfjL00bdT4MxgF3ly/8WJMjbKCASbkd2nK3q9jChi8DR+Z YUc2s3yOEEbEaB73IzMcU2A5mm0pz+GxF8vy2bzg= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D68976034E; Thu, 24 Jan 2019 20:22:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361333; bh=zaruU3IgIUz/nxpIq1WfW9wyVxVMCUZsHVSm1uZdDRo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G7S3ow5eudFIWqbkmy95xqUY35CjVFQ9YvBXQXG5WpFyPfdxm28/CU1edFh2MiIpr mdw2Ns9WlC7TrVJqlYB/6mxT+0I96OTZKQlSCTe9cHYI1xplXQb4+/8UlmOOam3dlA p1CQPZdi1EBh9PUQEijtySSaH/MpmB/ICQFJ/XCA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D68976034E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Thierry Reding , Lina Iyer Subject: [PATCH v2 1/8] gpio: Add support for hierarchical IRQ domains Date: Thu, 24 Jan 2019 13:21:58 -0700 Message-Id: <20190124202205.7940-2-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Hierarchical IRQ domains can be used to stack different IRQ controllers on top of each other. One specific use-case where this can be useful is if a power management controller has top-level controls for wakeup interrupts. In such cases, the power management controller can be a parent to other interrupt controllers and program additional registers when an IRQ has its wake capability enabled or disabled. Signed-off-by: Thierry Reding Signed-off-by: Lina Iyer --- drivers/gpio/gpiolib.c | 15 +++++++++++---- include/linux/gpio/driver.h | 6 ++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 1651d7f0a303..1c3ae1d3c368 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1888,7 +1888,9 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, type = IRQ_TYPE_NONE; } - gpiochip->to_irq = gpiochip_to_irq; + if (!gpiochip->to_irq) + gpiochip->to_irq = gpiochip_to_irq; + gpiochip->irq.default_type = type; gpiochip->irq.lock_key = lock_key; gpiochip->irq.request_key = request_key; @@ -1898,9 +1900,14 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, else ops = &gpiochip_domain_ops; - gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio, - gpiochip->irq.first, - ops, gpiochip); + if (gpiochip->irq.parent_domain) + gpiochip->irq.domain = irq_domain_add_hierarchy(gpiochip->irq.parent_domain, + 0, gpiochip->ngpio, + np, ops, gpiochip); + else + gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio, + gpiochip->irq.first, + ops, gpiochip); if (!gpiochip->irq.domain) return -EINVAL; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 07cddbf45186..88ef196f96ec 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -48,6 +48,12 @@ struct gpio_irq_chip { */ const struct irq_domain_ops *domain_ops; + /** + * @parent_domain: + * + */ + struct irq_domain *parent_domain; + /** * @handler: * From patchwork Thu Jan 24 20:21:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 837A71399 for ; Thu, 24 Jan 2019 20:23:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72F3228EC2 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer Subject: [PATCH v2 2/8] irqdomain: add bus token DOMAIN_BUS_WAKEUP Date: Thu, 24 Jan 2019 13:21:59 -0700 Message-Id: <20190124202205.7940-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new bus token to describe domains that are wakeup capable. Suggested-by: Stephen Boyd Signed-off-by: Lina Iyer --- include/linux/irqdomain.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 35965f41d7be..05055bc992ab 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -82,6 +82,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_NEXUS, DOMAIN_BUS_IPI, DOMAIN_BUS_FSL_MC_MSI, + DOMAIN_BUS_WAKEUP, }; /** From patchwork Thu Jan 24 20:22:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D3CC14E5 for ; Thu, 24 Jan 2019 20:22:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A1A82EF4D for ; Thu, 24 Jan 2019 20:22:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D9522FF0C; Thu, 24 Jan 2019 20:22:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72CBF2EF4D for ; Thu, 24 Jan 2019 20:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729252AbfAXUWZ (ORCPT ); Thu, 24 Jan 2019 15:22:25 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53140 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729124AbfAXUWY (ORCPT ); Thu, 24 Jan 2019 15:22:24 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A121360D5A; Thu, 24 Jan 2019 20:22:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361342; bh=L9V54sbbUgHNYhItyXPDtWw9cPL0oBD5jud+ryaKs9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZDZFlJYWB6TSd/tnl1hXaCH2LENcbELfahUWOYBXNC4u+saXPLiad/uFzw1xZgm+W TvJUdI+gzespp/+rkCgrtjvSDcLY5k4RGv1jFQETb4YSvLowJLmKUGJcsG50TFn18V pQ22EfyMjOKrZwrobrhcYvopbQj0QXZkFrVWNTmU= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 01ED36034E; Thu, 24 Jan 2019 20:22:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361336; bh=L9V54sbbUgHNYhItyXPDtWw9cPL0oBD5jud+ryaKs9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ocVgJpXMDeducJVA5+/r5NM65L5++FwLKJ8IjMvF0X7IaDI/2RzsGe9cxhJgZ/Kkg r8SHwbiZ+r3ZWyjbeSs2mAVPm1p6LDpKisz6N7Ljis3TZpa+VOrNNrzSEvlervAmAF pUAujkPVJcf6XwzTs0qSbiwB40Nhw3SthvcThwAM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 01ED36034E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer Subject: [PATCH v2 3/8] drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs Date: Thu, 24 Jan 2019 13:22:00 -0700 Message-Id: <20190124202205.7940-4-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent. Also, provide the map of the PDC pins for the GPIOs for SDM845. Co-developed-by: Stephen Boyd Signed-off-by: Lina Iyer --- Changes in v2: - Remove separate file for PDC GPIO map data - Error checks and return - Whitespace fixes --- drivers/irqchip/qcom-pdc.c | 204 +++++++++++++++++++++++++++++++++-- include/linux/soc/qcom/irq.h | 23 ++++ 2 files changed, 216 insertions(+), 11 deletions(-) create mode 100644 include/linux/soc/qcom/irq.h diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index faa7d61b9d6c..eecf5b920250 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -13,12 +13,13 @@ #include #include #include +#include #include -#include #include #include #define PDC_MAX_IRQS 126 +#define PDC_MAX_GPIO_IRQS 256 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) @@ -32,6 +33,16 @@ struct pdc_pin_region { u32 cnt; }; +struct pdc_gpio_pin_map { + unsigned int gpio; + u32 pdc_pin; +}; + +struct pdc_gpio_pin_data { + size_t size; + const struct pdc_gpio_pin_map *map; +}; + static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; static struct pdc_pin_region *pdc_region; @@ -47,9 +58,8 @@ static u32 pdc_reg_read(int reg, u32 i) return readl_relaxed(pdc_base + reg + i * sizeof(u32)); } -static void pdc_enable_intr(struct irq_data *d, bool on) +static void pdc_enable_intr(irq_hw_number_t pin_out, bool on) { - int pin_out = d->hwirq; u32 index, mask; u32 enable; @@ -65,13 +75,23 @@ static void pdc_enable_intr(struct irq_data *d, bool on) static void qcom_pdc_gic_mask(struct irq_data *d) { - pdc_enable_intr(d, false); + irq_hw_number_t hwirq = d->hwirq; + + if (hwirq == ULONG_MAX) + return; + + pdc_enable_intr(hwirq, false); irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { - pdc_enable_intr(d, true); + irq_hw_number_t hwirq = d->hwirq; + + if (hwirq == ULONG_MAX) + return; + + pdc_enable_intr(hwirq, true); irq_chip_unmask_parent(d); } @@ -111,9 +131,12 @@ enum pdc_irq_config_bits { */ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) { - int pin_out = d->hwirq; + irq_hw_number_t pin_out = d->hwirq; enum pdc_irq_config_bits pdc_type; + if (pin_out == ULONG_MAX) + return 0; + switch (type) { case IRQ_TYPE_EDGE_RISING: pdc_type = PDC_EDGE_RISING; @@ -157,7 +180,7 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_set_affinity = irq_chip_set_affinity_parent, }; -static irq_hw_number_t get_parent_hwirq(int pin) +static irq_hw_number_t get_parent_hwirq(irq_hw_number_t pin) { int i; struct pdc_pin_region *region; @@ -169,7 +192,6 @@ static irq_hw_number_t get_parent_hwirq(int pin) return (region->parent_base + pin - region->pin_base); } - WARN_ON(1); return ~0UL; } @@ -232,6 +254,64 @@ static const struct irq_domain_ops qcom_pdc_ops = { .free = irq_domain_free_irqs_common, }; +static irq_hw_number_t qcom_gpio_to_pdc_pin(struct irq_domain *domain, + unsigned int gpio) +{ + unsigned int i; + const struct pdc_gpio_pin_data *data = domain->host_data; + + if (data) { + for (i = 0; i < data->size; i++) + if (gpio == data->map[i].gpio) + return data->map[i].pdc_pin; + } + + return ULONG_MAX; +} + +static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct qcom_irq_fwspec *qcom_fwspec = data; + struct irq_fwspec *fwspec = &qcom_fwspec->fwspec; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq, parent_hwirq; + unsigned int type; + int ret; + + hwirq = qcom_gpio_to_pdc_pin(domain, fwspec->param[0]); + if (hwirq == ULONG_MAX) + return 0; + + parent_hwirq = get_parent_hwirq(hwirq); + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &qcom_pdc_gic_chip, NULL); + if (ret) + return ret; + + qcom_fwspec->mask = true; + + if (type & IRQ_TYPE_EDGE_BOTH) + type = IRQ_TYPE_EDGE_RISING; + + if (type & IRQ_TYPE_LEVEL_MASK) + type = IRQ_TYPE_LEVEL_HIGH; + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = parent_hwirq; + parent_fwspec.param[2] = type; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &parent_fwspec); +} + +static const struct irq_domain_ops qcom_pdc_gpio_ops = { + .alloc = qcom_pdc_gpio_alloc, + .free = irq_domain_free_irqs_common, +}; + static int pdc_setup_pin_mapping(struct device_node *np) { int ret, n; @@ -268,9 +348,10 @@ static int pdc_setup_pin_mapping(struct device_node *np) return 0; } -static int qcom_pdc_init(struct device_node *node, struct device_node *parent) +static int qcom_pdc_init(struct device_node *node, struct device_node *parent, + struct pdc_gpio_pin_data *data) { - struct irq_domain *parent_domain, *pdc_domain; + struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; int ret; pdc_base = of_iomap(node, 0); @@ -301,6 +382,18 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) goto fail; } + pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, 0, + PDC_MAX_GPIO_IRQS, + of_fwnode_handle(node), + &qcom_pdc_gpio_ops, data); + if (!pdc_gpio_domain) { + pr_err("%pOF: GIC domain add failed for GPIO domain\n", node); + ret = -ENOMEM; + goto fail; + } + + irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); + return 0; fail: @@ -309,4 +402,93 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) return ret; } -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); +static const struct pdc_gpio_pin_map sdm845_gpio_pdc_map[] = { + { 1, 30 }, + { 3, 31 }, + { 5, 32 }, + { 10, 33 }, + { 11, 34 }, + { 20, 35 }, + { 22, 36 }, + { 24, 37 }, + { 26, 38 }, + { 30, 39 }, + { 31, 117 }, + { 32, 41 }, + { 34, 42 }, + { 36, 43 }, + { 37, 44 }, + { 38, 45 }, + { 39, 46 }, + { 40, 47 }, + { 41, 115 }, + { 43, 49 }, + { 44, 50 }, + { 46, 51 }, + { 48, 52 }, + { 49, 118 }, + { 52, 54 }, + { 53, 55 }, + { 54, 56 }, + { 56, 57 }, + { 57, 58 }, + { 58, 59 }, + { 59, 60 }, + { 60, 61 }, + { 61, 62 }, + { 62, 63 }, + { 63, 64 }, + { 64, 65 }, + { 66, 66 }, + { 68, 67 }, + { 71, 68 }, + { 73, 69 }, + { 77, 70 }, + { 78, 71 }, + { 79, 72 }, + { 80, 73 }, + { 84, 74 }, + { 85, 75 }, + { 86, 76 }, + { 88, 77 }, + { 89, 116 }, + { 91, 79 }, + { 92, 80 }, + { 95, 81 }, + { 96, 82 }, + { 97, 83 }, + { 101, 84 }, + { 103, 85 }, + { 104, 86 }, + { 115, 90 }, + { 116, 91 }, + { 117, 92 }, + { 118, 93 }, + { 119, 94 }, + { 120, 95 }, + { 121, 96 }, + { 122, 97 }, + { 123, 98 }, + { 124, 99 }, + { 125, 100 }, + { 127, 102 }, + { 128, 103 }, + { 129, 104 }, + { 130, 105 }, + { 132, 106 }, + { 133, 107 }, + { 145, 108 }, +}; + +static struct pdc_gpio_pin_data sdm845_gpio_data = { + .size = ARRAY_SIZE(sdm845_gpio_pdc_map), + .map = sdm845_gpio_pdc_map, +}; + +static int qcom_sdm845_pdc_init(struct device_node *node, + struct device_node *parent) +{ + return qcom_pdc_init(node, parent, &sdm845_gpio_data); +} + +IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_sdm845_pdc_init); diff --git a/include/linux/soc/qcom/irq.h b/include/linux/soc/qcom/irq.h new file mode 100644 index 000000000000..bacc9edbce0d --- /dev/null +++ b/include/linux/soc/qcom/irq.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __QCOM_IRQ_H +#define __QCOM_IRQ_H + +#include + +/** + * struct qcom_irq_fwspec - qcom specific irq fwspec wrapper + * @fwspec: irq fwspec + * @mask: if true, keep the irq masked in the gpio controller + * + * Use this structure to communicate between the parent irq chip, MPM or PDC, + * to the gpio chip, TLMM, about the gpio being allocated in the parent + * and if the gpio chip should keep the line masked because the parent irq + * chip is handling everything about the irq line. + */ +struct qcom_irq_fwspec { + struct irq_fwspec fwspec; + bool mask; +}; + +#endif From patchwork Thu Jan 24 20:22:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B1791515 for ; Thu, 24 Jan 2019 20:22:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C1302EEDF for ; Thu, 24 Jan 2019 20:22:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4F9343003B; Thu, 24 Jan 2019 20:22:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E059B2EEDF for ; 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Thu, 24 Jan 2019 20:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361337; bh=xCNFJvpJoucdMcv9Mi45On077kDW81gZ9ob80pgMpYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IR+lyG3q+J6iK/G+ePQ+h4u+6iuD6JaL5cuLe16Q2nDVpRdsjCX8yDZgtDlgzDL8P s+6c5Q7iiTQ2mXNiHH6XCWz7+oOEfWqqyUa0tt7BO5oYTFIk3DxYcGJp+utpjl06dt cDazQT3NbzKrqTr64L7Cxjd8vyHFdYcyqANU1QAk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 677E560C55 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH v2 4/8] dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for GPIO Date: Thu, 24 Jan 2019 13:22:01 -0700 Message-Id: <20190124202205.7940-5-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO routed to the PDC as interrupts that can be used to wake the system up from deep low power modes and suspend. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer --- .../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt index 665aadb5ea28..f0fedbc5d41a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -29,6 +29,11 @@ SDM845 platform. Definition: must be 2. Specifying the pin number and flags, as defined in +- wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + - gpio-controller: Usage: required Value type: @@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc. - PIN CONFIGURATION NODES: The name of each subnode is not important; all subnodes should be enumerated @@ -160,6 +164,7 @@ Example: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wake-parent = <&pdc_intc>; qup9_active: qup9-active { mux { From patchwork Thu Jan 24 20:22:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780063 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 268011399 for ; Thu, 24 Jan 2019 20:22:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 15CDD2EF4D for ; Thu, 24 Jan 2019 20:22:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0A3212F806; Thu, 24 Jan 2019 20:22:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F1D52EF4D for ; Thu, 24 Jan 2019 20:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728035AbfAXUWu (ORCPT ); Thu, 24 Jan 2019 15:22:50 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53240 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729296AbfAXUW0 (ORCPT ); Thu, 24 Jan 2019 15:22:26 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 99DDC61616; Thu, 24 Jan 2019 20:22:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361345; bh=hn7aakuuEpFsknH3CVVshuWEZwXcvU7VVwCs36htKrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M8JoIRhthKNowHG/sWq3e4a6HY8A4+7beVw+deS8DFlqYHXw3Dr3eLzmYo4k/tAx+ rpUTKYIyvqZzAXWVPUdFq6WZ70nYMoW20evZD9aKtwxrObc9Bh1FnXAlW8oKZMgERy hh2/5llTFdjkIJ3gnY7lJIiV5EYEIMN+r/+RVU4E= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E6C0060D80; Thu, 24 Jan 2019 20:22:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361339; bh=hn7aakuuEpFsknH3CVVshuWEZwXcvU7VVwCs36htKrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ud1xCD4QcXhPvk5io45lQdbcWiEBs+d9mYFdxhQiVjoyZJXMJzfGLKKWz8INNA32I 7jX/ZVhBT+I8cMAh8QP6kzabO2dwakalYr2QO5darMmOgsvahDk6kxWWKYxGMzZMah iLAvu9+Rnm5wW5tLD9+mFaBN6VxD2LVt9Exx1KJs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E6C0060D80 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer Subject: [PATCH v2 5/8] drivers: pinctrl: msm: setup GPIO irqchip hierarchy Date: Thu, 24 Jan 2019 13:22:02 -0700 Message-Id: <20190124202205.7940-6-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To allow GPIOs to wakeup the system from suspend or deep idle, the wakeup capable GPIOs are setup in hierarchy with interrupts from the wakeup-parent irqchip. In older SoC's, the TLMM will handover detection to the parent irqchip and in newer SoC's, the parent irqchip may also be active as well as the TLMM and therefore the GPIOs need to be masked at TLMM to avoid duplicate interrupts. To enable both these configurations to exist, allow the parent irqchip to dictate the TLMM irqchip's behavior when masking/unmasking the interrupt. Co-developed-by: Stephen Boyd Signed-off-by: Lina Iyer --- Changes in v2: - Fix bug when unmaksing PDC interrupt --- drivers/pinctrl/qcom/pinctrl-msm.c | 133 ++++++++++++++++++++++++++--- 1 file changed, 120 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index ee8119879c4c..e13bead566aa 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -69,6 +71,7 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(wakeup_masked_irqs, MAX_NR_GPIO); const struct msm_pinctrl_soc_data *soc; void __iomem *regs[MAX_NR_TILES]; @@ -747,6 +750,13 @@ static void msm_gpio_irq_unmask(struct irq_data *d) g = &pctrl->soc->groups[d->hwirq]; + if (d->parent_data) + irq_chip_unmask_parent(d); + + /* Monitored by parent wakeup controller? Keep masked */ + if (test_bit(d->hwirq, pctrl->wakeup_masked_irqs)) + return; + raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_intr_cfg(pctrl, g); @@ -767,6 +777,10 @@ static void msm_gpio_irq_ack(struct irq_data *d) unsigned long flags; u32 val; + /* Handled by parent wakeup controller? Do nothing */ + if (test_bit(d->hwirq, pctrl->wakeup_masked_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -794,6 +808,13 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) g = &pctrl->soc->groups[d->hwirq]; + if (d->parent_data) + irq_chip_set_type_parent(d, type); + + /* Monitored by parent wakeup controller? Keep masked */ + if (test_bit(d->hwirq, pctrl->wakeup_masked_irqs)) + return 0; + raw_spin_lock_irqsave(&pctrl->lock, flags); /* @@ -890,6 +911,9 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) raw_spin_unlock_irqrestore(&pctrl->lock, flags); + if (d->parent_data) + irq_chip_set_wake_parent(d, on); + return 0; } @@ -967,11 +991,86 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; } +static int msm_gpio_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, unsigned int *type) +{ + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count < 2) + return -EINVAL; + *hwirq = fwspec->param[0]; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + return 0; + } + + return -EINVAL; +} + +static int msm_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int ret; + irq_hw_number_t hwirq; + struct gpio_chip *gc = domain->host_data; + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct irq_fwspec *fwspec = arg; + struct qcom_irq_fwspec parent = { }; + unsigned int type; + + ret = msm_gpio_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &pctrl->irq_chip, gc); + if (ret < 0) + return ret; + + if (!domain->parent) + return 0; + + parent.fwspec.fwnode = domain->parent->fwnode; + parent.fwspec.param_count = 2; + parent.fwspec.param[0] = hwirq; + parent.fwspec.param[1] = type; + + ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent); + if (ret) + return ret; + + if (parent.mask) + set_bit(hwirq, pctrl->wakeup_masked_irqs); + + return 0; +} + +/* + * TODO: Get rid of this and push it into gpiochip_to_irq() + */ +static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct irq_fwspec fwspec; + + fwspec.fwnode = of_node_to_fwnode(chip->of_node); + fwspec.param[0] = offset; + fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; + fwspec.param_count = 2; + + return irq_create_fwspec_mapping(&fwspec); +} + +static const struct irq_domain_ops msm_gpio_domain_ops = { + .translate = msm_gpio_domain_translate, + .alloc = msm_gpio_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; int ret; unsigned ngpio = pctrl->soc->ngpios; + struct device_node *dn; if (WARN_ON(ngpio > MAX_NR_GPIO)) return -EINVAL; @@ -986,6 +1085,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); pctrl->irq_chip.name = "msmgpio"; + pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; @@ -994,6 +1094,22 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + chip->irq.chip = &pctrl->irq_chip; + chip->irq.domain_ops = &msm_gpio_domain_ops; + chip->irq.handler = handle_edge_irq; + chip->irq.default_type = IRQ_TYPE_NONE; + + dn = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); + if (dn) { + chip->irq.parent_domain = irq_find_matching_host(dn, + DOMAIN_BUS_WAKEUP); + of_node_put(dn); + if (!chip->irq.parent_domain) + return -EPROBE_DEFER; + + chip->to_irq = msm_gpio_to_irq; + } + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); @@ -1015,26 +1131,17 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) dev_name(pctrl->dev), 0, 0, chip->ngpio); if (ret) { dev_err(pctrl->dev, "Failed to add pin range\n"); - gpiochip_remove(&pctrl->chip); - return ret; + goto fail; } } - ret = gpiochip_irqchip_add(chip, - &pctrl->irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); - gpiochip_remove(&pctrl->chip); - return -ENOSYS; - } - gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, msm_gpio_irq_handler); return 0; +fail: + gpiochip_remove(&pctrl->chip); + return ret; } static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, From patchwork Thu Jan 24 20:22:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 130DC1399 for ; Thu, 24 Jan 2019 20:22:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0277E2A85C for ; Thu, 24 Jan 2019 20:22:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E89C930122; Thu, 24 Jan 2019 20:22:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D7E42A85C for ; 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Thu, 24 Jan 2019 20:22:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361341; bh=zSqqsRDWt5Ma24zl3RMyJ/Vp8szImbQdhVP5OlnAcH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mAyuZ2gW40vXOOUvQXYwT1HtB9WD8oHfgx14wDRTGquPf/Oop2frS458nKx3T/xbR xx5bQFUBDiRXZtiwYYMsVXlWzcfjQNpYoTcVRon1CWhxBaDNIIiiAersGddDIKboL8 BMtRigWb3PLccd8MDX4qYPM36+LnROWHt7i5WCQI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BCB1D60D77 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer Subject: [PATCH v2 6/8] arm64: dts: qcom: add PDC interrupt controller for SDM845 Date: Thu, 24 Jan 2019 13:22:03 -0700 Message-Id: <20190124202205.7940-7-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PDC interrupt controller device bindings for SDM845. Signed-off-by: Lina Iyer --- Changes in v2: - Use updated address specification in reg - Rename to pdc_intc - Sort per address in DT --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c27cbd3bcb0a..e55100c2705e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1534,6 +1534,15 @@ #power-domain-cells = <1>; }; + pdc_intc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tsens0: thermal-sensor@c263000 { compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; reg = <0xc263000 0x1ff>, /* TM */ From patchwork Thu Jan 24 20:22:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CD6D1399 for ; Thu, 24 Jan 2019 20:22:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CD752C857 for ; Thu, 24 Jan 2019 20:22:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 50AE32F806; Thu, 24 Jan 2019 20:22:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF70E2C857 for ; Thu, 24 Jan 2019 20:22:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726271AbfAXUWi (ORCPT ); Thu, 24 Jan 2019 15:22:38 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53484 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728074AbfAXUWe (ORCPT ); Thu, 24 Jan 2019 15:22:34 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0847B61640; Thu, 24 Jan 2019 20:22:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361354; bh=ToehwFPiPS3LTfFWh/KBWOGOiw5Vcyq6Uc3orROdysw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IuQsdFBwKpYJZf1G8K7FoBc+P293KIT9GluTb9U7Qo0BroAmSUYq9NRC/HiLUUPIx otmjuV18PVb4+T1QA+9+JNpyOv4sDhODuI931soSRvJ6KFfwkCSpaYDdKSmfd+WYQs NTYLxTKILK0vdQkKMYPPC4vI3bs6QR808q8RFkW8= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 522AE60D7F; Thu, 24 Jan 2019 20:22:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361342; bh=ToehwFPiPS3LTfFWh/KBWOGOiw5Vcyq6Uc3orROdysw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XyqpclTZ/1ivYX/jim77gfhJIj2lFWN/6Sm0Fb+iN6ey5b+UaPoJI0kDOlgm50/Xn L4rP1SRSVjW5jH+K4ui3StxwgOPI+6nyPur1dN2xQ6Miczp94YRjBYDG+PsGZ64rvT 4NzmJ9yQyuse5eieYEySOvWwU8+uZzYRmIKiPQzM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 522AE60D7F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer Subject: [PATCH v2 7/8] arm64: dts: qcom: setup PDC as wakeup parent for GPIOs for SDM845 Date: Thu, 24 Jan 2019 13:22:04 -0700 Message-Id: <20190124202205.7940-8-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Setup PDC wakeup parent for TLMM for SDM845 SoC. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e55100c2705e..89982f6ee147 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -994,6 +994,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc_intc>; qup_i2c0_default: qup-i2c0-default { pinmux { From patchwork Thu Jan 24 20:22:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10780059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9772F14E5 for ; Thu, 24 Jan 2019 20:22:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87AD82C857 for ; Thu, 24 Jan 2019 20:22:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7AE422F0D7; Thu, 24 Jan 2019 20:22:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 292C42C857 for ; Thu, 24 Jan 2019 20:22:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727889AbfAXUWn (ORCPT ); Thu, 24 Jan 2019 15:22:43 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53590 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728035AbfAXUWj (ORCPT ); Thu, 24 Jan 2019 15:22:39 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 343CE60D3A; Thu, 24 Jan 2019 20:22:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361358; bh=ABF6vgsWKN9GZIGL/rqqe/8FztsVkObvmZPcf2pDx7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kgPJc1oB11duIOWCWwQvIE/dmfB09j1MID6hSroVtD4WdRMzSZi1QEnY/YHDBfLFP 5hOotnzxFRJodgINbgE0XPXmF/1IBDTb/4kaL3TCYfikNJjK9DhV8X1Dh4gltQPrSa 5v+hhLWfO7HlCv4gqjhm6gFVHrIEXiwm9Yn0h3lw= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 072216165F; Thu, 24 Jan 2019 20:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1548361344; bh=ABF6vgsWKN9GZIGL/rqqe/8FztsVkObvmZPcf2pDx7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W5RcAh4ib71h16T+Vr4wCaSfBTzAqsafE5LWuuN8KMipxIN3TRtGu1LRm2d85MjLA cVSN0Rq+ASED1R57XA6MDLnIy9KpGjY9UN5Rok5pxoI3IllNF/LPlZb7XzP9dJJ5aa 5rmNr3qIDx8H1k8I3F+As9FXtTtXu3XtYLmO8YA4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 072216165F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, Lina Iyer Subject: [PATCH v2 8/8] arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 Date: Thu, 24 Jan 2019 13:22:05 -0700 Message-Id: <20190124202205.7940-9-ilina@codeaurora.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> References: <20190124202205.7940-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable PDC interrupt controller for SDM845 devices. The interrupt controller can detect wakeup capable interrupts when the SoC is in a low power state. Signed-off-by: Lina Iyer --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2649b7102565..9e7c58803cd5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -658,6 +658,7 @@ CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SMP2P=y CONFIG_QCOM_SMSM=y +CONFIG_QCOM_PDC=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y