From patchwork Thu Jan 12 12:56:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C50B3C67871 for ; Thu, 12 Jan 2023 12:56:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231960AbjALM44 (ORCPT ); Thu, 12 Jan 2023 07:56:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232416AbjALM4h (ORCPT ); Thu, 12 Jan 2023 07:56:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF9B75F46; Thu, 12 Jan 2023 04:56:33 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2D0E86602DB9; Thu, 12 Jan 2023 12:56:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528192; bh=w39uQHzOIPIO90WhRE4IjTj/4vTR7fwhKBVkNmGEQWM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NBGxuiJVU2ZpQxkVaZeH5CCCS70AGYjTI2usSFgDYvqxG8S1aMWZyj8I5xBnf+XQa A9xd20BDkGD/y+dweWOYWDuG/iqx0M4ZSAXqhbiY4PCZp2ss/gdd6Cfi/J+h4/z0mV 2v1arb4yPppKzNsKyLOPG3o05bVXUVQcqv1Nv8By09CsEXEW/82QCkhHyC9Qjii4UP 9k1B/ZiCjsBeXmpBEtrf/CDIH6uVBePNk2JZ2P1sc1NheN7/vGI+tEkhYTAIWkht+T G1O14WBe3J1zzQFR6kwGybsbOWqEmRYVBqU4PCivCWju4bfEF1fAjb/HVCPDSdYg89 bVDiRKaYnQPaw== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:16 +0100 Subject: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-1-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=6437; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=uy2g9GPcP+lRwPYfgkcuiU1U/soD1j3DQtWijfz/vHI=; b=/pxqbPJRJoRG0ZRyvRot/+yIY4H7+UpAZVlvL+UZ7AKc8JtwF17tqhJfcI1anbbRdRkx4HIuWV2Q xDA5Hg6pCybcCwPBMeJzHeOj63Bav5GFBGgjC+fTds/GMfujTawu X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonas Karlman Add the NV15 pixel format used by the Rockchip Video Decoder for 10-bit buffers. NV15 is a packed 10-bit 4:2:0 Y/CbCr format similar to P010 and P210 but has no padding between components. Instead, luminance and chrominance samples are grouped into 4s so that each group is packed into an integer number of bytes: YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes The '15' suffix refers to the optimum effective bits per pixel which is achieved when the total number of luminance samples is a multiple of 8 for NV15. Signed-off-by: Jonas Karlman Signed-off-by: Sebastian Fricke --- .../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 75 ++++++++++++++++++++++ drivers/media/v4l2-core/v4l2-common.c | 2 + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + include/uapi/linux/videodev2.h | 1 + 4 files changed, 79 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst index f1d5bb7b806d..7d8d228f8063 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst @@ -79,6 +79,13 @@ All components are stored with the same number of bits per component. - Cr, Cb - Yes - Linear + * - V4L2_PIX_FMT_NV15 + - 'NV15' + - 15 + - 4:2:0 + - Cb, Cr + - Yes + - Linear * - V4L2_PIX_FMT_NV12M - 'NM12' - 8 @@ -183,6 +190,7 @@ horizontally. .. _V4L2-PIX-FMT-NV12: .. _V4L2-PIX-FMT-NV21: +.. _V4L2-PIX-FMT-NV15: .. _V4L2-PIX-FMT-NV12M: .. _V4L2-PIX-FMT-NV21M: .. _V4L2-PIX-FMT-P010: @@ -586,6 +594,73 @@ Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian ord - Cb\ :sub:`11` - Cr\ :sub:`11` +.. _V4L2_PIX_FMT_NV15: + +NV15 +---- + +Similar to P010, a semi-planar 10-bit Y/CbCr format, but all components are +packed without any padding between each other. As a side-effect, each group of +4 components are stored over 5 bytes (YYYY or UVUV = 4 * 10 bits = 40 bits = 5 +bytes). + +.. flat-table:: Sample 4x4 NV15 Image + :header-rows: 0 + :stub-columns: 0 + + * - start + 0: + - Y'\ :sub:`00` + - Y'\ :sub:`01` + - Y'\ :sub:`02` + - Y'\ :sub:`03` + * - start + 8: + - Y'\ :sub:`04` + - Y'\ :sub:`10` + - Y'\ :sub:`11` + - Y'\ :sub:`12` + * - start + 16: + - Y'\ :sub:`13` + - Y'\ :sub:`14` + - Y'\ :sub:`20` + - Y'\ :sub:`21` + * - start + 24: + - Y'\ :sub:`22` + - Y'\ :sub:`23` + - Y'\ :sub:`24` + - Y'\ :sub:`30` + * - start + 32: + - Y'\ :sub:`31` + - Y'\ :sub:`32` + - Y'\ :sub:`33` + - Y'\ :sub:`34` + + * - start + 0: + - Cb\ :sub:`00` + - Cr\ :sub:`00` + - Cb\ :sub:`01` + - Cr\ :sub:`01` + * - start + 8: + - Cb\ :sub:`02` + - Cr\ :sub:`02` + - Cb\ :sub:`03` + - Cr\ :sub:`03` + * - start + 16: + - Cb\ :sub:`04` + - Cr\ :sub:`04` + - Cb\ :sub:`10` + - Cr\ :sub:`10` + * - start + 24: + - Cb\ :sub:`11` + - Cr\ :sub:`11` + - Cb\ :sub:`12` + - Cr\ :sub:`12` + * - start + 32: + - Cb\ :sub:`13` + - Cr\ :sub:`13` + - Cb\ :sub:`14` + - Cr\ :sub:`14` + +.. raw:: latex Fully Planar YUV Formats ======================== diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index 40f56e044640..be23e319fb3a 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -262,6 +262,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) /* YUV planar formats */ { .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 }, { .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 }, + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, + .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, { .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 8e0a0ff62a70..1c80ad78ef00 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1343,6 +1343,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break; case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break; case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break; + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break; case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break; case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break; case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 1befd181a4cc..e9731286dc77 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -621,6 +621,7 @@ struct v4l2_pix_format { /* two planes -- one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ From patchwork Thu Jan 12 12:56:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6C11C61DB3 for ; Thu, 12 Jan 2023 12:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232006AbjALM46 (ORCPT ); Thu, 12 Jan 2023 07:56:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231434AbjALM4h (ORCPT ); Thu, 12 Jan 2023 07:56:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88EC7AE4A; Thu, 12 Jan 2023 04:56:36 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2E7356602DBC; Thu, 12 Jan 2023 12:56:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528195; bh=TMBuSYYQgufdE8ilX8+9MkfvSRLEsm/O1NHAsGj+B/Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XOPL1XeRQInEt43srKZYrnrk2C/E2t6TlKO5p4bXvoEV/zBpFhHONeClKtTqj6JBz 4o16E9P1tWHpCvOrfc/+9iIjNnCFUEt3alSQI9jpYrBa97dU0lspWglEQG7xskQ+Vh XgKtlMfpbzLXq5q5BhUkbtzWVHVDkvZEYFxOjhJNvkgCXtU1KoG3oR4M3PnfACexdl 9q7Korw+75cBpygJm/0frQyYKChkqDwnB9NkXuNDQiZrBS9TrMrOaalV1OFgwXKasX moplnbm24XFPXMFZ9qSAmZAwk4rp/hYi5DzvT741iOfZxvOz2Ti1iZicgEHEOkRIEQ VFf5gm44ncdsA== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:17 +0100 Subject: [PATCH v2 02/12] media: v4l2-common: Add helpers to calculate bytesperline and sizeimage MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-2-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=4683; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=LcMmGvBIJq4nek85HGURC0+BOvaXuS5YxkC2HDnyM4I=; b=21yB2ximJGHXO2qRmwC71wOACLdxQEDfraCFxz9My9OOeP/Bg30IT6qXnRdRmTEICA6UNWxjEJjI 0AsKrLSDBeIJqIIhK3dU2M8+aYSDn/AyK7/xOhcyFbJLtFv1L49Z X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonas Karlman Add helper functions to calculate plane bytesperline and sizeimage, these new helpers consider block width and height when calculating plane bytesperline and sizeimage. This prepares support for a new pixel format added in next patch that makes use of block width and height. Signed-off-by: Jonas Karlman --- drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++++++------------------ 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index be23e319fb3a..12c1d2f409b0 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -340,6 +340,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf return info->block_h[plane]; } +static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, + unsigned int width) +{ + unsigned int hdiv = plane ? info->hdiv : 1; + unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane], + v4l2_format_block_width(info, plane) * + v4l2_format_block_height(info, plane)); + + return DIV_ROUND_UP(bytes, hdiv); +} + +static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, + unsigned int height) +{ + unsigned int vdiv = plane ? info->vdiv : 1; + unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane)); + + return DIV_ROUND_UP(lines, vdiv); +} + +static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, + unsigned int width, unsigned int height) +{ + return v4l2_format_plane_width(info, plane, width) * + v4l2_format_plane_height(info, plane, height); +} + void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, const struct v4l2_frmsize_stepwise *frmsize) { @@ -375,37 +402,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, if (info->mem_planes == 1) { plane = &pixfmt->plane_fmt[0]; - plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0]; + plane->bytesperline = v4l2_format_plane_width(info, 0, width); plane->sizeimage = 0; - for (i = 0; i < info->comp_planes; i++) { - unsigned int hdiv = (i == 0) ? 1 : info->hdiv; - unsigned int vdiv = (i == 0) ? 1 : info->vdiv; - unsigned int aligned_width; - unsigned int aligned_height; - - aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); - aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); - - plane->sizeimage += info->bpp[i] * - DIV_ROUND_UP(aligned_width, hdiv) * - DIV_ROUND_UP(aligned_height, vdiv); - } + for (i = 0; i < info->comp_planes; i++) + plane->sizeimage += + v4l2_format_plane_size(info, i, width, height); } else { for (i = 0; i < info->comp_planes; i++) { - unsigned int hdiv = (i == 0) ? 1 : info->hdiv; - unsigned int vdiv = (i == 0) ? 1 : info->vdiv; - unsigned int aligned_width; - unsigned int aligned_height; - - aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); - aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); - plane = &pixfmt->plane_fmt[i]; plane->bytesperline = - info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv); - plane->sizeimage = - plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); + v4l2_format_plane_width(info, i, width); + plane->sizeimage = plane->bytesperline * + v4l2_format_plane_height(info, i, height); } } return 0; @@ -429,22 +438,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, pixfmt->width = width; pixfmt->height = height; pixfmt->pixelformat = pixelformat; - pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0]; + pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); pixfmt->sizeimage = 0; - for (i = 0; i < info->comp_planes; i++) { - unsigned int hdiv = (i == 0) ? 1 : info->hdiv; - unsigned int vdiv = (i == 0) ? 1 : info->vdiv; - unsigned int aligned_width; - unsigned int aligned_height; - - aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); - aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); - - pixfmt->sizeimage += info->bpp[i] * - DIV_ROUND_UP(aligned_width, hdiv) * - DIV_ROUND_UP(aligned_height, vdiv); - } + for (i = 0; i < info->comp_planes; i++) + pixfmt->sizeimage += + v4l2_format_plane_size(info, i, width, height); return 0; } EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); From patchwork Thu Jan 12 12:56:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47A82C54EBD for ; Thu, 12 Jan 2023 12:57:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231743AbjALM5A (ORCPT ); Thu, 12 Jan 2023 07:57:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231651AbjALM4k (ORCPT ); Thu, 12 Jan 2023 07:56:40 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E901B641D; Thu, 12 Jan 2023 04:56:39 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9E63B6602DBA; Thu, 12 Jan 2023 12:56:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528198; bh=8FFms7ZFvtbGRTeN4REh/YGhyU+oeFdqYWO/CK2KT8c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hXDggCyHhkjfeIswJAT/y/OZ3Uv10V8Cte6Wd/pyHY8rOY6dr9GSn0wpvJqTPLhAn huVgJgPug9zwf6cZosazKC86t1j54jjlPgFuIsy+QRuqZT1+iPX9piPWAJMlNjqjuG OScE+wYlc6cVvt/TBZahO964vjW3VE37MbhQ94bfU0QB+iyniOOy6KJEcIgZxSjqQK fotcKNvAIDnTYGKuQZXOYWdvsbeIDsUTfJ2+wAx0S2d8E1/NX8hW0NhtfMSaHK0Ur2 Dao5hfPydn5QXY2ImcTCrAm24Q/K0DZKTPJECRS5W5DOD0MUySUoXpHHjb1QhUGGu/ qieM9+NzZLXQg== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:18 +0100 Subject: [PATCH v2 03/12] staging: media: rkvdec: Helper for buffer queue busy check MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-3-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=2269; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=8FFms7ZFvtbGRTeN4REh/YGhyU+oeFdqYWO/CK2KT8c=; b=ub/wDdTpC9jeMsoCSRmmqPKTVKH8soQUtOakduE6Kmcgt/JvOwM+tMckRDcgsVcmdLW9umjznn05 a7TSEWbUC2GDJJri/M43YYI86BB6vTZEyOuxzEaRrXkA+V76F2vz X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Implement a helper function, wrapping around getting a vb2 queue and checking whether it is busy, to reduce the amount of code duplication in the driver. Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index 7bab7586918c..c849f6c20279 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,17 @@ #include "rkvdec.h" #include "rkvdec-regs.h" +static int rkvdec_queue_busy(struct rkvdec_ctx *ctx, enum v4l2_buf_type buf_type) +{ + struct vb2_queue *vq; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, buf_type); + if (vb2_is_busy(vq)) + return -EBUSY; + else + return 0; +} + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -311,13 +322,10 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, struct v4l2_format *f) { struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - struct vb2_queue *vq; int ret; /* Change not allowed if queue is busy */ - vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, - V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); - if (vb2_is_busy(vq)) + if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) != 0) return -EBUSY; ret = rkvdec_try_capture_fmt(file, priv, f); @@ -335,7 +343,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; const struct rkvdec_coded_fmt_desc *desc; struct v4l2_format *cap_fmt; - struct vb2_queue *peer_vq, *vq; + struct vb2_queue *vq; int ret; /* @@ -354,8 +362,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, * queue, we can't allow doing so when the CAPTURE queue has buffers * allocated. */ - peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); - if (vb2_is_busy(peer_vq)) + if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) != 0) return -EBUSY; ret = rkvdec_try_output_fmt(file, priv, f); From patchwork Thu Jan 12 12:56:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49C0FC54EBD for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528201; bh=AVEg4DSMK0gqYca27eD54R157QB5YV2sWChYYaBFpmI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LM1vgt+pOaabBAJ85FdbLo9wq5mUT0w0x5nAszJ37VGijYHKcIXfdOuoVfBt0gFKM 6V0TsNYP9Ceg5NVgCMb5s0IZWo5rZ1dbo1r5fvwCxpo0VEyHldVhngCZ0XpZuXi7cB aNfDgYu++punO6h4oxFkcZ7KjeWXaYxHFhfFxOuq9Le8mNU8nv04VPbmGJwPlU5+L9 H+xIH29P1Jx2f8ei32MK42TPAd34QOcwHrFPJGwMZzJFHYJ2kzjYxAbPEAb3fIUCjd 6xgX3fHo389Rsu+JdAl860N6hgqDWhXpo04SbF0lJbmDCfInbfMID2Zwd3C7+fJY9z H5eTXOOfjX8wQ== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:19 +0100 Subject: [PATCH v2 04/12] staging: media: rkvdec: Block start streaming until both queues run MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-4-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=1025; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=AVEg4DSMK0gqYca27eD54R157QB5YV2sWChYYaBFpmI=; b=4fInMsBgcT6jf30p/7TvMJW1s4sjmIUMu2MIX6uCwRuxM7iBhvTpC/00Nu4xtEZo2TrulpGwWaVw pfVDB17lDTsDfzQFYB1UAn0aetGnBIbCWNnkmQVCdoIqa/IR7mT0 X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Ensure that both the CAPTURE and the OUTPUT queue are running (e.g. busy -> have buffers allocated) before starting the actual streaming process. Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index c849f6c20279..e0e95d06e216 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -562,6 +562,13 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) if (V4L2_TYPE_IS_CAPTURE(q->type)) return 0; + /* + * Make sure that both the output and the capture queue are running + */ + if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) == 0 || + rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) == 0) + return -EAGAIN; + desc = ctx->coded_fmt_desc; if (WARN_ON(!desc)) return -EINVAL; From patchwork Thu Jan 12 12:56:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC9EFC54EBD for ; Thu, 12 Jan 2023 12:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232111AbjALM5I (ORCPT ); Thu, 12 Jan 2023 07:57:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231582AbjALM4q (ORCPT ); Thu, 12 Jan 2023 07:56:46 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13DAADEC9; Thu, 12 Jan 2023 04:56:46 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id BF6A36602DBB; Thu, 12 Jan 2023 12:56:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528204; bh=GtQZT2nN8QVz9LN/mUHoZT/CUo6gIVaMFXE6EeZP8+w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=f3+wXOfId313ZjMh/uj5YyArXZ6QYSDBTl+YVjkRP7vNA+aP9XlSN7x31pOqpO/i0 U3XO5+2Qtclgr/r+hSRfU/AN+LfDrxKmTKLaRJuIt2EUryjNtbN9xgdsOhK7h445kP 9FvsvDF8lu94aevG1t2G5NA3coRX2H2u8epSH5srfqlProjYdCGS9eNDwMT2iSdB9l 1BJQVrrxC3m+tqhcXg5cESXNUPLHcm/3LfdAyEYwt3VxQXOv7lH85o7SeNe7WSrkmm MCLS5aMFnELvLxFYZq+jkhufKL3Ahp0BsIi7a8uSaCkF3/IrYc/t70/+3uFD2ZFm3S qwQKrW4BVuUHA== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:20 +0100 Subject: [PATCH v2 05/12] staging: media: rkvdec: Add SPS structure to internal context MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-5-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=801; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=GtQZT2nN8QVz9LN/mUHoZT/CUo6gIVaMFXE6EeZP8+w=; b=OjC0Py2sReXxL+AYZYLXHyPGdbsOwyx+uqaYl4Y1kEeTAbxmGZkntvZnq3XKEtOeM85QWw+Ztya4 wmZhOV/OBs/BI5WNTao0NajI7uAMZXp/pcpslmQlBD+AoRw3Kxzc X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Prepare storing the SPS structure for HEVC & H264 in the internal context of the rkvdec instance. This structure is used to figure out which capture queue format is appropriate for decoding. Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index 633335ebb9c4..332126e7b812 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -105,6 +105,7 @@ struct rkvdec_ctx { struct v4l2_ctrl_handler ctrl_hdl; struct rkvdec_dev *dev; void *priv; + void *sps; }; static inline struct rkvdec_ctx *fh_to_rkvdec_ctx(struct v4l2_fh *fh) From patchwork Thu Jan 12 12:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD68C54EBD for ; Thu, 12 Jan 2023 12:57:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231660AbjALM5G (ORCPT ); Thu, 12 Jan 2023 07:57:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231679AbjALM4v (ORCPT ); Thu, 12 Jan 2023 07:56:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10D2939F81; Thu, 12 Jan 2023 04:56:49 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id BA61F6602DB1; Thu, 12 Jan 2023 12:56:47 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528207; bh=Da6QtFYOuId0q8spuTSgR9gP0GfvHSM7GfQl76avmIU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dHzAuxLpAj79iY9LVET5QkBL9VPhVA1ioJQwPn2iFXHU4fDdFn9jzLrSF87VecJ2y 1g4/d6x53E0SC3CNDg90z3NYtWNIMSmbDKQL9hU958IXnDuafam/WNGpmJbUwSYfrB 7XAEnIX34wDmWKijisW8hShchRspOnId3nGqxD0wNFptvHvdLBIZ2hP5HxLP0mbtsB 8vfs4fP10dIJERtoHYCSiY6fm95Y2n60qeW6NRfZAfazo04rhOlRNAw44VAk+2TSC5 Y/yrD0dScreg28gKD8HaSfR1/oASNvZ/pY/7vp1xqbDHuvtoJq1cHwigZI9Im2CVlN e0Za9curbjdng== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:21 +0100 Subject: [PATCH v2 06/12] staging: media: rkvdec: Add a valid pixel format check as callback MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-6-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=3923; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=Da6QtFYOuId0q8spuTSgR9gP0GfvHSM7GfQl76avmIU=; b=Ei9OhrN5lMhBxVdjk4LBAl2cBQ2833Mt1irFmo2edGvikdXUqvhqqNyW0wxQ84YZ9drS3FRc9gZs 0Ef1O9TjAyFyFdBeAO/IeTnNjUYTD+y6bGpxE1du+FdS0vTDEOur X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Provide a callback for codec variant drivers to indicate the correct output pixel-format. It will either utilize the SPS structure stored via the S_CTRL IOCTL or return the default pixel-format. Signed-off-by: Jonas Karlman Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.c | 45 +++++++++++++++++++++++++++++------ drivers/staging/media/rkvdec/rkvdec.h | 1 + 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index e0e95d06e216..a46f918926a2 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -38,6 +38,20 @@ static int rkvdec_queue_busy(struct rkvdec_ctx *ctx, enum v4l2_buf_type buf_type return 0; } +/* + * Use the current SPS, set by the user via the VIDIOC_S_CTRL IOCTL, + * to determine the optimal pixel-format. Each codec is responsible + * for choosing the appropriate pixel-format for a given parameter set. + */ +static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx) +{ + const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; + + if (coded_desc->ops->valid_fmt) + return coded_desc->ops->valid_fmt(ctx); + return ctx->coded_fmt_desc->decoded_fmts[0]; +} + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -200,8 +214,9 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->decoded_fmt; + u32 valid_fmt = rkvdec_get_valid_fmt(ctx); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); + rkvdec_reset_fmt(ctx, f, valid_fmt); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, ctx->coded_fmt_desc->decoded_fmts[0], @@ -260,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, if (WARN_ON(!coded_desc)) return -EINVAL; - for (i = 0; i < coded_desc->num_decoded_fmts; i++) { - if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) - break; - } + if (ctx->sps) { + pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx); + } else { + for (i = 0; i < coded_desc->num_decoded_fmts; i++) { + if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) + break; + } - if (i == coded_desc->num_decoded_fmts) - pix_mp->pixelformat = coded_desc->decoded_fmts[0]; + if (i == coded_desc->num_decoded_fmts) + pix_mp->pixelformat = coded_desc->decoded_fmts[0]; + } /* Always apply the frmsize constraint of the coded end. */ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); @@ -435,6 +454,18 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, if (WARN_ON(!ctx->coded_fmt_desc)) return -EINVAL; + /* + * According to the specification the driver can only return formats + * that are supported by both the current encoded format and the + * provided controls + */ + if (ctx->sps) { + if (f->index) + return -EINVAL; + f->pixelformat = rkvdec_get_valid_fmt(ctx); + return 0; + } + if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) return -EINVAL; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index 332126e7b812..e353a4403e5b 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); + u32 (*valid_fmt)(struct rkvdec_ctx *ctx); int (*start)(struct rkvdec_ctx *ctx); void (*stop)(struct rkvdec_ctx *ctx); int (*run)(struct rkvdec_ctx *ctx); From patchwork Thu Jan 12 12:56:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2108CC54EBD for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528211; bh=L7yUo+Zy/WcujWFgTjyCDy8xs7O/0zxdTxZIPyBpgSk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P22F8isb/92Gjf4AENjAKMgGWDmFwC0qIFR7iMIgoD9bBf9rFm664WPACZSLAr8E2 qfajrA7qgYi5RoMLhupOs4cAP6zWL05znXgyChFWLKpziSUCzxy+2hrjfXNN7dXHWa 0zHFrQsP6FZvz+0ew0u+No52ksa3xqB8VjYR74M0OaS8qN0CRB7YojDQSo6ZoAJGtr EjQL9xHzvjcnsFjrFiMR93+H8rstCGkRnMCshoJu05db/zuBOPM9wqLLatm//9x0TE jcl1H3/M/lAi6hMVNz6qQI+rELbEZeur5dMwA2IIuaY/+ydg2CE91YAxI1jb1XVVY/ wI3oUA0Z1tQ7A== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:22 +0100 Subject: [PATCH v2 07/12] staging: media: rkvdec: Add a routine to fetch SPS attributes as a callback MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-7-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=2158; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=L7yUo+Zy/WcujWFgTjyCDy8xs7O/0zxdTxZIPyBpgSk=; b=BQBpXVr9E3Fn2xXJWy5utkd9tAkwvp5ZmvKorxmvoteBpq2FSBbzIP1smBJqXM3OVtIox4UT7+qw qNzHyG+6AZYM2KNQS3zMp/Hpk0VCVIgsydDjavwdm+2IKSiWNpT1 X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a callback for each codec variant, that fetches basic information like resolution, bit-depth and sub-sampling from a SPS structure. This data is used to verify whether a new SPS structure is valid. Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.c | 10 ++++++++++ drivers/staging/media/rkvdec/rkvdec.h | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index a46f918926a2..e8c750a7343a 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -52,6 +52,16 @@ static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx) return ctx->coded_fmt_desc->decoded_fmts[0]; } +static int rkvdec_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps, + struct sps_attributes *attributes) +{ + const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; + + if (coded_desc->ops->get_sps_attributes) + return coded_desc->ops->get_sps_attributes(ctx, sps, attributes); + return 0; +} + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index e353a4403e5b..7b6702c360fd 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -63,10 +63,20 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) base.vb.vb2_buf); } +struct sps_attributes { + unsigned int width; + unsigned int height; + unsigned int luma_bitdepth; + unsigned int chroma_bitdepth; + unsigned int subsampling; +}; + struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); u32 (*valid_fmt)(struct rkvdec_ctx *ctx); + int (*get_sps_attributes)(struct rkvdec_ctx *ctx, void *sps, + struct sps_attributes *attributes); int (*start)(struct rkvdec_ctx *ctx); void (*stop)(struct rkvdec_ctx *ctx); int (*run)(struct rkvdec_ctx *ctx); From patchwork Thu Jan 12 12:56:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 941CFC54EBC for ; Thu, 12 Jan 2023 12:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232241AbjALM5Q (ORCPT ); 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b=iFWWVGd0PM+MpyqfisZJ8ZATeRpN9ueRYPloz+zab6riogtw9/H/jMvGclFgaXL27 Iecy/xV1AUO4NhXd2HknaBrbA0KNS+e4fS8zCri1Gh8xW2Nod13mZ+LxeV5n8F5yjc +cURbe6rY59CdaVeW9cYcNKzo9bRGgp7M0wXHO+aM/vRP9rOQbnS+mBCiM8vilslz/ G93/nO79P39GLfJEMTbEWrRV42SsXRH753uhUx1YgS5OC67wi014XyGjHPU2+rin1H 7X5xq9KghhFbMBukRC+/7069InJwB7ymRkR6URNI299eTDzRWoAjRSU5t8Ca41MoFF wfWWZlcj7oERg== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:23 +0100 Subject: [PATCH v2 08/12] staging: media: rkvdec: Add a valid SPS check as a callback MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-8-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=3157; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=NR4NgmAwqSKt432W3wHLkNsbDlb7Ku6yU6hoKm5PFhw=; b=IQDkaNXJm1EiGyDmWoVKY4f+RD7CQ6A9pSeRltErtvX0pqcjW0RWXs2BZkhZonGnlhJ66v4IbQHv T3KBCKDWAP+0YbahHXPuYtABeVBdfI70Rp3wIpLpoKQRRGG5TI/Z X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a callback for each codec variant, that ensures that a given format is compatible with the SPS that is stored in the context of the instance. This is used for two scenarios: - New output queue format is set, which is incompatible with the currently stored SPS - Start streaming is called but the SPS doesn't match the current format anymore Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.c | 35 +++++++++++++++++++++++++++++++++++ drivers/staging/media/rkvdec/rkvdec.h | 1 + 2 files changed, 36 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index e8c750a7343a..8d948bcc4e46 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -52,6 +52,26 @@ static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx) return ctx->coded_fmt_desc->decoded_fmts[0]; } +static int rkvdec_sps_check(struct rkvdec_ctx *ctx, struct v4l2_pix_format_mplane *pix_mp) +{ + const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; + + /* + * When a codec doesn't implement the SPS check, handle it as if no + * SPS exists for the codec. + */ + if (coded_desc->ops->sps_check) { + if (!ctx->sps) + return -EINVAL; + + if (!pix_mp) + pix_mp = &ctx->decoded_fmt.fmt.pix_mp; + return coded_desc->ops->sps_check(ctx, ctx->sps, pix_mp); + } + + return 0; +} + static int rkvdec_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps, struct sps_attributes *attributes) { @@ -375,6 +395,13 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, struct vb2_queue *vq; int ret; + /* + * When the new output format doesn't match the existing SPS stored in + * the context, then the SPS needs to be reset by user-space. + */ + if (rkvdec_sps_check(ctx, &f->fmt.pix_mp) < 0) + ctx->sps = NULL; + /* * In order to support dynamic resolution change, the decoder admits * a resolution change, as long as the pixelformat remains. Can't be @@ -603,6 +630,14 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) if (V4L2_TYPE_IS_CAPTURE(q->type)) return 0; + /* + * An incompatible SPS at this point is invalid, abort the process. + */ + if (rkvdec_sps_check(ctx, NULL) < 0) { + ctx->sps = NULL; + return -EINVAL; + } + /* * Make sure that both the output and the capture queue are running */ diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index 7b6702c360fd..d74821f9fd0b 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -75,6 +75,7 @@ struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); u32 (*valid_fmt)(struct rkvdec_ctx *ctx); + int (*sps_check)(struct rkvdec_ctx *ctx, void *sps, struct v4l2_pix_format_mplane *pix_mp); int (*get_sps_attributes)(struct rkvdec_ctx *ctx, void *sps, struct sps_attributes *attributes); int (*start)(struct rkvdec_ctx *ctx); From patchwork Thu Jan 12 12:56:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D28FAC54EBC for ; Thu, 12 Jan 2023 12:57:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232195AbjALM5O (ORCPT ); Thu, 12 Jan 2023 07:57:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231934AbjALM5A (ORCPT ); Thu, 12 Jan 2023 07:57:00 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF9C638BC; Thu, 12 Jan 2023 04:56:58 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7A1636602DBA; Thu, 12 Jan 2023 12:56:57 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528217; bh=19U+A00eX7GomcVZ4hwuwzX1XI4Jf/K9mYqNNP1Mc6c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=d7S8hzbl9CZf9tINvxTrwAjOPyZGpYeDkOqtO15LV6A+mhlACIc8cO4x/l0QhLMDV RKtUTsC7nqNRAguPa6HrSTppiAP+1MA8FDk9ZHJ6IeS3YiPDk9+Z0RHqgXca364iyY kPl9M+S+OxTFPmU58ZejKKYo/UXx+XjYE7gInFp8dzFpr6PjgyppTspRMHeBo6B0vR wGh0SrbnkraovnN/1QBadr3FDZT4PVFJePnsNXM/Ey47S0Kgc8cBk0q4HU3KAmJ+AT CSQoFV/3kRVQDouTMqx+p/j/egX/DTbgfWmQixUEaho3i+DQosC1e3d9d3RjYAvhRy txFyOGKwsixbA== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:24 +0100 Subject: [PATCH v2 09/12] staging: media: rkvdec: h264: Add callbacks for h264 MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-9-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=5576; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=19U+A00eX7GomcVZ4hwuwzX1XI4Jf/K9mYqNNP1Mc6c=; b=q/7dHZEZC7Om5sfZ593nhkIVNVGwUmKnKRnaq5y/97IVmaJeS8raTGDHwcL5TyDW1rqoym9zCAKB cUypHMjIB7YqWAGX5s3xun+/JDEUBTd5vaUDxzWqeURvM7C16Agw X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Implement the valid format and sps validation callbacks for H264. H264 already has a SPS validation function, adjust it to fit the function the declaration and add error messages. Additionally, add a function to fetch attributes from the SPS in a human readable format to make the code more self documenting. Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec-h264.c | 105 ++++++++++++++++++++++------- 1 file changed, 80 insertions(+), 25 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c index 4fc167b42cf0..17b215874ddd 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -1026,40 +1026,80 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, return 0; } -static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, - const struct v4l2_ctrl_h264_sps *sps) +/* + * Convert some fields from the SPS structure into human readable attributes. + */ +static int rkvdec_h264_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps, + struct sps_attributes *attributes) +{ + struct v4l2_ctrl_h264_sps *h264_sps = sps; + unsigned int width = (h264_sps->pic_width_in_mbs_minus1 + 1) * 16; + unsigned int height = (h264_sps->pic_height_in_map_units_minus1 + 1) * 16; + /* + * When frame_mbs_only_flag is not set, this is field height, + * which is half the final height (see (7-18) in the + * specification) + */ + if (!(h264_sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) + height *= 2; + + attributes->width = width; + attributes->height = height; + attributes->luma_bitdepth = h264_sps->bit_depth_luma_minus8 + 8; + attributes->chroma_bitdepth = h264_sps->bit_depth_chroma_minus8 + 8; + switch (h264_sps->chroma_format_idc) { + case 0: + attributes->subsampling = 400; + break; + case 1: + attributes->subsampling = 420; + break; + case 2: + attributes->subsampling = 422; + break; + case 3: + attributes->subsampling = 444; + break; + }; + return 0; +} + +static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, void *sps, + struct v4l2_pix_format_mplane *pix_mp) { - unsigned int width, height; + struct sps_attributes attributes = {0}; + + rkvdec_h264_get_sps_attributes(ctx, sps, &attributes); /* * TODO: The hardware supports 10-bit and 4:2:2 profiles, * but it's currently broken in the driver. * Reject them for now, until it's fixed. */ - if (sps->chroma_format_idc > 1) - /* Only 4:0:0 and 4:2:0 are supported */ + if (attributes.subsampling > 420) { + dev_err(ctx->dev->dev, + "Only 4:0:0 and 4:2:0 subsampling schemes are supported, got: %d\n", + attributes.subsampling); return -EINVAL; - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) - /* Luma and chroma bit depth mismatch */ + } + if (attributes.luma_bitdepth != attributes.chroma_bitdepth) { + dev_err(ctx->dev->dev, + "Luma and chroma bit depth mismatch, luma %d, chroma %d\n", + attributes.luma_bitdepth, attributes.chroma_bitdepth); return -EINVAL; - if (sps->bit_depth_luma_minus8 != 0) - /* Only 8-bit is supported */ + } + if (attributes.luma_bitdepth != 8) { + dev_err(ctx->dev->dev, "Only 8-bit H264 formats supported, SPS %d\n", + attributes.luma_bitdepth); return -EINVAL; + } - width = (sps->pic_width_in_mbs_minus1 + 1) * 16; - height = (sps->pic_height_in_map_units_minus1 + 1) * 16; - - /* - * When frame_mbs_only_flag is not set, this is field height, - * which is half the final height (see (7-18) in the - * specification) - */ - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) - height *= 2; - - if (width > ctx->coded_fmt.fmt.pix_mp.width || - height > ctx->coded_fmt.fmt.pix_mp.height) + if (attributes.width > pix_mp->width || attributes.height > pix_mp->height) { + dev_err(ctx->dev->dev, + "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.", + attributes.width, attributes.height, pix_mp->width, pix_mp->height); return -EINVAL; + } return 0; } @@ -1077,8 +1117,9 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx) if (!ctrl) return -EINVAL; - ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); - if (ret) + ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps, + &ctx->coded_fmt.fmt.pix_mp); + if (ret < 0) return ret; h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); @@ -1175,10 +1216,21 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) return 0; } +static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx) +{ + /* + * Only 8 bit 4:0:0 and 4:2:0 formats supported for now. + * The SPS is validated at a different function thus we can assume that + * it is correct. + */ + return V4L2_PIX_FMT_NV12; +} + static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) { if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) - return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); + return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps, + &ctx->coded_fmt.fmt.pix_mp); return 0; } @@ -1189,4 +1241,7 @@ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { .stop = rkvdec_h264_stop, .run = rkvdec_h264_run, .try_ctrl = rkvdec_h264_try_ctrl, + .valid_fmt = rkvdec_h264_valid_fmt, + .sps_check = rkvdec_h264_validate_sps, + .get_sps_attributes = rkvdec_h264_get_sps_attributes, }; From patchwork Thu Jan 12 12:56:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D24E3C54EBC for ; Thu, 12 Jan 2023 12:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231443AbjALM5U (ORCPT ); Thu, 12 Jan 2023 07:57:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232099AbjALM5C (ORCPT ); Thu, 12 Jan 2023 07:57:02 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F020DEC9; Thu, 12 Jan 2023 04:57:01 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3DE736602DBC; Thu, 12 Jan 2023 12:57:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528220; bh=s+EQFfhyAuhQn7YicE5XWPWi6yC+rHeMTsHsU87SIDc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Eyo/iGEhDGKhLVHuYynBUcGxCA0HxniOOj0YZEwal5LZ6soLeyCp4E7HfoRrLRjJE +7CPbCElblJWl5FLdwz5ki6VcLqRHunXVfOk/eeKydjm0nZd0xMDazQUYyNDBj6KxP pOezH+PpLuIjcqzHCmBymhOJ5i4eCyoG8Tdk8lhF2uVIwCX9ezQEfpfV95CsbSWAL6 ho+dTUNgvObJF1HFAQd6jiIyZ+etRpjnfwynf0OCN1ddZHY6lqgq7fAPdhBJSa+TWf B9yaXLU7wS/F0pZHXWBbL4XLWNpAP/pUEEVBjcnVkSgjvhIFuzNkBDg4tft8sNJKIL 2S8s260THKobA== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:25 +0100 Subject: [PATCH v2 10/12] staging: media: rkvdec: Wrapper for pixel format preparation MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-10-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=2354; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=s+EQFfhyAuhQn7YicE5XWPWi6yC+rHeMTsHsU87SIDc=; b=oUnmXcIum/7DI0U2ej2rfr/P1PixLPwOAObjiKfMcquGxYFvoCILsKjwmY7ITmfCmaF2++etqDiM TEkWc0fzCCv3jOdJWB4kONL9IPeV96X/47kcNH//+CB+vl9DcchG X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Reduce code duplication by creating a wrapper around the preparation of the `v4l2_pix_format_mplane` structure and the calculation of the image size. Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/rkvdec.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index 8d948bcc4e46..b303c6e0286d 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,17 @@ #include "rkvdec.h" #include "rkvdec-regs.h" +static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, + struct v4l2_pix_format_mplane *pix_mp) +{ + v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, + pix_mp->width, pix_mp->height); + pix_mp->plane_fmt[0].sizeimage += 128 * + DIV_ROUND_UP(pix_mp->width, 16) * + DIV_ROUND_UP(pix_mp->height, 16); + pix_mp->field = V4L2_FIELD_NONE; +} + static int rkvdec_queue_busy(struct rkvdec_ctx *ctx, enum v4l2_buf_type buf_type) { struct vb2_queue *vq; @@ -248,13 +259,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) rkvdec_reset_fmt(ctx, f, valid_fmt); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, - ctx->coded_fmt_desc->decoded_fmts[0], - ctx->coded_fmt.fmt.pix_mp.width, - ctx->coded_fmt.fmt.pix_mp.height); - f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * - DIV_ROUND_UP(f->fmt.pix_mp.height, 16); + f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; + f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; + rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); } static int rkvdec_enum_framesizes(struct file *file, void *priv, @@ -324,13 +331,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, &pix_mp->height, &coded_desc->frmsize); - v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, - pix_mp->width, pix_mp->height); - pix_mp->plane_fmt[0].sizeimage += - 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); - pix_mp->field = V4L2_FIELD_NONE; + rkvdec_fill_decoded_pixfmt(ctx, pix_mp); return 0; } From patchwork Thu Jan 12 12:56:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02E41C54EBD for ; Thu, 12 Jan 2023 12:57:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232658AbjALM5n (ORCPT ); Thu, 12 Jan 2023 07:57:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232322AbjALM5d (ORCPT ); Thu, 12 Jan 2023 07:57:33 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0501A5130D; Thu, 12 Jan 2023 04:57:05 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id B56856602DB1; Thu, 12 Jan 2023 12:57:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528223; bh=KAJmQ51TusAs/OBMlUcE6FAB/zXgKsXdACD+yS0cJJs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=abuLMAtI+0Ssmb0Qet0J4hPnVAdraA31EB3fvZ/zDjZvc2UyLQpbuGpOiFbxXhOqc S9NUy9xnqLwAqNNtyQFTUiP7+lJpwbtRYRwTevw/9OIF62BM43kv9v/Y8O5Dan8zJD zy3+0jfREptqFrzuMIuITsGVocKGn8VB9qrbRTUXlbka8E6UkheBghOkMgwWlfjhJ6 bvU2BcEkzGokpvaFOODMzAKJe3+Xa3+EXgkqaaYK3u3a9zVb6+KOCsN5F9v9WFMQIW dAqSQiVNpyzqaypDHC12Df8AFUhQ4HVKlMv25c6RbKfbpJOAj4W627U9Xoa2Xkd1Up n9oHDOyuMFo1Q== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:26 +0100 Subject: [PATCH v2 11/12] staging: media: rkvdec: Enable S_CTRL IOCTL MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-11-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=3704; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=KAJmQ51TusAs/OBMlUcE6FAB/zXgKsXdACD+yS0cJJs=; b=3Q8dYQ7JJV91gBKcZI7SdzmsUpSj8tSF8FmAoOpA4+8doicKKzpHZXOKqfCS3w0RSMTTwbQ545S3 /EmOOuLQCwWk/liG7p+9gfjw2YEBe+DwYIkP0cAdOuppKUob+jYn X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Enable user-space to set the SPS of the current byte-stream on the decoder. This action will enable the decoder to pick the optimal pixel-format for the capture queue, whenever it is required. Signed-off-by: Sebastian Fricke Signed-off-by: Jonas Karlman --- drivers/staging/media/rkvdec/rkvdec.c | 81 +++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index b303c6e0286d..3d413c5ad1d2 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -93,6 +93,79 @@ static int rkvdec_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps, return 0; } +static int rkvdec_set_sps(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + struct v4l2_pix_format_mplane *pix_mp; + struct sps_attributes attributes = {0}; + void *new_sps = NULL; + + /* + * SPS structures are not filled until the control handler is set up + */ + if (!ctx->fh.ctrl_handler) + return 0; + + switch (ctrl->id) { + case V4L2_CID_STATELESS_H264_SPS: + new_sps = (void *)ctrl->p_new.p_h264_sps; + break; + case V4L2_CID_STATELESS_HEVC_SPS: + new_sps = (void *)ctrl->p_new.p_hevc_sps; + break; + default: + dev_err(ctx->dev->dev, "Unsupported stateless control ID: %x\n", ctrl->id); + return -EINVAL; + }; + rkvdec_get_sps_attributes(ctx, new_sps, &attributes); + + /* + * Providing an empty SPS is valid but we do not store it. + */ + if (attributes.width == 0 && attributes.height == 0) + return 0; + + pix_mp = &ctx->decoded_fmt.fmt.pix_mp; + + /* + * SPS must match the provided format dimension, if it doesn't userspace has to + * first reset the output format + */ + if ((attributes.width > pix_mp->width) || (attributes.height > pix_mp->height)) { + dev_err(ctx->dev->dev, + "Dimension mismatch. [%s SPS] W: %d, H: %d, [Format] W: %d, H: %d)\n", + ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ? "HEVC" : "H264", + attributes.width, attributes.height, pix_mp->width, pix_mp->height); + return -EINVAL; + } + + if (ctx->sps && pix_mp->pixelformat == rkvdec_get_valid_fmt(ctx)) { + /* + * Userspace is allowed to change the SPS at any point, if the + * pixel format doesn't differ from the format in the context, + * just accept the change even if buffers are queued + */ + ctx->sps = new_sps; + } else { + /* + * Do not accept changing the SPS, while buffers are queued, + * when the new SPS would cause switching the CAPTURE pixel format + */ + if (pix_mp->pixelformat != rkvdec_get_valid_fmt(ctx)) { + if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)) + return -EBUSY; + } + ctx->sps = new_sps; + /* + * For the initial SPS setting and when the pixel format is + * changed adjust the pixel format stored in the context + */ + pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx); + rkvdec_fill_decoded_pixfmt(ctx, pix_mp); + } + + return 0; +} + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -104,8 +177,16 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + + return rkvdec_set_sps(ctx, ctrl); +} + static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { .try_ctrl = rkvdec_try_ctrl, + .s_ctrl = rkvdec_s_ctrl, }; static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { From patchwork Thu Jan 12 12:56:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 13097961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D209C54EBD for ; Thu, 12 Jan 2023 12:58:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232135AbjALM6U (ORCPT ); Thu, 12 Jan 2023 07:58:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232822AbjALM5u (ORCPT ); Thu, 12 Jan 2023 07:57:50 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98EC539F81; Thu, 12 Jan 2023 04:57:08 -0800 (PST) Received: from localhost (89-26-75-29.goll.dyn.salzburg-online.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 099706602DB9; Thu, 12 Jan 2023 12:57:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673528227; bh=pm+8+YSV1gNiZGXugXBzMsEYogDn1ApTCdetzlcVJrQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VnsGrgCHFmlORitNIU9rHOIym3yFT5s3PzDpx5cwZOHT6rIih7/2i6AM6oIe5UIGu CelHh94pV0zGkElZaxLSAO30kovBidEmjUiI0MrhdB7Jpc+c/VXW7q0EMnLf5F8S6m ITi0wNU5zA7XrlajUuRGcKIUxRgHA07s/KbcOqrYYPePblDar63nemG1qc1kvNNj3O wI8fiapnTqintzm76PDST+RGhfnOvoUl9NZYlZrWkDrW8fmqOCXmGqDuj69jw3Ak3R /MUuaVHpbIkopxkQUGJogP4Sz/QA3uUsfTF3MQcqnCEEPiTK9HLM991wmyC2sFZYth 7/dUJynw4yHcg== From: Sebastian Fricke Date: Thu, 12 Jan 2023 13:56:27 +0100 Subject: [PATCH v2 12/12] staging: media: rkvdec: Add HEVC backend MIME-Version: 1.0 Message-Id: <20230101-patch-series-v2-6-2-rc1-v2-12-fa1897efac14@collabora.com> References: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> In-Reply-To: <20230101-patch-series-v2-6-2-rc1-v2-0-fa1897efac14@collabora.com> To: Mauro Carvalho Chehab , Ezequiel Garcia , Greg Kroah-Hartman Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, Jonas Karlman , Alex Bee , Nicolas Dufresne , Collabora Kernel-domain , Robert Beckett , Laurent Pinchart , Andrzej Pietrasiewicz , Benjamin Gaignard , Sebastian Fricke X-Mailer: b4 0.11.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1673528186; l=212070; i=sebastian.fricke@collabora.com; s=linux-media; h=from:subject:message-id; bh=pm+8+YSV1gNiZGXugXBzMsEYogDn1ApTCdetzlcVJrQ=; b=ivYlPMVhGccrpB90PzjCCFa5sBo/IrUkhl7ipx96EORF/rVhRoRMPJkz5C1D2+3iXO1p1j6uBlLv U9BczBMaAT3ZKDW06UMe06Iuxdzxsn4MlYCNyE6u8c42K53/K7By X-Developer-Key: i=sebastian.fricke@collabora.com; a=ed25519; pk=pYXedPwrTtErcj7ERYeo/IpTrpe4QbJuEzSB52fslBg= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The Rockchip VDEC supports the HEVC codec with the Main and Main10 Profile up to Level 5.1 High Tier: 4096x2304@60 fps. Add the backend for that format to the decoder. Signed-off-by: Jonas Karlman Signed-off-by: Alex Bee Signed-off-by: Nicolas Dufresne Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/Makefile | 2 +- drivers/staging/media/rkvdec/TODO | 11 +- drivers/staging/media/rkvdec/rkvdec-hevc-data.c | 1845 +++++++++++++++++++++++ drivers/staging/media/rkvdec/rkvdec-hevc.c | 910 +++++++++++ drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + drivers/staging/media/rkvdec/rkvdec.c | 72 + drivers/staging/media/rkvdec/rkvdec.h | 1 + 7 files changed, 2834 insertions(+), 8 deletions(-) diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile index cb86b429cfaa..a77122641d14 100644 --- a/drivers/staging/media/rkvdec/Makefile +++ b/drivers/staging/media/rkvdec/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o -rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO index 2c0779383276..58652251241b 100644 --- a/drivers/staging/media/rkvdec/TODO +++ b/drivers/staging/media/rkvdec/TODO @@ -1,11 +1,8 @@ -* Support for HEVC is planned for this driver. - - Given the V4L controls for that CODEC will be part of - the uABI, it will be required to have the driver in staging. - - For this reason, we are keeping this driver in staging for now. - * Evaluate introducing a helper to consolidate duplicated code in rkvdec_request_validate and cedrus_request_validate. The helper needs to the driver private data associated with the videobuf2 queue, from a media request. + +* Add support for other hardware revisions (like RK3288 etc.) + +* Fix concurrent decoding for the HEVC codec diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c new file mode 100644 index 000000000000..d3b7760063ef --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c @@ -0,0 +1,1845 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder driver + * + * Copyright (C) 2023 Collabora, Ltd. + * Sebastian Fricke + */ +#include + +#define RKV_CABAC_TABLE_SIZE 27456 + +static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { + 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, + 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, + 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 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0x40, 0x40, 0x40, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x27, 0x07, 0x40, + 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, 0x07, 0x27, 0x40, 0x17, + 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f, + 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f, + 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f, + 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, + 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, + 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, + 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, + 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, + 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, + 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 index 000000000000..d3802ba613ab --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -0,0 +1,910 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder HEVC backend + * + * Copyright (C) 2023 Collabora, Ltd. + * Sebastian Fricke + * + * Copyright (C) 2019 Collabora, Ltd. + * Boris Brezillon + * + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Jeffy Chen + */ + +#include + +#include "rkvdec.h" +#include "rkvdec-regs.h" +#include "rkvdec-hevc-data.c" + +/* Size in u8/u32 units. */ +#define RKV_SCALING_LIST_SIZE 1360 +#define SCALING_LIST_SIZE_NUM 4 +#define RKV_PPS_SIZE (80 / 4) +#define RKV_PPS_LEN 64 +#define RKV_RPS_SIZE (32 / 4) +#define RKV_RPS_LEN 600 +#define RKV_PPS_MAX_COLUMNS 20 +#define RKV_PPS_MAX_ROWS 22 +#define RKV_RPS_MAX_REFERENCES 15 +#define RKV_MAX_DEPTH_IN_BYTES 2 + +struct rkvdec_sps_pps_packet { + u32 info[RKV_PPS_SIZE]; +}; + +struct rkvdec_rps_packet { + u32 info[RKV_RPS_SIZE]; +}; + +struct rkvdec_ps_field { + u16 offset; + u8 len; +}; + +#define PS_FIELD(_offset, _len) \ + ((struct rkvdec_ps_field){ _offset, _len }) + +/* SPS */ +#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) +#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) +#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) +#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) +#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) +#define BIT_DEPTH_LUMA PS_FIELD(36, 4) +#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) +#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) +#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) +#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) +#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) +#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) +#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) +#define AMP_ENABLED_FLAG PS_FIELD(66, 1) +#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) +#define PCM_ENABLED_FLAG PS_FIELD(68, 1) +#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) +#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) +#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) +#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) +#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) +#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) +#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) +#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) +#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) +#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) +#define PPS_MBZ_1 PS_FIELD(100, 7) +#define PPS_MBO_1 PS_FIELD(107, 21) +/* PPS */ +#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) +#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) +#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) +#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) +#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) +#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) +#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) +#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) +#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) +#define INIT_QP_MINUS26 PS_FIELD(163, 7) +#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) +#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) +#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) +#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) +#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) +#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) +#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) +#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) +#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) +#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) +#define TILES_ENABLED_FLAG PS_FIELD(190, 1) +#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) +#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) +#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) +#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) +#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) +#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) +#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) +#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) +#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) +#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) +#define PPS_MBZ_2 PS_FIELD(209, 3) +#define NUM_TILE_COLUMNS PS_FIELD(212, 5) +#define NUM_TILE_ROWS PS_FIELD(217, 5) +#define PPS_M_MODE PS_FIELD(222, 2) +#define PPS_MBO_2 PS_FIELD(224, 30) +#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8) +#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8) +#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) +#define PPS_MBO_3 PS_FIELD(624, 16) + +/* Data structure describing auxiliary buffer format. */ +struct rkvdec_hevc_priv_tbl { + u8 cabac_table[RKV_CABAC_TABLE_SIZE]; + u8 scaling_list[RKV_SCALING_LIST_SIZE]; + struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; + struct rkvdec_rps_packet rps[RKV_RPS_LEN]; +}; + +struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; + const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; + int num_slices; +}; + +struct rkvdec_hevc_ctx { + struct rkvdec_aux_buf priv_tbl; + struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; +}; + +struct scaling_factor { + u8 scalingfactor0[1248]; + u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ + u8 scalingdc[12]; /*N1005 Vienna Meeting*/ + u8 reserved[4]; /*16Bytes align*/ +}; + +static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) +{ + u8 bit = field.offset % 32, word = field.offset / 32; + u64 mask = GENMASK_ULL(bit + field.len - 1, bit); + u64 val = ((u64)value << bit) & mask; + + buf[word] &= ~mask; + buf[word] |= val; + if (bit + field.len > 32) { + buf[word + 1] &= ~(mask >> 32); + buf[word + 1] |= val >> 32; + } +} + +static void assemble_hw_pps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_pps *pps = run->pps; + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; + struct rkvdec_sps_pps_packet *hw_ps; + u8 pcm_enabled = 0; + u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; + u32 width, height, max_min_cb_size, x, pic_in_cts_width, pic_in_cts_height; + u32 log2_min_cu_qp_delta_size, scaling_distance; + dma_addr_t scaling_list_address; + int i; + u32 tmp_w = 0; + u32 prev_w = 0; + u32 tmp_h = 0; + u32 prev_h = 0; + u16 column_width[RKV_PPS_MAX_COLUMNS] = {0}; + u16 row_height[RKV_PPS_MAX_ROWS] = {0}; + + /* + * HW read the SPS/PPS information from PPS packet index by PPS id. + * offset from the base can be calculated by PPS_id * 80 (size per PPS + * packet unit). so the driver copy SPS/PPS information to the exact PPS + * packet unit for HW accessing. + */ + hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; + memset(hw_ps, 0, sizeof(*hw_ps)); + + min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; + width = sps->pic_width_in_luma_samples; + height = sps->pic_height_in_luma_samples; + max_min_cb_size = sps->log2_diff_max_min_luma_coding_block_size; + +#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) + /* write sps */ + WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); + WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); + WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); + WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); + WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); + WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); + WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); + WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, + LOG2_MAX_PIC_ORDER_CNT_LSB); + WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, + LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); + WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, + LOG2_MIN_LUMA_CODING_BLOCK_SIZE); + WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, + LOG2_MIN_TRANSFORM_BLOCK_SIZE); + WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, + LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); + WRITE_PPS(sps->max_transform_hierarchy_depth_inter, + MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); + WRITE_PPS(sps->max_transform_hierarchy_depth_intra, + MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), + SCALING_LIST_ENABLED_FLAG); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), + AMP_ENABLED_FLAG); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), + SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); + pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED); + WRITE_PPS(pcm_enabled, PCM_ENABLED_FLAG); + WRITE_PPS(pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0, + PCM_SAMPLE_BIT_DEPTH_LUMA); + WRITE_PPS(pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0, + PCM_SAMPLE_BIT_DEPTH_CHROMA); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), + PCM_LOOP_FILTER_DISABLED_FLAG); + WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, + LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); + WRITE_PPS(pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0, + LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); + WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), + LONG_TERM_REF_PICS_PRESENT_FLAG); + WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), + SPS_TEMPORAL_MVP_ENABLED_FLAG); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), + STRONG_INTRA_SMOOTHING_ENABLED_FLAG); + WRITE_PPS(0, PPS_MBZ_1); + WRITE_PPS(0x1fffff, PPS_MBO_1); + + /* write pps */ + WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); + WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), + DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), + OUTPUT_FLAG_PRESENT_FLAG); + WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), + SIGN_DATA_HIDING_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), + CABAC_INIT_PRESENT_FLAG); + WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, + NUM_REF_IDX_L0_DEFAULT_ACTIVE); + WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, + NUM_REF_IDX_L1_DEFAULT_ACTIVE); + WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), + CONSTRAINED_INTRA_PRED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), + TRANSFORM_SKIP_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), + CU_QP_DELTA_ENABLED_FLAG); + + ctb_log2_size_y = min_cb_log2_size_y + + sps->log2_diff_max_min_luma_coding_block_size; + ctb_size_y = 1 << ctb_log2_size_y; + log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; + WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); + WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); + WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), + PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), + WEIGHTED_PRED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), + WEIGHTED_BIPRED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), + TRANSQUANT_BYPASS_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), + TILES_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), + ENTROPY_CODING_SYNC_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), + PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), + LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), + DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), + PPS_DEBLOCKING_FILTER_DISABLED_FLAG); + WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); + WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), + LISTS_MODIFICATION_PRESENT_FLAG); + WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), + SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); + WRITE_PPS(0, PPS_MBZ_2); + WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); + WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); + WRITE_PPS(3, PPS_M_MODE); + WRITE_PPS(0x3fffffff, PPS_MBO_2); + + if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { + if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) { + x = 1 << (min_cb_log2_size_y + max_min_cb_size); + pic_in_cts_width = (width + x - 1) / (x); + pic_in_cts_height = (height + x - 1) / (x); + for (i = 0; i <= pps->num_tile_columns_minus1; i++) { + tmp_w = ((i + 1) * pic_in_cts_width) / + (pps->num_tile_columns_minus1 + 1); + column_width[i] = tmp_w - prev_w - 1; + prev_w = tmp_w; + } + for (i = 0; i <= pps->num_tile_rows_minus1; i++) { + tmp_h = ((i + 1) * pic_in_cts_height) / + (pps->num_tile_rows_minus1 + 1); + row_height[i] = tmp_h - prev_h - 1; + prev_h = tmp_h; + } + } else { + for (i = 0; i <= pps->num_tile_columns_minus1; i++) + column_width[i] = pps->column_width_minus1[i]; + for (i = 0; i <= pps->num_tile_rows_minus1; i++) + row_height[i] = pps->row_height_minus1[i]; + } + } else { + column_width[0] = + ((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1; + row_height[0] = + ((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1; + } + + for (i = 0; i < RKV_PPS_MAX_COLUMNS; i++) + WRITE_PPS(column_width[i], COLUMN_WIDTH(i)); + for (i = 0; i < RKV_PPS_MAX_ROWS; i++) + WRITE_PPS(row_height[i], ROW_HEIGHT(i)); + + scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); + scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; + WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); + WRITE_PPS(0xffff, PPS_MBO_3); +} + +/* + * Creation of the Reference Picture Set memory blob for the hardware. + * The layout looks like this: + * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference) + * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references + * + 4 bits of the 13th reference) + * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and + * 21 bits for L1 (4 references + first bit of 5) + * [3] 32 bits of padding with 0s + * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11) + * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references) + * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32) + * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12) + * number of references (bit 13 - 16), remaining 16 bits of padding with 0s + * [7] 32 bits of padding with 0s + * + * Thus we have to set up padding in between reference 5 of the L1 list. + */ +static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; + struct rkvdec_rps_packet *hw_ps; + int i, j; + unsigned int lowdelay; + +#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) + +#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1) +#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4) +#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1) +#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4) + +#define LOWDELAY PS_FIELD(182, 1) +#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) +#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) +#define NUM_RPS_POC PS_FIELD(202, 4) + + for (j = 0; j < run->num_slices; j++) { + uint st_bit_offset = 0; + uint num_l0_refs = 0; + uint num_l1_refs = 0; + + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; + + if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { + num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; + + if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) + num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; + + lowdelay = 1; + } else { + lowdelay = 0; + } + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + + for (i = 0; i < num_l0_refs; i++) { + const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]]; + + WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); + + if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt) + lowdelay = 0; + } + + for (i = 0; i < num_l1_refs; i++) { + const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]]; + int is_long_term = + !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); + + WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); + + if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt) + lowdelay = 0; + } + + WRITE_RPS(lowdelay, LOWDELAY); + + if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { + if (sl_params->short_term_ref_pic_set_size) + st_bit_offset = sl_params->short_term_ref_pic_set_size; + else if (sps->num_short_term_ref_pic_sets > 1) + st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); + } + + WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, + LONG_TERM_RPS_BIT_OFFSET); + WRITE_RPS(sl_params->short_term_ref_pic_set_size, + SHORT_TERM_RPS_BIT_OFFSET); + + WRITE_RPS(decode_params->num_poc_st_curr_before + + decode_params->num_poc_st_curr_after + + decode_params->num_poc_lt_curr, + NUM_RPS_POC); + } +} + +/* + * Flip one or more matrices along their main diagonal and flatten them + * before writing it to the memory. + * Convert: + * ABCD AEIM + * EFGH => BFJN => AEIMBFJNCGKODHLP + * IJKL CGKO + * MNOP DHLP + */ +static void rotate_and_flatten_matrices(u8 *output, const u8 *input, int matrices, int row_length) +{ + int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; + + matrix_size = row_length * row_length; + for (i = 0; i < matrices; i++) { + row = 0; + x_offset = 0; + matrix_offset = i * matrix_size; + for (j = 0; j < matrix_size; j++) { + y_offset = j - (row * row_length); + rot_index = y_offset * row_length + x_offset; + new_value = *(input + i * matrix_size + j); + output[matrix_offset + rot_index] = *(input + i * matrix_size + j); + if ((j + 1) % row_length == 0) { + row += 1; + x_offset += 1; + } + } + } +} + +static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) +{ + int offset = 0; + + rotate_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); + offset = 6 * 16 * sizeof(u8); + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); + offset += 6 * 64 * sizeof(u8); + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, 6, 8); + offset += 6 * 64 * sizeof(u8); + /* Add a 128 byte padding with 0s between the two 32x32 matrices */ + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, 1, 8); + offset += 64 * sizeof(u8); + memset(output + offset, 0, 128); + offset += 128 * sizeof(u8); + rotate_and_flatten_matrices(output + offset, + (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), + 1, 8); + offset += 64 * sizeof(u8); + memset(output + offset, 0, 128); +} + +/* + * Required layout: + * A = scaling_list_dc_coef_16x16 + * B = scaling_list_dc_coef_32x32 + * 0 = Padding + * + * A, A, A, A, A, A, B, 0, 0, B, 0, 0 + */ +static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) +{ + u8 list_32x32[6] = {0}; + + memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); + list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; + list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; + memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); +} + +static void translate_scaling_list(struct scaling_factor *output, + const struct v4l2_ctrl_hevc_scaling_matrix *input) +{ + assemble_scalingfactor0(output->scalingfactor0, input); + memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); + assemble_scalingdc(output->scalingdc, input); + memset(output->reserved, 0, 4 * sizeof(u8)); +} + +static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; + u8 *dst; + + if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) + return; + + dst = tbl->scaling_list; + translate_scaling_list((struct scaling_factor *)dst, scaling); + + memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); +} + +static struct vb2_buffer * +get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, unsigned int dpb_idx) +{ + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; + struct vb2_buffer *buf = NULL; + + if (dpb_idx < decode_params->num_active_dpb_entries) + buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); + + /* + * If a DPB entry is unused or invalid, the address of current destination + * buffer is returned. + */ + if (!buf) + return &run->base.bufs.dst->vb2_buf; + + return buf; +} + +static void config_registers(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; + const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; + const struct v4l2_pix_format_mplane *dst_fmt; + struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; + struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; + const struct v4l2_format *f; + dma_addr_t rlc_addr; + dma_addr_t refer_addr; + u32 rlc_len; + u32 hor_virstride; + u32 ver_virstride; + u32 y_virstride; + u32 uv_virstride; + u32 yuv_virstride; + u32 offset; + dma_addr_t dst_addr; + u32 reg, i; + + reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); + + f = &ctx->decoded_fmt; + dst_fmt = &f->fmt.pix_mp; + hor_virstride = dst_fmt->plane_fmt[0].bytesperline; + ver_virstride = dst_fmt->height; + y_virstride = hor_virstride * ver_virstride; + uv_virstride = y_virstride / 2; + yuv_virstride = y_virstride + uv_virstride; + + reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | + RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | + RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); + + /* config rlc base address */ + rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); + + rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); + reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); + + /* config cabac table */ + offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); + + /* config output base address */ + dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); + + reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); + + reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); + + /* config ref pic address */ + for (i = 0; i < 15; i++) { + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); + + if (i < 4 && decode_params->num_active_dpb_entries) { + reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); + reg = (reg >> (i * 4)) & 0xf; + } else { + reg = 0; + } + + refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); + writel_relaxed(refer_addr | reg, rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); + + reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? + dpb[i].pic_order_cnt_val : 0); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); + } + + reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); + + /* config hw pps address */ + offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_PPS_BASE); + + /* config hw rps address */ + offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_RPS_BASE); + + reg = RKVDEC_AXI_DDR_RDATA(0); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); + + reg = RKVDEC_AXI_DDR_WDATA(0); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); +} + +static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; + + fmt->num_planes = 1; + if (!fmt->plane_fmt[0].sizeimage) + fmt->plane_fmt[0].sizeimage = + fmt->width * fmt->height * RKV_MAX_DEPTH_IN_BYTES; + return 0; +} + +static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_hevc_priv_tbl *priv_tbl; + struct rkvdec_hevc_ctx *hevc_ctx; + int ret; + + hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); + if (!hevc_ctx) + return -ENOMEM; + + priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), + &hevc_ctx->priv_tbl.dma, GFP_KERNEL); + if (!priv_tbl) { + ret = -ENOMEM; + goto err_free_ctx; + } + + hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); + hevc_ctx->priv_tbl.cpu = priv_tbl; + memset(priv_tbl, 0, sizeof(*priv_tbl)); + memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, sizeof(rkvdec_hevc_cabac_table)); + + ctx->priv = hevc_ctx; + return 0; + +err_free_ctx: + kfree(hevc_ctx); + return ret; +} + +static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) +{ + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_dev *rkvdec = ctx->dev; + + dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, + hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); + kfree(hevc_ctx); +} + +static int rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + struct v4l2_ctrl *ctrl; + + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); + run->decode_params = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->decode_params)) + return -EINVAL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); + run->slices_params = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->slices_params)) + return -EINVAL; + run->num_slices = ctrl->new_elems; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SPS); + run->sps = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->sps)) + return -EINVAL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_PPS); + run->pps = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->pps)) + return -EINVAL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->scaling_matrix)) + return -EINVAL; + + rkvdec_run_preamble(ctx, &run->base); + return 0; +} + +static void start_hardware(struct rkvdec_dev *rkvdec) +{ + void __iomem *register_base_addr = rkvdec->regs; + struct delayed_work *watchdog_worker = &rkvdec->watchdog_work; + /* + * RkVDEC error detection doesn't work really well and seems racy + * and unstable. Disable it. + */ + writel_relaxed(0, register_base_addr + RKVDEC_REG_STRMD_ERR_EN); + writel_relaxed(0, register_base_addr + RKVDEC_REG_H264_ERR_E); + + schedule_delayed_work(watchdog_worker, msecs_to_jiffies(2000)); + + writel(1, register_base_addr + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); + writel(1, register_base_addr + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); + + /* Start decoding! */ + writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | + RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, + register_base_addr + RKVDEC_REG_INTERRUPT); +} + +static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx) +{ + const struct v4l2_ctrl_hevc_sps *sps = ctx->sps; + + /* + * No need to check chroma_format_idc, currently only 4:2:0 formats + * supported. + */ + if (sps && sps->bit_depth_luma_minus8 == 2) + return V4L2_PIX_FMT_NV15; + else + return V4L2_PIX_FMT_NV12; +} + +/* + * Convert some fields from the SPS structure into human readable attributes. + */ +static int rkvdec_hevc_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps, + struct sps_attributes *attributes) +{ + struct v4l2_ctrl_hevc_sps *hevc_sps = sps; + unsigned int width = hevc_sps->pic_width_in_luma_samples; + unsigned int height = hevc_sps->pic_height_in_luma_samples; + + if (!(width % 64 == 0)) + width = ALIGN(width, 64); + + if (!(height % 16 == 0)) + height = ALIGN(height, 16); + + attributes->width = width; + attributes->height = height; + attributes->luma_bitdepth = hevc_sps->bit_depth_luma_minus8 + 8; + attributes->chroma_bitdepth = hevc_sps->bit_depth_chroma_minus8 + 8; + switch (hevc_sps->chroma_format_idc) { + case 0: + attributes->subsampling = 400; + break; + case 1: + attributes->subsampling = 420; + break; + case 2: + attributes->subsampling = 422; + break; + case 3: + attributes->subsampling = 444; + break; + }; + + return 0; +} + +static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, void *sps, + struct v4l2_pix_format_mplane *pix_mp) +{ + struct sps_attributes attributes = {0}; + + rkvdec_hevc_get_sps_attributes(ctx, sps, &attributes); + + if ((attributes.width != pix_mp->width) || (attributes.height != pix_mp->height)) { + dev_err(ctx->dev->dev, + "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.", + attributes.width, attributes.height, pix_mp->width, pix_mp->height); + return -EINVAL; + } + + if ((attributes.luma_bitdepth == 8 && pix_mp->pixelformat != V4L2_PIX_FMT_NV12) || + (attributes.luma_bitdepth == 10 && pix_mp->pixelformat != V4L2_PIX_FMT_NV15)) { + dev_err(ctx->dev->dev, + "Incompatible SPS bit-depth, SPS %d, Pixel format %d.", + attributes.luma_bitdepth, + pix_mp->pixelformat == V4L2_PIX_FMT_NV12 ? 8 : 10); + return -EINVAL; + } + + return 0; +} + +static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + struct sps_attributes attributes = {0}; + + rkvdec_hevc_get_sps_attributes(ctx, ctrl->p_new.p_hevc_sps, &attributes); + + if (attributes.subsampling > 420) + return -EINVAL; + if (attributes.luma_bitdepth != 8 && attributes.luma_bitdepth != 10) + return -EINVAL; + return 0; +} + +static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_hevc_run run; + int ret; + + ret = rkvdec_hevc_run_preamble(ctx, &run); + if (ret) { + dev_err(ctx->dev->dev, "Missing required controls for the RkVDEC HEVC decoder."); + return ret; + } + + assemble_hw_scaling_list(ctx, &run); + assemble_hw_pps(ctx, &run); + assemble_hw_rps(ctx, &run); + config_registers(ctx, &run); + rkvdec_run_postamble(ctx, &run.base); + start_hardware(rkvdec); + + return 0; +} + +const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { + .adjust_fmt = rkvdec_hevc_adjust_fmt, + .start = rkvdec_hevc_start, + .stop = rkvdec_hevc_stop, + .run = rkvdec_hevc_run, + .try_ctrl = rkvdec_hevc_try_ctrl, + .valid_fmt = rkvdec_hevc_valid_fmt, + .sps_check = rkvdec_hevc_validate_sps, + .get_sps_attributes = rkvdec_hevc_get_sps_attributes, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h index 15b9bee92016..83bf790ed9b7 100644 --- a/drivers/staging/media/rkvdec/rkvdec-regs.h +++ b/drivers/staging/media/rkvdec/rkvdec-regs.h @@ -43,6 +43,7 @@ #define RKVDEC_RLC_MODE BIT(11) #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) #define RKVDEC_MODE(x) (((x) & 0x03) << 20) +#define RKVDEC_MODE_HEVC 0 #define RKVDEC_MODE_H264 1 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index 3d413c5ad1d2..6462dd83ea6d 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -230,6 +231,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { }, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { + .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, + .cfg.name = "Slice parameters", + .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, + .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, + .cfg.dims = { 600 }, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, + .cfg.ops = &rkvdec_ctrl_ops, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, + .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, + .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + }, +}; + +static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { + .ctrls = rkvdec_hevc_ctrl_descs, + .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), +}; + +static const u32 rkvdec_hevc_decoded_fmts[] = { + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_NV15, +}; + static const struct rkvdec_ctrls rkvdec_h264_ctrls = { .ctrls = rkvdec_h264_ctrl_descs, .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), @@ -260,6 +317,21 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_HEVC_SLICE, + .frmsize = { + .min_width = 64, + .max_width = 4096, + .step_width = 64, + .min_height = 64, + .max_height = 2304, + .step_height = 16, + }, + .ctrls = &rkvdec_hevc_ctrls, + .ops = &rkvdec_hevc_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts = rkvdec_hevc_decoded_fmts, + }, { .fourcc = V4L2_PIX_FMT_H264_SLICE, .frmsize = { diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index d74821f9fd0b..9cf354968d52 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -135,6 +135,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; +extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; #endif /* RKVDEC_H_ */