From patchwork Mon Jan 16 10:14:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13102860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 863E7C54EBE for ; Mon, 16 Jan 2023 10:16:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=VCUK9NeeEwUI94y7hbXIWt/YZZlTp9LOOkQWJWq8uKw=; b=bExVOj30vHsWlx cWK1m6W3J6GTBxTWA4cO1Ys6AtOz3jE2KQF6bWtd+nG/VBK1l9BfaCSfy1vhac/lPAmA2tvtfS+GO fI6oHkJ/fQQ81lYgJXElO7THIXfEckFJESBqUun8Fqr+o7OIWlJcUPDJxBhbBcUoES9uWw0L6dIUw OsFJupoYeceMF9bqPHpuqSILd7PccSBVAPrEOkIpp5B6XAXxuMh+kE54w+cOOJehi2fVX4uU6LIBM 0RspmaJAP48gJPwhlFWCkfjoT0dlcf9DzcwpfP/TXXMskLMr3NqeFsDONIoW4klRL08pXvA7AN9yk wTPHaTkcqUzKeOBMStnw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHMVx-009b18-7s; Mon, 16 Jan 2023 10:14:53 +0000 Received: from phobos.denx.de ([85.214.62.61]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHMVl-009axY-Re for linux-arm-kernel@lists.infradead.org; Mon, 16 Jan 2023 10:14:44 +0000 Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id DFAFB82131; Mon, 16 Jan 2023 11:14:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1673864080; bh=RNZ5KUbWGfJeIfLoBqoYBtZU2bduuORytr5mCWizxBQ=; h=From:To:Cc:Subject:Date:From; b=QdTBsPygUy9xxlZFVy/YJdp32n3obL1ejGBWeSvjqweasAck7aWvLGHB9R/U1V0Cz PMb7Hi7joUhXdm03tmQ0uzLrGWpu44YZp84Y6dI6s8+x9G14mIzqVGQ0vUFdVVXs95 pcbjgj8CIll9ylpU7aXNPlPMGVIweLM9s9NWvJ1WR+wjSVIPu43uqvlKq6YkNjTy/s Po6/0bbsXNbcCoY6nmbLzk1hGn3uFhkqfkMo/5cxWJzQZyAndGOuKsCwpoQCEx767X SSaTUvDTIet/ub7kn8Qz5kHA8poTUFU3lavfNMnjelKIOh3LdSrgBSGv8KMkC/jSAa cD1huJJfwLWTQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexander Stein , Fabio Estevam , Peng Fan , Richard Zhu , Shawn Guo , NXP Linux Team Subject: [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Date: Mon, 16 Jan 2023 11:14:21 +0100 Message-Id: <20230116101422.46257-1-marex@denx.de> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230116_021442_305589_F8D5F57A X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Move the PCIe clock-names property from various DTs into SoC dtsi to reduce duplication. In case of a couple of boards, reorder the clock so they match the order in yaml DT bindings. Reviewed-by: Alexander Stein # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts Signed-off-by: Marek Vasut Reviewed-by: Richard Zhu --- Cc: Fabio Estevam Cc: Peng Fan Cc: Richard Zhu Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Alex - Fix venice build - Add default pcie clock entry into dtsi V3: - Drop clocks altogether from imx8mm-innocomm-wb15.dtsi imx8mm-phyboard-polis-rdk.dts imx8mm-verdin.dtsi as they are identical to imx8mm.dtsi --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi | 3 --- arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 3 --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 5 ++--- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ++++ 15 files changed, 26 insertions(+), 43 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 169f047fbca50..bc531175ff765 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -241,9 +241,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk_gated>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 9889319d4f045..b1f2beb40a98f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -905,9 +905,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcieclk 0>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e0b604ac0da4f..0ce3005d578d2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -360,9 +360,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi index 44e87b1568e79..299752aa82772 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi @@ -210,9 +210,6 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>, - <&clk IMX8MM_CLK_PCIE1_AUX>; - clock-names = "pcie", "pcie_bus", "pcie_aux"; fsl,max-link-speed = <1>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 4a3df2b77b0be..266129b4a70d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -175,9 +175,6 @@ &pcie0 { assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index a0aeac6199299..156d793a0c972 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -79,9 +79,8 @@ &pcie_phy { &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index c557dbf4dcd60..0ce60ad9c7d50 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -120,9 +120,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 41d0de6a7027b..570992a52b759 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -142,9 +142,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 7761d5671cb13..1800c6a4b1fc6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -162,9 +162,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 64b366e83fa14..df3b2c93d2d58 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -702,9 +702,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index e8bc1fccc47be..c33ec6826d324 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -623,9 +623,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index acc2ba8e00a88..363020a08c9b8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -557,9 +557,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index eceed9816f5dc..93088fa1c3b9c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -618,9 +618,8 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 7e8b3b0fa3066..5b2493bb8dd93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -657,10 +657,6 @@ &pcie0 { assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, - <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; /* PCIE_1_RESET# (SODIMM 244) */ diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 04cf2c3c9928b..31f4548f85cfa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1302,6 +1302,10 @@ pcie0: pcie@33800000 { <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; From patchwork Mon Jan 16 10:14:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13102859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37A93C46467 for ; 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Mon, 16 Jan 2023 10:14:45 +0000 Received: from phobos.denx.de ([2a01:238:438b:c500:173d:9f52:ddab:ee01]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHMVm-009axf-8b for linux-arm-kernel@lists.infradead.org; Mon, 16 Jan 2023 10:14:44 +0000 Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 5772C85531; Mon, 16 Jan 2023 11:14:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1673864080; bh=r/qc0/3GEBwMpScdbbch/AyL2vpeceMJAmecu9nNDZQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kSJugi9oDhx1u1k675tygSfjzx01Pq/yYXvYFVlqlmMOX4yUhuSS0rAfMCl9YsspT nS3/TGLZvCpyyTnMFsdCunWcexWH1QzIbqXexNo/HoO7h9i9dO9SuDBp/VhXfA/cYj tlG6Y2Ta1X/iCrOvfyrj9hk4UtMzFRmrrL+I4gYYhCYLeu99O2kxvmyquox/5BDCeq pU6spNvDDg/05MZXLNs/LOBC8gMLGvNyDyU17/3/SzkorEXznkJhp4cfTCCQTbKEeF qiREBVbXCYoJdklXsRtwy1SoYYI76Jt15YbmK1edg6wgWH6Fy2Y8AMj7C6k1W+WcAP tzx9tYGxIrUJQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexander Stein , Fabio Estevam , Peng Fan , Richard Zhu , Shawn Guo , NXP Linux Team Subject: [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe clock-names property Date: Mon, 16 Jan 2023 11:14:22 +0100 Message-Id: <20230116101422.46257-2-marex@denx.de> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116101422.46257-1-marex@denx.de> References: <20230116101422.46257-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230116_021442_627929_4F7B94C6 X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Move the PCIe clock-names property from various DTs into SoC dtsi to reduce duplication. In case of a couple of boards, reorder the clock so they match the order in yaml DT bindings. Reviewed-by: Alexander Stein # imx8mq.dtsi, imx8mq-tqma8mq-mba8mx.dts Signed-off-by: Marek Vasut Reviewed-by: Richard Zhu --- Cc: Fabio Estevam Cc: Peng Fan Cc: Richard Zhu Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Alex - Add default pcie clock entry into dtsi - Fix the Ultra board V3: Rebase on latest next-20230116 --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 ++++------ .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 5 ++--- .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++++++++ 6 files changed, 28 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 78937910f4039..7507548cdb16b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -356,10 +356,9 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; vph-supply = <&vgen5_reg>; status = "okay"; }; @@ -369,10 +368,9 @@ &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; vpcie-supply = <®_pcie1>; vph-supply = <&vgen5_reg>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index a91c136797f60..6376417e918c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -245,20 +245,18 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; status = "okay"; }; /* Intel Ethernet Controller I210/I211 */ &pcie1 { clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; fsl,max-link-speed = <1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 055031bba8c4b..200268660518d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -197,10 +197,9 @@ &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index d7660eab68b94..344cfdaeb1d59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -105,10 +105,9 @@ &led2 { &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; epdev_on-supply = <®_vcc_3v3>; hard-wired = <1>; status = "okay"; @@ -120,10 +119,9 @@ &pcie0 { */ &pcie1 { clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; epdev_on-supply = <®_vcc_3v3>; hard-wired = <1>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 4e05120c62d41..74a7a589a3296 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -551,10 +551,9 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; vph-supply = <&vgen5_reg>; status = "okay"; }; @@ -564,10 +563,9 @@ &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; vph-supply = <&vgen5_reg>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index faed28e3ffa17..98fbba4c99a99 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1542,6 +1542,11 @@ pcie0: pcie@33800000 { <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, @@ -1579,6 +1584,11 @@ pcie1: pcie@33c00000 { <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,