From patchwork Mon Jan 16 10:53:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 13102907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 906EBC677F1 for ; Mon, 16 Jan 2023 10:53:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230402AbjAPKxZ (ORCPT ); Mon, 16 Jan 2023 05:53:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229863AbjAPKxW (ORCPT ); Mon, 16 Jan 2023 05:53:22 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FAAB6A46; Mon, 16 Jan 2023 02:53:15 -0800 (PST) X-UUID: f6cbfb40958b11ed945fc101203acc17-20230116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WVRQn0/z4/Txw4tds1T9p+ZOw4h5tZ0f/iFMTnbJITI=; b=Pj6hEWsfv9oRV4U2rOZYD6l4jaT5dTzEwB26ZnKI+aGzKPbg3ROGkhgk5NgRyCr2TgNlDsOfADYL/he+suWi+RjuZY2QHJ007jjMKjRL9NE9S0PC8Sa5zPF1I86VUFe3VuvyQzIj3KenYyiqCmqVP4/RU+4p/wlmYKPgKSeJW0w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:4a0b832a-bab0-49c3-8c4c-e05570b52d2d,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:3ca2d6b,CLOUDID:bb93638c-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: f6cbfb40958b11ed945fc101203acc17-20230116 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 814725318; Mon, 16 Jan 2023 18:53:09 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 16 Jan 2023 18:53:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 16 Jan 2023 18:53:07 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , CC: , , , , , Allen-KH Cheng Subject: [PATCH v2 1/2] dt-bindings: watchdog: mtk-wdt: Add reset-by-toprgu support Date: Mon, 16 Jan 2023 18:53:04 +0800 Message-ID: <20230116105305.31818-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230116105305.31818-1-allen-kh.cheng@mediatek.com> References: <20230116105305.31818-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org In some applications, the mtk-wdt requires the toprgu (TOP Reset Generation Unit) to reset timer after system resets. Add optional mediatek,reset-by-toprgu property to enable it. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index b3605608410c..b4de6b134ce1 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -52,6 +52,12 @@ properties: description: Disable sending output reset signal type: boolean + mediatek,reset-by-toprgu: + description: The top reset generate unit (toprgu) generates reset signals + and distributes them to each system. If present, means the watchdog + timer will reset by toprgu once system resets. + type: boolean + '#reset-cells': const: 1 From patchwork Mon Jan 16 10:53:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 13102906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0D50C63797 for ; Mon, 16 Jan 2023 10:53:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230418AbjAPKx0 (ORCPT ); Mon, 16 Jan 2023 05:53:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbjAPKxV (ORCPT ); Mon, 16 Jan 2023 05:53:21 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86BD5196B2; Mon, 16 Jan 2023 02:53:15 -0800 (PST) X-UUID: f74acf9c958b11ed945fc101203acc17-20230116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=4G8Y0ViVJzXb6BsOeFBPQvk3DHX0QfUnX0ejt3ACyfU=; b=kzEtSVn8Hu+INqkYtPtHDQ84mcUFru8ZQY4cxOv92Vqa6UWd0+OxRSpEFlYeHAbw0ZIeNiU8seI8zAokpPIEBbz1lSpH7zX6ct3IrOUZ7I+x9PqFEoFC4Y59a7FuUsYtUcSpFC0DpujVOqpVS5qRmYBo0xNX5FnFCmlIcgmC+pM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:07ba01da-45e7-47bd-b518-c0bbed90f295,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.18,REQID:07ba01da-45e7-47bd-b518-c0bbed90f295,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:3ca2d6b,CLOUDID:75a2c854-dd49-462e-a4be-2143a3ddc739,B ulkID:2301161853114L1JMK7F,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: f74acf9c958b11ed945fc101203acc17-20230116 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 886985106; Mon, 16 Jan 2023 18:53:10 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 16 Jan 2023 18:53:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 16 Jan 2023 18:53:08 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , CC: , , , , , Allen-KH Cheng Subject: [PATCH v2 2/2] watchdog: mtk_wdt: Add reset_by_toprgu support Date: Mon, 16 Jan 2023 18:53:05 +0800 Message-ID: <20230116105305.31818-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230116105305.31818-1-allen-kh.cheng@mediatek.com> References: <20230116105305.31818-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org In some cases, the MediaTek watchdog requires the toprgu to reset timer after system resets. Provide a reset_by_toprgu parameter for configuration. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 3e6212591e69..a9c437598e7e 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -50,6 +50,7 @@ #define WDT_MODE_IRQ_EN (1 << 3) #define WDT_MODE_AUTO_START (1 << 4) #define WDT_MODE_DUAL_EN (1 << 6) +#define WDT_MODE_CNT_SEL (1 << 8) #define WDT_MODE_KEY 0x22000000 #define WDT_SWRST 0x14 @@ -70,6 +71,7 @@ struct mtk_wdt_dev { spinlock_t lock; /* protects WDT_SWSYSRST reg */ struct reset_controller_dev rcdev; bool disable_wdt_extrst; + bool reset_by_toprgu; }; struct mtk_wdt_data { @@ -279,6 +281,8 @@ static int mtk_wdt_start(struct watchdog_device *wdt_dev) reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); if (mtk_wdt->disable_wdt_extrst) reg &= ~WDT_MODE_EXRST_EN; + if (mtk_wdt->reset_by_toprgu) + reg |= WDT_MODE_CNT_SEL; reg |= (WDT_MODE_EN | WDT_MODE_KEY); iowrite32(reg, wdt_base + WDT_MODE); @@ -408,6 +412,9 @@ static int mtk_wdt_probe(struct platform_device *pdev) mtk_wdt->disable_wdt_extrst = of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); + mtk_wdt->reset_by_toprgu = + of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu"); + return 0; }