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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 19:11:20.4402 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c6a856a-789c-4649-221c-08daf7f573ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6096 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Yazen Ghannam Add new error descriptions to extend existing SMCA error decoding functionality for modern AMD processors. Additionally, also reword some existing error descriptions and remove the unused ones. [avadnaik: Add error descriptions for MPDMA SMCA bank, rework the commit message] Signed-off-by: Yazen Ghannam Signed-off-by: Avadhut Naik --- drivers/edac/mce_amd.c | 53 ++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index cc5c63feb26a..869dcca5e2f4 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -192,24 +192,24 @@ static const char * const smca_ls2_mce_desc[] = { "A SystemReadDataError error was reported on read data returned from L2 for an SCB store", "A SystemReadDataError error was reported on read data returned from L2 for a WCB store", "A hardware assertion error was reported", - "A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access", + "A parity error was detected in an STLF, SCB EMEM entry, store data mask or SRB store data by any access", }; static const char * const smca_if_mce_desc[] = { - "Op Cache Microtag Probe Port Parity Error", + "Op Cache Microtag Parity Error", "IC Microtag or Full Tag Multi-hit Error", "IC Full Tag Parity Error", "IC Data Array Parity Error", - "Decoupling Queue PhysAddr Parity Error", + "PRQ Parity Error", "L0 ITLB Parity Error", - "L1 ITLB Parity Error", - "L2 ITLB Parity Error", + "L1-TLB Parity Error", + "L2-TLB Parity Error", "BPQ Thread 0 Snoop Parity Error", "BPQ Thread 1 Snoop Parity Error", - "L1 BTB Multi-Match Error", - "L2 BTB Multi-Match Error", + "BP L1-BTB Multi-Hit Error", + "BP L2-BTB Multi-Hit Error", "L2 Cache Response Poison Error", - "System Read Data Error", + "L2 Cache Error Response", "Hardware Assertion Error", "L1-TLB Multi-Hit", "L2-TLB Multi-Hit", @@ -222,12 +222,13 @@ static const char * const smca_l2_mce_desc[] = { "L2M Tag or State Array ECC Error", "L2M Data Array ECC Error", "Hardware Assert Error", + "SDP Read Response Parity Error", }; static const char * const smca_de_mce_desc[] = { - "Micro-op cache tag parity error", - "Micro-op cache data parity error", - "Instruction buffer parity error", + "Micro-op cache tag array parity error", + "Micro-op cache data array parity error", + "IBB Register File parity error", "Micro-op queue parity error", "Instruction dispatch queue parity error", "Fetch address FIFO parity error", @@ -247,7 +248,7 @@ static const char * const smca_ex_mce_desc[] = { "Checkpoint queue parity error", "Retire dispatch queue parity error", "Retire status queue parity error", - "Scheduling queue parity error", + "Scheduler queue parity error", "Branch buffer queue parity error", "Hardware Assertion error", "Spec Map parity error", @@ -262,6 +263,7 @@ static const char * const smca_fp_mce_desc[] = { "Retire queue (RQ) parity error", "Status register file (SRF) parity error", "Hardware assertion", + "Physical K mask register file (KRF) parity error", }; static const char * const smca_l3_mce_desc[] = { @@ -270,9 +272,10 @@ static const char * const smca_l3_mce_desc[] = { "L3M Tag ECC Error", "L3M Tag Multi-way-hit Error", "L3M Data ECC Error", - "SDP Parity Error or SystemReadDataError from XI", - "L3 Victim Queue Parity Error", + "SDP Parity Error from XI", + "L3 Victim Queue Data Fabric Error", "L3 Hardware Assertion", + "XI WCB Parity Poison Creation Event", }; static const char * const smca_cs_mce_desc[] = { @@ -302,6 +305,10 @@ static const char * const smca_cs2_mce_desc[] = { "SDP read response had an unexpected RETRY error", "Counter overflow error", "Counter underflow error", + "Illegal Request on the no data channel", + "Address Violation on the no data channel", + "Security Violation on the no data channel", + "Hardware Assert Error", }; static const char * const smca_pie_mce_desc[] = { @@ -309,7 +316,9 @@ static const char * const smca_pie_mce_desc[] = { "Register security violation", "Link Error", "Poison data consumption", - "A deferred error was detected in the DF" + "A deferred error was detected in the DF", + "Watch Dog Timer", + "An SRAM ECC error was detected in the CNLI block", }; static const char * const smca_umc_mce_desc[] = { @@ -321,6 +330,10 @@ static const char * const smca_umc_mce_desc[] = { "Write data CRC error", "DCQ SRAM ECC error", "AES SRAM ECC error", + "ECS Row Error", + "ECS Error", + "UMC Throttling Error", + "Read CRC Error", }; static const char * const smca_umc2_mce_desc[] = { @@ -443,17 +456,12 @@ static const char * const smca_mpdma_mce_desc[] = { "MPDMA TVF SDP Master Memory 4 ECC or parity error", "MPDMA TVF SDP Master Memory 5 ECC or parity error", "MPDMA TVF SDP Master Memory 6 ECC or parity error", + "SDP Watchdog Timer expired", "MPDMA PTE Command FIFO ECC or parity error", "MPDMA PTE Hub Data FIFO ECC or parity error", "MPDMA PTE Internal Data FIFO ECC or parity error", "MPDMA PTE Command Memory DMA ECC or parity error", "MPDMA PTE Command Memory Internal ECC or parity error", - "MPDMA PTE DMA Completion FIFO ECC or parity error", - "MPDMA PTE Tablewalk Completion FIFO ECC or parity error", - "MPDMA PTE Descriptor Completion FIFO ECC or parity error", - "MPDMA PTE ReadOnly Completion FIFO ECC or parity error", - "MPDMA PTE DirectWrite Completion FIFO ECC or parity error", - "SDP Watchdog Timer expired", }; static const char * const smca_nbio_mce_desc[] = { @@ -461,7 +469,8 @@ static const char * const smca_nbio_mce_desc[] = { "PCIE error", "SDP ErrEvent error", "SDP Egress Poison Error", - "IOHC Internal Poison Error", + "Internal Poison Error", + "Internal system fatal error event", }; static const char * const smca_pcie_mce_desc[] = { From patchwork Mon Jan 16 19:11:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naik, Avadhut" X-Patchwork-Id: 13103586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE420C54EBE for ; Mon, 16 Jan 2023 19:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233076AbjAPTLm (ORCPT ); Mon, 16 Jan 2023 14:11:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232813AbjAPTLk (ORCPT ); Mon, 16 Jan 2023 14:11:40 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EA482A173; 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Mon, 16 Jan 2023 19:11:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT085.mail.protection.outlook.com (10.13.174.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.13 via Frontend Transport; Mon, 16 Jan 2023 19:11:36 +0000 Received: from onyx-7400host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 16 Jan 2023 13:11:35 -0600 From: Avadhut Naik To: , CC: , , , , Subject: [PATCH v1 2/3] x86/MCE/AMD: Add HWID Fixup for PCS_XGMI SMCA Date: Mon, 16 Jan 2023 19:11:01 +0000 Message-ID: <20230116191102.4226-3-avadnaik@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116191102.4226-1-avadnaik@amd.com> References: <20230116191102.4226-1-avadnaik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT085:EE_|DS7PR12MB8345:EE_ X-MS-Office365-Filtering-Correlation-Id: ae6a2550-cbcc-44df-5fd4-08daf7f57d41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 19:11:36.5112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae6a2550-cbcc-44df-5fd4-08daf7f57d41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8345 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On AMD systems, during Scalable MCA (SMCA) initialization, the HWID and McaType tuple, read from MCA_IPID register of a SMCA bank type, is used by the kernel for populating the per-CPU smca_banks array. This very array is, in turn being utilized by the edac_mce_amd module for determining the SMCA bank type while decoding a machine check error. However, on some AMD CPUs, the HWID read from the MCA_IPID register for XGMI Controller SMCA bank type does not match the value expected by the kernel. Consequently, the smca_banks array is not populated for the bank type resulting in the machine check errors on the bank type not being decoded. As a solution, set the HWID, obtained from the MCA_IPID register, of the XGMI Controller SMCA bank type on affected CPUs, to the value expected by the kernel to ensure that the machine check errors on the bank type are correctly decoded. Signed-off-by: Avadhut Naik --- arch/x86/kernel/cpu/mce/amd.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 23c5072fbbb7..b0cce0ce056c 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -249,6 +249,30 @@ static void default_deferred_error_interrupt(void) } void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; +/* + * Errata encountered on AMD CPUs for some SMCA bank types requires fixup + * of HWID, read from MCA_IPID register, for accurate SMCA error decoding. + */ +static inline void fixup_hwid(unsigned int *hwid_mcatype) +{ + struct cpuinfo_x86 *c = &boot_cpu_data; + + if (c->x86 == 0x19) { + switch (c->x86_model) { + /* + * Handle discrepancy in HWID of kernel and MCA_IPID register + * for XGMI Controller SMCA bank type + */ + case 0x30 ... 0x3F: + if (*hwid_mcatype == HWID_MCATYPE(0x80, 0x0)) + *hwid_mcatype = HWID_MCATYPE(0x50, 0x0); + break; + default: + break; + } + } +} + static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) { u32 low, high; @@ -321,6 +345,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, (high & MCI_IPID_MCATYPE) >> 16); + fixup_hwid(&hwid_mcatype); + for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { s_hwid = &smca_hwid_mcatypes[i]; From patchwork Mon Jan 16 19:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naik, Avadhut" X-Patchwork-Id: 13103587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3276BC46467 for ; Mon, 16 Jan 2023 19:12:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232509AbjAPTMC (ORCPT ); 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Mon, 16 Jan 2023 13:11:46 -0600 From: Avadhut Naik To: , CC: , , , , Subject: [PATCH v1 3/3] x86/MCE/AMD: Handle reassigned bit definitions for CS SMCA Date: Mon, 16 Jan 2023 19:11:02 +0000 Message-ID: <20230116191102.4226-4-avadnaik@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116191102.4226-1-avadnaik@amd.com> References: <20230116191102.4226-1-avadnaik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT044:EE_|DM8PR12MB5447:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d542fdc-aaf7-4323-92c5-08daf7f5843f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ot6Ll6CSWD9DQ9FzQk1JpCsnDObNQDv9zxFpdeIDjvTUaFzLh4vf+La0B+WI12KZTmlEsateRTwYl8SNXDPHqnUygxZglNvlfxOSEg5Ypq8mdGcm+/be2ToVo/IeLpGWGoBpUUEZoeJDzlwxT9RxzHJHKSIZCYf+vYfHW0HzSI2iUCnGlG9xJWQlvc9XwnUyD+k0Rn1SW8LSYvWD/ps7bfsJFhLMKoSTyr9rccog3KXjZ0SmRhCw6NNDBpNLJhtDt5UIec2kDml5BjanDUpP86Aj7haNETG3fuqXKgtae09lLiQji3Jd9j4f8xZmorI6LXboPN6hvB7+hZZ8YTxD3ujDK+aVSgnHrePSlwysmIUesdiEKjGNvFgb9La2rCzbUXJFuZRsqgJjSCvdskD7ZQaMwD8LlOQ5yuhl6mfjF/TljH2j8Ckn3ZO2rCF7A8BfBp46vmb8oHeUAQ58eMAuAV5G/uTRxHr8K0yXc4AcwO9R3sa0/4zbgdDM6VzZgzeptLsS72GQfOe6vRXsHNcPj1+Ho5e/qaULs09ZR+xpf1dMwg3g9tonbOWz40Jczh4TY1x+ecwFtYa7mTePO+YP9ZTt/yhqPXnhshay9cYGEIPdnNK9ZzQIVLtxpXXEk+Kq66e0WyhSfE/ZixwfujpCCx5FT01RGFpyXnrTUlbDU8MRBgM9/gCXH8NwFyZDyTihzWgeZFMYXdpyhEsW8DXV4YG5YPuPcU1Bo+9rPrxpJ9U= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(36756003)(8936002)(356005)(70206006)(4326008)(70586007)(8676002)(5660300002)(2906002)(81166007)(83380400001)(82740400003)(36860700001)(478600001)(316002)(40460700003)(7696005)(6666004)(110136005)(54906003)(40480700001)(82310400005)(41300700001)(47076005)(1076003)(426003)(336012)(26005)(2616005)(16526019)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 19:11:47.9778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d542fdc-aaf7-4323-92c5-08daf7f5843f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5447 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Currently, on AMD systems with Scalable MCA (SMCA), each machine check error of a SMCA bank type has an associated bit position in the bank's control (CTL) register used for enabling / disabling reporting of the very error. An error's bit position in the CTL register is also used during error decoding for offsetting into the corresponding bank's error description structure. As new errors are being added in newer AMD systems for existing SMCA bank types, the underlying SMCA architecture guarantees that the bit positions of existing errors are not altered. However, on some AMD systems viz. Genoa, some of the existing bit definitions in the CTL register of the Coherent Slave (CS) SMCA bank type are reassigned without defining new HWID and McaType. Consequently, the very errors whose bit definitions have been reassigned in the CTL register are being erroneously decoded. As a solution, create a new software defined SMCA bank type by utilizing one of the hardware-reserved values for HWID. The new SMCA bank type will only be employed for CS error decoding on affected CPU models. Additionally, since the existing error description structure for the CS SMCA bank type is still valid, add new error description structure to compensate for the reassigned bit definitions. Signed-off-by: Avadhut Naik --- arch/x86/include/asm/mce.h | 1 + arch/x86/kernel/cpu/mce/amd.c | 24 +++++++++++++++++++++++- drivers/edac/mce_amd.c | 26 ++++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 9646ed6e8c0b..d0442b4147b5 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -308,6 +308,7 @@ enum smca_bank_types { SMCA_L3_CACHE, /* L3 Cache */ SMCA_CS, /* Coherent Slave */ SMCA_CS_V2, + SMCA_CS_V2_QUIRK, SMCA_PIE, /* Power, Interrupts, etc. */ SMCA_UMC, /* Unified Memory Controller */ SMCA_UMC_V2, diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index b0cce0ce056c..317307772048 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -101,7 +101,7 @@ static struct smca_bank_name smca_names[] = { [SMCA_EX] = { "execution_unit", "Execution Unit" }, [SMCA_FP] = { "floating_point", "Floating Point Unit" }, [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, - [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, + [SMCA_CS ... SMCA_CS_V2_QUIRK] = { "coherent_slave", "Coherent Slave" }, [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, /* UMC v2 is separate because both of them can exist in a single system. */ @@ -178,6 +178,8 @@ static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, + /* Software defined SMCA bank type to handle erratum 1384*/ + { SMCA_CS_V2_QUIRK, HWID_MCATYPE(0x0, 0x1) }, /* Unified Memory Controller MCA type */ { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, @@ -259,6 +261,17 @@ static inline void fixup_hwid(unsigned int *hwid_mcatype) if (c->x86 == 0x19) { switch (c->x86_model) { + /* + * Per Genoa's revision guide, erratum 1384, some SMCA Extended + * Error Codes and SMCA Control bits are incorrect for SMCA CS + * bank type. + */ + case 0x10 ... 0x1F: + case 0x60 ... 0x7B: + case 0xA0 ... 0xAF: + if (*hwid_mcatype == HWID_MCATYPE(0x2E, 0x2)) + *hwid_mcatype = HWID_MCATYPE(0x0, 0x1); + break; /* * Handle discrepancy in HWID of kernel and MCA_IPID register * for XGMI Controller SMCA bank type @@ -270,6 +283,15 @@ static inline void fixup_hwid(unsigned int *hwid_mcatype) default: break; } + } else if (c->x86 == 0x1A) { + switch (c->x86_model) { + case 0x40 ... 0x4F: + if (*hwid_mcatype == HWID_MCATYPE(0x2E, 0x2)) + *hwid_mcatype = HWID_MCATYPE(0x0, 0x1); + break; + default: + break; + } } } diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 869dcca5e2f4..0586356475fd 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -311,6 +311,31 @@ static const char * const smca_cs2_mce_desc[] = { "Hardware Assert Error", }; +/* + * Per Genoa's revision guide, erratum 1384, existing bit definitions + * are reassigned for SMCA CS bank type. + */ +static const char * const smca_cs2_quirk_mce_desc[] = { + "Illegal Request", + "Address Violation", + "Security Violation", + "Illegal Response", + "Unexpected Response", + "Request or Probe Parity Error", + "Read Response Parity Error", + "Atomic Request Parity Error", + "SDP read response had no match in the CS queue", + "SDP read response had an unexpected RETRY error", + "Counter overflow error", + "Counter underflow error", + "Probe Filter Protocol Error", + "Probe Filter ECC Error", + "Illegal Request on the no data channel", + "Address Violation on the no data channel", + "Security Violation on the no data channel", + "Hardware Assert Error", +}; + static const char * const smca_pie_mce_desc[] = { "Hardware Assert", "Register security violation", @@ -602,6 +627,7 @@ static struct smca_mce_desc smca_mce_descs[] = { [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) }, [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) }, [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) }, + [SMCA_CS_V2_QUIRK] = { smca_cs2_quirk_mce_desc, ARRAY_SIZE(smca_cs2_quirk_mce_desc)}, [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) }, [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) }, [SMCA_UMC_V2] = { smca_umc2_mce_desc, ARRAY_SIZE(smca_umc2_mce_desc) },